Finite Field Arithmetic Research Articles

High-performance elliptic curve cryptoprocessors over $$\varvec{GF(2^{m})}$$ G F ( 2 m ) on Koblitz curves

Efficient computation of the finite field arithmetic is required for elliptic curve cryptography over $$G\!F\!(2^{m})$$GF(2m). In order to achieve the above, this paper presents the design of high-performance cryptoprocessors over $$G\!F\!(2^{163})$$GF(2163) and $$G\!F\!(2^{233})$$GF(2233) using finite field multipliers with digit-level processing. The arithmetic operations were implemented in hardware using Gaussian normal bases representation and the scalar point multiplication kP was performed on Koblitz curves using window-$$\tau $$?NAF algorithm with w = 2, 4 and 8. The cryptoprocessors were designed using VHDL description, synthesized on the FPGA Stratix-V using Quartus II 13.0, and verified using ModelSIM and Matlab. The simulation results show that the cryptoprocessors present a very good performance using low area. In this case, the processing times for calculating the scalar point multiplication over $$G\!F\!(2^{163})$$GF(2163) and $$G\!F\!(2^{233})$$GF(2233) for w = 2, 4 and 8 were 9.1, 6.7 and 5.1, and 12.9, 9.5 and 6.8 $$\upmu $$μs, respectively.

High-Throughput Low-Complexity Systolic Montgomery Multiplication Over <inline-formula><tex-math notation="LaTeX">$GF(2^{m})$</tex-math></inline-formula> Based on Trinomials

Cryptographic computation exploits finite field arithmetic and, in particular, multiplication. Lightweight and fast implementations of such arithmetic are necessary for many sensitive applications. This brief proposed a low-complexity systolic Montgomery multiplication over $GF(2^{m})$ . Our complexity analysis shows that the area complexity of the proposed architecture is reduced compared with the previous work. This has also been confirmed through our application-specific integrated circuit area and time equivalent estimations and implementations. Hence, the proposed architecture appears to be very well suited for high-throughput low-complexity cryptographic applications.

Error Detection Mechanism Based On Bch Decoder And Root Finding Of Polynomial Over Finite Fields

Error Correction Code is very important in modern communication systems. BCH (Bose, Chaudhuri, and Hocqunghem) codes are being widely used in variety communication and storage systems. In this paper the construction and decoding BCH codes which are based on finite field arithmetic is introduced and also an improved algorithm for finding roots of polynomials over finite fields is proposed. This makes possible significant speed up of the decoding process of BCH codes.

Study of Modular Multiplication Methods for Embedded Processors

The improvements of embedded processors make future technologies including wireless sensor network and internet of things feasible. These applications firstly gather information from target field through wireless network. However, this networking process is highly vulnerable to malicious attacks including eavesdropping and forgery. In order to ensure secure and robust networking, information should be kept in secret with cryptography. Well known approach is public key cryptography and this algorithm consists of finite field arithmetic. There are many works considering high speed finite field arithmetic. One of the famous approach is Montgomery multiplication. In this study, we investigated Montgomery multiplication for public key cryptography on embedded microprocessors. This paper includes helpful information on Montgomery multiplication implementation methods and techniques for various target devices including 8-bit and 16-bit microprocessors. Further, we expect that the results reported in this paper will become part of a reference book for advanced Montgomery multiplication methods for future researchers.

Accelerating elliptic curve scalar multiplication over [formula omitted] on graphic hardwares

In this paper, we present PEG (Parallel ECC library on GPU), which is efficient implementation of Elliptic Curve Scalar Multiplication over GF(2m) on Graphic Processing Units. While existing ECC implementations over GPU focused on limited parameterizations such as (fixed scalar and different curves) or (different scalars and same base point), PEG covers all parameter options ((a) fixed scalar and variable points, (b) random scalars and fixed input point, and (c) random scalars and variable points) which are used for ECC-based protocols such as ECDH, ECDSA and ECIES. With GPU optimization concerns and through analyzing parameter types used for ECC-based protocols, we investigate promising algorithms at both finite field arithmetic and scalar multiplication level for performance optimization according to each parameterization. PEG covers ECC implementations over GF(2163), GF(2233) and GF(2283) for 80-bit, 112-bit and 128-bit security on GTX285 and GTX480. PEG can achieve remarkable performance compared with MIRACL, one of the most famous ECC library, running on Intel i7 CPU (2.67 GHz).

On the Capacity of the Finite Field Counterparts of Wireless Interference Networks

This paper explores how degrees of freedom (DoF) results from wireless networks can be translated into capacity or linear capacity results for their finite field counterparts that arise in network coding applications. The main insight is that scalar (SISO) finite field channels over \(\mathbb {F}_{\!p^n}\) are analogous to \(n\times n\) vector (MIMO) channels in the wireless setting, but with an important distinction—there is additional structure due to finite field arithmetic, which enforces commutativity of matrix multiplication and limits the channel diversity to \(n\) , making these channels similar to diagonal channels in the wireless setting. Within the limits imposed by the channel structure, the DoF optimal precoding solutions for wireless networks can be translated into capacity or linear capacity optimal solutions for their finite field counterparts. This is shown through the study of capacity of the 2-user X channel and linear capacity of the 3-user interference channel. Besides bringing the insights from wireless networks into network coding applications, the study of finite field networks over \(\mathbb {F}_{\!p^n}\) also touches upon important open problems in wireless networks (finite SNR, finite diversity scenarios) through interesting parallels between \(p\) and SNR, and \(n\) and diversity.

Improving the computational efficiency of modular operations for embedded systems

Abstract Security protocols such as IPSec, SSL and VPNs used in many communication systems employ various cryptographic algorithms in order to protect the data from malicious attacks. Thanks to public-key cryptography, a public channel which is exposed to security risks can be used for secure communication in such protocols without needing to agree on a shared key at the beginning of the communication. Public-key cryptosystems such as RSA, Rabin and ElGamal cryptosystems are used for various security services such as key exchange and key distribution between communicating nodes and many authentication protocols. Such public-key cryptosystems usually depend on modular arithmetic operations including modular multiplication and exponentiation. These mathematical operations are computationally intensive and fundamental arithmetic operations which are intensively used in many fields including cryptography, number theory, finite field arithmetic, and so on. This paper is devoted to the analysis of modular arithmetic operations and the improvement of the computation of modular multiplication and exponentiation from hardware design perspective based on FPGA. Two of the well-known algorithms namely Montgomery modular multiplication and Karatsuba algorithms are exploited together within our high-speed pipelined hardware architecture. Our proposed design presents an efficient solution for a range of applications where area and performance are both important. The proposed coprocessor offers scalability which means that it supports different security levels with a cost of performance. We also build a system-on-chip design using Xilinx’s latest Zynq-7000 family extensible processing platform to show how our proposed design improve the processing time of modular arithmetic operations for embedded systems.

A Survey on Normal Bases Over Finite Fields

Normal bases are important in efficient implementation of finite field arithmetic for many applications in coding theory and cryptography. This paper gives a survey on various topics of normal bases including basic properties of normal elements, primitive normal bases, dual and self-dual normal bases, fast arithmetic under normal bases, and constructions for low complexity normal bases.

High-Performance Implementation of Point Multiplication on Koblitz Curves

Fast and high-performance computation of finite-field arithmetic is crucial for elliptic curve cryptography (ECC) over binary extension fields. In this brief, we propose a highly parallel scheme to speed up the point multiplication for high-speed hardware implementation of ECC cryptoprocessor on Koblitz curves. We slightly modify the addition formulation in order to employ four parallel finite-field multipliers in the data flow. This reduces the latency of performing point addition and speeds up the overall point multiplication. To the best of our knowledge, the proposed data flow of point addition has the lowest latency in comparison to the counterparts available in the literature. To make the cryptoprocessor more efficient, we employ a low-complexity and efficient digit-level Gaussian normal basis multiplier to perform lower level finite-field multiplications. Finally, we have implemented our proposed architecture for point multiplication on an Altera Stratix II field-programmable gate array and obtained the results of timing and area.

Indices Isotypiques des Éléments Cyclotomiques

Given $F$ a real abelian field, $p$ an odd prime and $\chi$ any Dirichlet character of $F$ we give a method for computing the $\chi$-index $\displaystyle \left (H^1(G_S,\mathbb{Z}_p(r))^\chi: C^F(r)^\chi\right)$ where the Tate twist $r$ is an odd integer $r\geq 3$, the group $C^F(r)$ is the group of higher circular units, $G_S$ is the Galois group over $F$ of the maximal $S$ ramified algebraic extension of $F$, and $S$ is the set of places of $F$ dividing $p$. This $\chi$-index can now be computed in terms only of elementary arithmetic of finite fields $\FM_\ell$. Our work generalizes previous results by Kurihara who used the assumption that the order of $\chi$ divides $p-1$.

Digit-Level Semi-Systolic and Systolic Structures for the Shifted Polynomial Basis Multiplication Over Binary Extension Fields

Finite field multiplication is one of the most important operations in the finite field arithmetic. In this paper, we study semi-systolic and systolic implementations of the shifted polynomial basis multiplication and propose low time complexity semi-systolic and systolic array structures. We show that our proposed semi-systolic multiplier is faster than its existing counterparts available in the literature. Our application-specified integrated circuit (ASIC) implementation of the proposed semi-systolic multiplier demonstrates that reduction in time complexity is achieved without imposing hardware overhead. Furthermore, our proposed systolic array shifted polynomial basis (SPB) multiplier has a low time complexity for general irreducible polynomials.

Non-XOR approach for low-cost bit-parallel polynomial basis multiplier over GF(2 m )

Finite field arithmetic has been widely used in many cryptosystems, particularly in the elliptic curve cryptosystem (ECC) and the advanced encryption standard (AES) as a method for speeding up their encryption/decryption processes. Low-cost design for finite field arithmetic is more attractive for various mobile applications. It is a factor that a large number of Exclusive OR (XOR) gates have been used in the arithmetic operations under the traditional finite field arithmetic implementation. Thus, the cost of the traditional finite field arithmetic cannot be effectively lowered, because a typical XOR gate design consists of 12 transistors. To address this, a novel non-XOR approach consisting of eight transistors, for realising low-cost polynomial basis (PB) multiplier over GF(2 m ) was developed in this study. The authors proposed that non-XOR architecture for bit-parallel PB multiplier uses the multiplexer function instead of the traditional XOR function in its design. Based on the proposed non-XOR methodology, three popular low-cost irreducible polynomials - trinomial, pentanomial and all-one-polynomial - are proposed and designed in this study. The results indicate that the proposed non-XOR architecture can reduce space complexity by 22-, compared with that of the traditional design.

Concurrent Error Detection in Montgomery Multiplication over Binary Extension Fields

Multiplication is one of the most important operations in finite field arithmetic. It is used in cryptographic and coding applications, such as elliptic curve cryptography and Reed-Solomon codes. In this paper, we consider the finite field multiplication used in elliptic curve cryptography and design concurrent error detection circuits. It is shown in the literature that the Montgomery multiplication can be used in cryptography to accelerate the scalar multiplication. Here, we use a parity-based concurrent error detection approach to increase the reliability of different Montgomery multipliers available in the literature. First, we consider bit-serial Montgomery multiplication and propose an error detection circuit. Then, we apply the same technique on the digit-serial Montgomery multiplication. Finally, we consider low time-complexity bit-parallel Montgomery multiplication and design the required components to implement the concurrent error detection circuits. ASIC implementations have been completed to analyze the time and area overheads of the proposed schemes. Also, the error detection capability is investigated by software simulations. We show that our approach results in efficient error detection schemes with small time and area overheads.

Learning a Skill-Teaching Curriculum with Dynamic Bayes Nets

We propose an intelligent tutoring system that constructs a curriculum of hints and problems in order to teach a student skills with a rich dependency structure. We provide a template for building a multi-layered Dynamic Bayes Net to model this problem and describe how to learn the parameters of the model from data. Planning with the DBN then produces a teaching policy for the given domain. We test this end-to-end curriculum design system in two human-subject studies in the areas of finite field arithmetic and artificial language and show this method performs on par with hand-tuned expert policies.

A Word-Level Finite Field Multiplier Using Normal Basis

Hardware implementations of finite field arithmetic using normal basis are advantageous due to the fact that the squaring operation can be done at almost no cost. In this paper, a new word-level finite field multiplier using normal basis is proposed. The proposed architecture takes d clock cycles to compute the product bits, where the value for d, 1 ≤ d ≤ m, can be arbitrarily selected by the designer to set the tradeoff between area and speed. When there exists an optimal normal basis, it is shown that the proposed design has a smaller critical path delay than other word-level normal basis multipliers found in the literature, while its circuit complexities are moderate and comparable to the others. Different word size multipliers were implemented in hardware, and implementation results are also presented.

Faster MapToPoint on Supersingular Elliptic Curves in Characteristic 3

Pairing-based cryptosystems are generally constructed using many functions such as pairing computation, arithmetic in finite fields, and arithmetic on elliptic curves. MapToPoint, which is a hashing algorithm onto an elliptic curve point, is one of the functions for constructing pairing-based cryptosystems. There are two MapToPoint algorithms on supersingular elliptic curves in characteristic three, which is used by ηT pairing. The first is computed by using a square root computation in F3m, and the computational cost of this algorithm is O(log m) multiplications in F3m. The second is computed by using an (m-1)×(m-1) matrix over F3. It can be computed by O(1) multiplications in F3m. However, this algorithm needs the off-line memory to store about m F3m-elements. In this paper, we propose an efficient MapToPoint algorithm on the supersingular elliptic curves in characteristic three by using 1/3-trace over F3m. We propose 1/3-trace over F3m, which can compute solution x of x3-x=c by using no multiplication in F3m. The proposed algorithm is computed by O(1) multiplications in F3m, and it requires less than m F3-elements to be stored in the off-line memory to efficiently compute trace over F3m. Moreover, in our software implementation of F3509, the proposed MapToPoint algorithm is approximately 35% faster than the conventional MapToPoint algorithm using the square root computation on an AMD Opteron processor (2.2GHz).

Sparse interpolation of multivariate rational functions

Consider the black box interpolation of a τ-sparse, n-variate rational function f, where τ is the maximum number of terms in either numerator or denominator. When numerator and denominator are at most of degree d, then the number of possible terms in f is O(dn) and explodes exponentially as the number of variables increases. The complexity of our sparse rational interpolation algorithm does not depend exponentially on n anymore. It still depends on d because we densely interpolate univariate auxiliary rational functions of the same degree. We remove the exponent n and introduce the sparsity τ in the complexity by reconstructing the auxiliary function’s coefficients via sparse multivariate interpolation.The approach is new and builds on the normalization of the rational function’s representation. Our method can be combined with probabilistic and deterministic components from sparse polynomial black box interpolation to suit either an exact or a finite precision computational environment. The latter is illustrated with several examples, running from exact finite field arithmetic to noisy floating point evaluations. In general, the performance of our sparse rational black box interpolation depends on the choice of the employed sparse polynomial black box interpolation. If the early termination Ben-Or/Tiwari algorithm is used, our method achieves rational interpolation in O(τd) black box evaluations and thus is sensitive to the sparsity of the multivariate f.

Concurrent error detection and correction in a polynomial basis multiplier over GF (2 m )

Finite-field arithmetic has been widely used to speed up the encryption and decryption processes in many cryptosystems, especially elliptic curve cryptosystems. Regular finite-field arithmetic structures are suitable for very large-scale integration implementation of cryptosystems, making them attractive for mobile commerce applications. Multiplication is the critical operation in finite-field arithmetic operations. Fault-based cryptanalysis is a new cryptanalysis method that deliberately injects faults into cryptographic devices, and requires only a small amount of side-channel information to break common ciphers. Thus, effective and simple methods for protecting the encryption/decryption circuitry from attackers are required to ensure that cryptographic devices can produce accurate signatures. This study presents a polynomial basis (PB) multiplier over GF(2m) with concurrent error detection (CED), and proposes a PB multiplier with concurrent error correction (CEC). A parallel structure of function cells is used in the proposed multiplier array to reduce the propagation delay. The proposed PB multiplier with internal parallel structure can reduce the time complexity by 28%, and reduce the space complexity by 90%, compared with existing PB multipliers. Compared with existing PB multipliers with CED, the proposed device with CED has a 20% greater space complexity but a 30% less time complexity. To the author's knowledge, there is no previous report of PB multipliers with CEC capability. The proposed PB multiplier with CEC capability has a space complexity of only about 10% more and requires five more clock cycles than the proposed device without CEC capability.

On hardware and software implementation of arithmetic in finite fields of characteristic 7 for calculation of pairings

We study scheme (hardware) and program (software) methods of multiplication of polynomials over fields of characteristic 7 in order to apply them to pairing-based cryptographic protocols on hyperelliptic curves of genus three. We consider hardware and software implementations of arithmetic in GF(7), GF(72), GF(7 n ), GF(77n ), and GF(714n ) and estimate the complexity of corresponding schemes and programs.

Efficient implementation of elliptic curve cryptography in wireless sensors

The deployment of cryptography in sensor networks is a challenging task, given the limited computational power and the resource-constrained nature of the sensoring devices. This paper presents the implementation of elliptic curve cryptography in the MICAz Mote, a popular sensor platform. We present optimization techniques for arithmetic in binary fields, including squaring, multiplication and modular reduction at two different security levels. Our implementation of field multiplication and modular reduction algorithms focuses on the reduction of memory accesses and appears as the fastest result for this platform. Finite field arithmetic was implemented in C and Assembly and elliptic curve arithmetic was implemented in Koblitz and generic binary curves. We illustrate the performance of our implementation with timings for key agreement and digital signature protocols. In particular, a key agreement can be computed in 0.40 seconds and a digital signature can be computed and verified in 1 second at the 163-bit security level. Our results strongly indicate that binary curves are the most efficient alternative for the implementation of elliptic curve cryptography in this platform.