Fine-pitch Interconnection Research Articles

Size Effects of Au/Ni-Coated Polymer Particles on the Electrical Performance of Anisotropic Conductive Adhesive Films under Flexible Mechanical Conditions.

In soft electronics, anisotropic conductive adhesive films (ACFs) are the trending interconnecting approach due to their substantial softness and superior bondability to flexible substrates. However, low bonding pressure (≤1 MPa) and fine-pitch interconnections of ACFs become challenging while being extended in advanced device developments such as wafer-level packaging and three-dimensional multi-layer integrated circuit board assembly. To overcome these difficulties, we studied two types of ACFs with distinct conductive filler sizes (ACF-1: ~20 μm and ACF-2: ~5 μm). We demonstrated a low-pressure thermo-compression bonding technique and investigated the size effect of conductive particles on ACF's mechanical properties in a customized testing device, which consists of flexible printing circuits and Flex on Flex assemblies. A consistency of low interconnection resistance (<1 Ω) after mechanical stress (cycling bending test up to 600 cycles) verifies the assembly's outstanding electrical reliability and mechanical stability and thus validates the great effectiveness of the ACF bonding technique. Additionally, in numerical studies using the finite element method, we developed a generic model to disclose the size effect of Au/Ni-coated polymer fillers in ACF on device reliability under mechanical stress. For the first time, we confirmed that ACFs with smaller filler particles are more prone to coating fracture, leading to deteriorated electrical interconnections, and are more likely to peel off from substrate electrode pads resulting in electrical faults. This study provides guides for ACF design and manufacturing and would facilitate the advancement of soft wearable electronic devices.

20 μm Copper Micro-Bump Bonding Through a Silver Metallization for Advanced Packaging Under a Low Pressure Condition

In this work, we proposed a copper (Cu) microbump bonding strategy by using a silver (Ag) metallization layer as an interconnect bridge. Si chips with 20 μm Cu-Ag bumps were bonded under a low pressure (0.4 MPa) and atmospheric conditions at 250 °C. By investigating the surface morphology evolution of the Cu-Ag bump, it is found that severe surface deformation caused by Ag abnormal grain growth and hillock generation plays a critical role in the Cu-Ag bump bonding, which facilitates the approach and bonding of top and bottom Ag surface of the bump structure. Moreover, this bonding strategy is expected to be particularly advantageous for finepitch interconnect applications. It not only mitigates the severe bonding condition requirements that are used in thermal compression bonding and hybrid bonding, but also provides higher quality bonding structures for advanced packaging.

Understanding the Contact Resistance in an ACF Bonding

Anisotropic Conductive Film (ACF) bonding, the technique of choice for display interconnects, allows very fine pitch interconnect at a moderate process temperature, typically at the expense of a non-negligible interconnect resistance. Modern ACFs have conducting particles in a thin layer of highviscosity adhesive. This allows even finer pitch but comes at the risk of high interconnect resistance due to trapped adhesive between pad and conductive particle. Conductive particles with spikes are designed to penetrate such a trapped adhesive layer. In this paper, we compare spiky conductive particles with the traditional, spherical, ones. We measure interconnect resistance of individual particles in a nano-indentation test setup, as well as the interconnect resistance of ACF bonding using the two different particles, in daisy-chain measurements. Interconnect resistance of individual spiky particles is more than an order of magnitude higher than the one for spherical particles. However, when mixed in an adhesive and used for ACF bonding, the interconnect resistance of ACF with spiky particles is somewhat lower than that of the ACF with spherical particles. The interconnect resistance of ACF with spherical particles is two orders of magnitude higher than that of the individual particles, whereas the interconnect resistance of ACF with spiky particles is comparable to the individual-particle resistance. We conclude that trapped adhesive is a major concern for fine-pitch ACF bonding, and that the use of spiky conductive particles has the potential to overcome these challenges.

Solder-less Fine Pitch Copper-to-Copper Bonding

The industry has been looking to increase pitch scaling through various methods. One of these methods is an alternative to solid-state solder bonding. However, very few processes can compete with solder bonding’s fast speed, low cost, and flexibility. The approach with the biggest potential for connecting fine pitch interconnects in high-density semiconductor packaging is solder-less copper-to-copper direct bonding. There are many benefits to using copper-to-copper direct bonding, including the ability to achieve ultra-fine-pitch (bump pitch 10 μm), higher reliability (both thermo-mechanically and better electromigration behavior), low resistance, as well as the lack of concern for solder hierarchy for multiple reflow. This copper-to-copper direct bonding technology enables a variety of 2.5D/3D advanced packaging architectures and is also suitable for multi-die stacking. In this study, we report the investigation of a direct copper-to-copper bonding methodology and reliability of the bonded components. Our process differs from common hybrid bonding copper-to-copper techniques, in that it is designed for low volume highly complex products. This technology allows a die-to-die and die-to-wafer process using thermocompression bonding under a deoxidizing vapor flow for direct copper-to-copper bonding. The process does not require high temperature oven annealing and can be done in a normal atmospheric environment. The investigated bonding process is ideal for high power, high thermal, high density 3D stacking and high-speed digital communication applications. We demonstrated the bonding procedure using a test vehicle with 40 μm diameter pillars and 80-μm bump pitch. We investigated the effects of bonding force and evaluated joint reliability. Interconnect/bond strength was determined through destructive shear testing and cross-sectional analysis. A scanning electron microscope was used to inspect and examine the bonded joint quality. Finally, completed assemblies were thermal cycled to evaluate degradation of joint strength under induced stress, and resistance measurements were performed to evaluate the electrical performance of the bonded copper joint.

The Impact of AI on Contact Resistance and Its Suitability in Fine Pitch Interconnects

Integration issues for a three-dimensional (3D) interconnect in a Face-to-Face (F2F) configuration are discussed. In particular, the effect of AI and organic dielectrics under the bump and their effect in chip-package-interaction (CPI) stresses as well as AI contact resistance issues that arise as the interconnection pitch is decreased. This paper will present a finite-element model created to study the stresses in advanced 3D microelectronic package. To assess the reliability of the 3D packages a submodeling approach is used to capture the CPI stresses. The modeling study presented indicates that it is beneficial to continue using AI pads as it has significatly lower stresses compared to copper pads/vias. In the second portion of the paper, the effect of PBO developer on AI corrosion is presented. Reactive ion etching (RIE) chemistries and wet chemistries were optimized using contact resistance as the success metric. Process robustness was achieved by decoupling the hard dielectric opening from the PBO via opening. Time of Flight Secondary Ion Mass Spectrometry (ToF-SIMS), Scanning Electron Microscopy (SEM), X-ray Photoelectron Spectroscopy (XPS) analysis were used to add clarity to the bump contact resistance values.

Thermo-compression Bonding Assembly Technology

With the slowing of Moore’s law heterogeneous integration and assembly became important drivers of the performance of semiconductor packaging. This “More than Moore” approach enables higher functional density and higher bandwidth packages. At the same time, heterogeneous integration drives an aggressive interconnect pitch roadmap, pushing the limits of Advanced Packaging technologies. Flip chip with mass reflow has been the main assembly technology for fine pitch interconnect. However, the need for even finer pitch and higher packaging density was not compatible with the limitations imposed by the mass reflow process, therefore requiring new interconnect technologies. Local reflow flip chip via thermocompression bonding (TCB) overcomes limitations due to CTE-mismatch and warpage. Meanwhile, TCB based on solder micro-bumps became a well-established and cost effective fine-pitch interconnect process and Cu to Cu Hybrid Bonding is emerging as a technology for the future. Normal TCB typically requires the application of flux and post-bond flux cleaning as any flux residue can result in post mold package reliability issues, even for ‘no-clean’ flux materials. Post-bond flux cleaning, however, becomes more and more difficult for increasing die size and with bump pitch and stand-off height shrinking even further. K&amp;S has developed and demonstrated a flux-less TCB process for large and high-density interconnect die that utilizes in-situ Formic Acid (FA) vapor application for copper and solder oxide reduction. This process eliminates the need for flux and, therefore, there is no need for the tedious and time-consuming cleaning of the post bond flux residue. The FA process delivers nearly the same productivity as a conventional flux based TCB process. The FA delivery system can be integrated on our high-accuracy C2S and C2W TCB tools, leveraging the existing HVM TCB infrastructure and extending its application space from ~35µm towards ultra-fine pitch applications around 10µm. Hybrid bonding created a lot of attention over the last years as this bump-less technology allows for long-term pitch scalability, possibly even down to 1µm. Hybrid bonding, however, requires a more complex process flow which relies on pristine die and target wafer surfaces as well as front-end level cleanliness conditions. Accordingly, the advantages and cost of Flux-less TCB as compared to Hybrid bonding should be explored in more detail. TCB can be viewed as an extension of flip chip. Using the existing assembly and metrology infrastructure as well as the existing die and substrate design layouts will be attractive to subcons. As a result, the overall cost and time to market should be much lower. An activity-based cost model has been developed along with SavanSys comparing flux-less TCB and Hybrid bonding. We present results on the process cost as well as the overall package cost as a function of die size and yield. In summary, flux-less thermo-compression bonding should be considered for ultra-fine pitch applications. We have demonstrated pitch capability below 30µm and believe that a pitch of 10µm may be possible. Other applications that formic acid vapor TCB enables are large module bonding (50 X 50 mm, 70 X 70 mm) and Cu to Cu interconnects.

Copper-Based Nanomaterials for Fine-Pitch Interconnects in Microelectronics.

ConspectusNanostructured copper-based materials have emerged as a new generation of robust architectures for realizing high-performing and reliable interconnection in modern electronic packaging. As opposed to traditional interconnects, nanostructured materials offer better compliance during the packaging assembly process. Due to the high surface area-to-volume ratio of nanomaterials, they also enable joint formation by sintering through thermal compression at much lower temperatures compared to bulk counterparts. Nanoporous Cu (np-Cu) films have been employed in electronic packaging as materials that facilitate a chip-to-substrate interconnection, realized by a Cu-on-Cu bonding after sintering.In this Account, we discuss the use of self-supported np-Cu films for low-temperature joint formation. The novelty of this work comes from the incorporation of tin (Sn) into the np-Cu structure, thus ensuring lower sintering temperatures with a goal of producing Cu-Sn intermetallic alloy-based joints between two Cu substrates. The incorporation of Sn is done using an all-electrochemical bottom-up approach that involves the conformal coating of fine-structured np-Cu (initially formed by dealloying of Cu-Zn alloys) with a thin layer of Sn.This Account provides insight on existing technologies for using nanostructured films as materials for interconnects as well as the optimization studies for the Sn-coating processes as a new alternative approach. The applicability of the synthesized Cu-Sn nanomaterials for low-temperature joint formation is also discussed. To realize this new approach, the Sn-coating process is administered by a galvanic pulse plating technique, which is optimized to preserve the porosity in the structure with a Cu/Sn atomic ratio that allows for the formation of the Cu6Sn5 intermetallic compound (IMC). Nanomaterials obtained using this approach are subjected to joint formation by sintering at temperatures between 300 and 200 °C under 20 MPa pressure in forming gas atmosphere. Cross-section characterization of the formed joints postsintering reveals densified bonds with minimal porosity that consist predominantly of the Cu3Sn IMC. Furthermore, these joints are less prone to structural inconsistencies compared to existing joints formed using purely np-Cu. The results presented in this Account provide a glimpse into a facile and cost-effective approach for synthesizing nanostructured Cu-Sn films and illustrate their applicability as new interconnect materials.

Analysis of Transmission Performance for Fine Pitch Interconnect

Wire bonding is the preferred interconnection in the IC packaging. Understanding the electrical performance of bonding wire as transmission line is utmost important. To date, there is very limited studies on the transmission performance of fine pitch bare bonding wire especially the insulated wires. This paper investigated the transmission performance of single bare bonding wires and insulated bonding wires with different wire material, wire diameter, bonding height, insulation thickness at high frequency. The simulation analysis shows that when the frequency increases above 15Ghz, the effect of the geometric parameters has no significant different to the transmission performance. The thickness of the insulation between 0.1μm to 0.3μm reacted similar performance for return loss and insertion loss across all frequency

Study for Bonding Technology by Electroplated Nano porous Cu Structure

The various kinds of the packaging technologies such as 2.nD, 2.5D, 3D are highly studied with the rapid development of miniaturization and high density of semiconductor packaging. This trend increases the importance of fine pitch interconnect. To achieve fine pitch interconnect, Cu-Cu direct bonding or hybrid bonding which has no solder in bonding layer is the promising technologies. There are some difficulties in the solderless bonding such as the control of bump uniformity, high accuracy CMP (Chemical Mechanical Polishing) process and so on. In particular, the exact surface shape control is the essential issue. To solve these problems, we are proposing Nano porous (NP) Cu materials for interconnect material. One of the technical challenges is the process for formation of NP Cu µ-bump structure. We are focusing on electroplating process for µ-bump formation. Firstly, we developed the plating chemicals for formation of NP Cu structure. We consider two types of plating chemicals for NP Cu formation, de-alloying and direct porous plating process. For de-alloying process, Cu-Zn alloy bumps were plated, and NP Cu bumps were obtained by de-alloying the Cu-Zn alloy. For direct porous plating process, NP Cu bumps were plated by using unique additives which can form NP structure directly. By using electroplated NP Cu, we studied its various properties, and carried out bonding tests. As the results, NP Cu structure shows unique properties such as electrical conductivity and the hardness, and we consider that these unique properties should widen the bonding process margin. We would like to present our recent research of NP Cu which is promising materials for advanced bonding technology.

Prediction of Curing Time/Shear Strength of Non-Conductive Adhesives Using a Neural Network Model

Electronic packaging has been developed with high resolution and fine interconnection pitches. Non-conductive adhesives (NCAs) have been growing with the increase of I/O pad count and density, along with fine pad bond pitch interconnections. Prediction and optimization of NCA characteristics are inherently complicated due to various and extensive materials composing NCAs. In this study, a framework predicting the curing time and shear strength of an NCA is established by a neural network model. NCA formulations with 4 resins, 3 hardeners, 8 catalysts, and a coupling agent were selected from in-house experiments, and an artificial neural network (ANN) with one dense layer with 3 nodes was trained using 65 data points. Model accuracy was improved by 28.9–35.2% compared with the reference, and the trained model was also verified through third-party reference data. Prediction of NCA properties and optimization of NCA formulations for mass production were demonstrated by using the trained ANN model. This paper provides a framework for ANN-based NCA design and confirmed the feasibility of ANN modeling, even with a small dataset.

Backplate-reinforced structures for enhancing solder joint reliability of server CPU assembly under thermal cycling

ABSTRACT To meet the requirement of the high I/O and fine-pitch interconnects, the conventional insertion-mount socket for central processing unit (CPU) has been changed to surface-mount one with ball grid array. The solder ball joint reliability of the socket used in the CPU assembly becomes very important. In this study, the socket's solder joint reliability of the backplate-reinforced CPU assembly and its related mechanics under mechanical and thermal loadings are investigated experimentally using strain gauge and shadow moiré, and numerically by a finite element method (FEM). The validated FEM results have suggested that maximum stress of solder balls increases almost linearly with decreasing the backplate thickness under mechanical loading during the CPU assembly, but is insensitive to the backplate thickness under thermal loading during the thermal cycling. It is also found that the residual (bending) strain on the PCB proportional to the maximum von Mises stresses of solder joints (or balls) can be used as a key parameter to correlate with the solder joint failures or cracks during the thermal cycling. Overall, experimental and FEM results in this study reveal that solder joint reliability in the CPU assembly during thermal cycling can be improved by adopting the thicker reinforced backplate.

(Invited) All Electrochemical Synthesis of Nanoporous Cu Films for the Purposes of Fine Pitch and Low Temperature Interconnection in 3D Packaging

Nanoporous Cu (np-Cu) films can be employed in the electronic packaging as materials facilitating chip-to-substrate interconnections, which is realized by Cu-on-Cu bonding. Unlike their bulk counterparts, np metals feature unique interconnected pore-ligament structure with a length scale in the range of single-to-tens of nanometers. This results in a high surface area-to-volume ratio accompanied with a substantially lower melting temperature. Research has been done in the field to experiment with Cu-on-Cu interconnects realized by np-Cu precursor films (1). While the initial results are undoubtedly promising, difficulties haver been met with sufficiently lowering the sintering / soldering temperature below 380-400oC. A way to address these shortcomings is to develop of approaches to sintering at much lower temperatures by introducing Sn into the np-Cu structures either directly or by coating then followed by processing to produce at lower sintering temperature Cu-Sn bonds with low resistivity and a greater current carrying capability than bare np-Cu. The foundation of this study relies on the development of fine structured np-Cu films with an open and uniform interconnected network of ultra-fine ligaments and pores of size preferably in the single digit nanometer range.The present report is focused on the development of a two-step all-electrochemical approach for the synthesis of the targeted np-Cu structures including (i) a controlled electrodeposition of Cu-based precursor alloy with a less-noble counterpart that is then (ii) selectively removed (de-alloyed) by anodization at appropriate potential to leave behind the desired “spongy” np-Cu structure (2). Therefore, the first part of this report introduces and discusses the development of protocols for flat and uniform deposition of Cu-Zn and Cu-Mn alloys that could both serve as precursors of the synthetically targeted np-Cu films. The choice of said alloy systems is motivated by the ability of Zn and Mn to form single-phase alloys or intermetallic compounds with Cu thus ensuring the ultra-fine length scale of the eventually synthesized np Cu structure. The alloy deposition routines included use of a pyrophosphate (P2O7 4-) plating bath for Cu-Zn alloys which were shown to have high stability and optimizable for the plating of smooth and fine-grained brass deposits (3). Also, ammonium sulfate with excess of ammonia as complexing agent, was employed in the optimization activity aimed at the deposition of continuous and relatively smooth Cu-Mn deposits (4). The report discusses the optimization of plating parameters and conditions along with the subsequent structural and compositional characterization of the accordingly deposited precursor alloys with 60 at % and higher representation of the less noble constituent.Next, the electrochemical de-alloying of as-deposited CuxZn(1-x) and CuxMn(1-x) precursor alloys on a gold substrate is introduced and discussed. Alike with the first part of the report, the emphasis is on the optimization routines that looked at the effect of de-alloying scan rate, de-alloying at different constant potentials, de-alloying bath, and precursor alloy composition on the morphology and composition of the resulting np-Cu. A valuable part of the report is the demonstration of how the implementation of best combinations of optimized parameters and conditions leads to the synthesis of interconnected pore-ligament thin film networks of np-Cu structures with average ligament sizes in the range of 15-30 nm. In conclusion, the discussion takes direction towards ideas and perspectives for improvement of the uniformity and further refinement of the pore ligament length scale. Finally, consideration is also given to the intended approaches to introduce Sn on or into the accordingly synthesized np-Cu films and eventually convert them to np-Cu-Sn alloy ready for sintering/soldering at low temperatures.

Flip Chip - Chip Scale Package Bonding Technology with Type 7 Solder Paste Printing

In this study, thermo-compression(TC) and vacuum reflow(VR) bonding processes of fine pitch interconnection were optimized using Type 7 Sn-3.0Ag-0.5Cu solder paste. A chip with Cu pillar Sn-2.5Ag bumps and BT substrate with ENEPIG surface finish were used, and the thickness and the aperture ratio of the metal mask were 30 ㎛/50 ㎛ and 70%/100%, respectively. As a result of optimizing the printing process, a metal mask with a thickness of 30 ㎛ and an aperture ratio of 100% was selected. As a result of the TC and VR bonding processes optimization, Cu6Sn5 and (Cu,Ni)6Sn5 IMC layers were formed on the top and bottom of the solder joint, respectively. In the conventional TC process sample, the thickness of the solder was measured to be 4.1 ㎛, and the IMC thickness ratio was calculated to be 40%. Also, in the TC and VR process samples with solder paste, the thickness of the solder was measured to be 6.5 ㎛ and 10.3 ㎛, respectively, and the ratio of the IMC thickness was calculated to be about 32% and 43%. It was expected that it would be beneficial to reliability by reducing the occurrence and propagation of cracks in the solder joint due to the effect of lowering the IMC thickness ratio as the volume of the solder becomes larger than that of the conventional TC process.

Silicon-Interconnect Fabric for Fine-Pitch (≤10 μm) Heterogeneous Integration

The apparent saturation of aggressive Moore's law scaling of semiconductor technologies is pushing the boundaries of traditional packaging and integration schemes to accommodate the ever-growing data bandwidth and heterogeneity demands. In this article, we demonstrate the silicon-interconnect fabric (Si-IF) technology as a superior alternative to conventional printed circuit boards (PCBs) to enhance system scaling. The Si-IF is a silicon-based, package-less, fine-pitch, highly scalable, heterogeneous integration platform to assemble and integrate massive wafer-scale systems. In this technology, dielets are closely assembled on the Si-IF at small interdielet spacings ( ≤ 50 μm) using fine-pitch ( ≤ 10 μm) die-to-substrate interconnects allowing for tight integration on a system-level package. To achieve these fine-pitch interconnects, a novel assembly technique using solder-less direct metal-metal [copper-copper (Cu-Cu)] thermal compression bonding was developed. Using this process, sub-10- μm-pitch interconnects with a low specific contact resistance of ≤ 0.7 Ω·μm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> 2</sup> and high shear force of 90 N for 4-mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> dies were successfully demonstrated. Moreover, these fine-pitch interconnects combined with the small interdie spacing provide a large number of parallel short links ( ≤ 500 μm) with low loss (≤2 dB) for interdielet communication that is comparable to on-chip connections. Consequently, simple buffers can transfer data between dies using a Simple Universal Parallel intERface for chips (SuperCHIPS) protocol at low link latency (<; 20 ps), low energy per bit (≤0.03 pJ/b), and high data rates (up to 10 Gb/s/link), corresponding to an aggregate data bandwidth of up to 8 Tb/s/mm. The benefits of the SuperCHIPS interface are experimentally demonstrated using functional dielet assembly on the Si-IF to show 4- 23× higher data bandwidth, 3- 65× lower latency, and 5- 40× lower energy per bit compared to existing integration schemes.

A review of intermetallic compound growth and void formation in electrodeposited Cu–Sn Layers for microsystems packaging

In recent years, Cu–Sn solid–liquid interdiffusion (SLID) bonding has been used in semiconductor packaging, die-attach, fine-pitch interconnection, and through-silicon vias (TSV)-based 3D stacking applications. Due to its specific advantages such as lower cost, less stringent surface uniformity requirements, higher thermal bond stability, and relatively lower processing temperatures, electrodeposited Cu–Sn-based bonding is explored to achieve wafer-level hermetic encapsulation of miniaturized sensors; however, the overall reliability of Cu–Sn bonds remains a challenge. The voids formed in the electrodeposited Cu–Sn layers and the brittle nature of the formed intermetallic compounds (IMC) affects the long term reliability of the Cu–Sn SLID bonds. A significant concern is the sporadic interfacial void formation within the Cu–Sn layers during the bonding process and high-temperature applications. This review article summarizes the different mechanisms of the IMC formation and their growth and explores the reasons behind the interfacial voids formed in the electrodeposited Cu–Sn layers when these are annealed at different temperatures ranging from 150 to 300 °C. A detailed description of the IMC and void formation and their subsequent growth in the thick electrodeposited Cu–Sn layers is presented, along with the various design parameters affecting the IMC growth during the bonding process. Various remedies to minimize these interfacial voids are also suggested. Higher bonding pressure, lower processing temperature, and reduced surface roughness are the key factors affecting the void size and voids density. The chemical impurity in the copper electrolyte and the resultant surface roughness affect the interfacial void formation in the electrodeposited Cu–Sn layers. This review will help minimize the interfacial voids and, thus, obtain higher bond reliability.

Bonding methods for chip integration with Parylene devices

Flexible electronics require more compact interconnects for next-generation devices. Polymer devices can be bonded to integrated circuit chips, but combining flexible and rigid substrates poses unique technical challenges. Existing technologies either cannot achieve the density required for modern chips or employ specialized equipment and complex processes to do so. Here, we adapt several approaches to achieve fine-pitch bonding between rigid and flexible substrates including epoxy, ultrasonic wire, and anisotropic conductive film bonding and also introduce a novel technique called polymer ultrasonic on bump (PUB) bonding. Using Parylene C devices and various rigid substrates as our model testbed systems, we investigate these four methods across a range of bond pad size and pitch by measuring yield and resistance and by subjecting devices to thermomechanical reliability tests. We demonstrate that all methods are capable of bonding fine pitch interconnects (100 µm) at low temperature (<100 °C). Additionally, we focus on PUB bonding and join a packaged chip and a bare die to Parylene devices.

Experimental and computational investigation of low temperature Cu[sbnd]Sn solid-state-diffusion bonding for 3D integration

Three critical experiments, including Sn interlayer thickness optimization, interfacial IMC growth evolution, and bump size effect, have been conducted for low temperature CuSn solid-state-diffusion (SSD) bonding. The minimum thickness of Sn interlayer was firstly optimized to shorten the bonding time through surface and interface analysis. During bonding and annealing processes for sandwich-structured Cu/Sn/Cu interconnection, Sn interlayer exhausting and intermetallic compounds (IMCs) transforming were then investigated detailly. The growth mechanism of Cu6Sn5 and Cu3Sn in low temperature CuSn bonding was still controlled by lattice diffusion. However, Cu6Sn5 growth inhibited Cu3Sn growth when Sn existed. Finally, a stable three-layer structure of Cu/Cu3Sn/Cu could form at bonding interface. Also, bump size effect due to IMC lateral growth have been demonstrated for fine-pitch interconnection. It is concluded these investigations would facilitate the application of low temperature CuSn SSD bonding for high-density 3D integration.

Development of electro-copper plating with nanodiamonds for electronic interconnects in advanced packaging

In order to advance a technology suitable for fabrication of fine pitch interconnects using copper electro plating, we developed the composite of copper (Cu) and nanodiamonds (NDs). Electro-Cu plating coatings obtained by adding NDs to the electro-Cu plating bath were demonstrated to maintain a smaller crystallite size compared to the plating coatings that NDs were not added. Moreover, in case of the electro-Cu plating coatings obtained by adding NDs, smoothness of the plating coating surface and hardness of the plating coating with time course have been improved, and the electro conductivity has been improved by up to 16%. The composite material of electro-Cu plating and NDs which we developed showed the potential that it could be expected for application to fine pitch interconnects in an advanced packaging technology.

(Invited) Heterogeneous Integration Packaging Challenges for Artificial Intelligence

As semiconductor and system scaling has saturated, heterogeneous integration of disparate components in a singular electronic package has become increasingly important. A variety of new packaging techniques are being developed for heterogeneous integration. These techniques include multiple-chip packages incorporating high-density laminated substrates, inter-chip bridges, silicon interposers, and three-dimensional chip stacking. This talk will compare and contrast these varied techniques and identify the associated challenges. These challenges include fine-pitch interconnects, new materials, complex assembly, thermal management, and test and reworkability, among others. Implications to tool development, test protocols, and simulation techniques will also be discussed.

Epoxy/silane pre-synthesis improving thermal properties and adhesion strength of silica-filled non-conductive adhesive for fine-pitch thermocompression bonding

We modified an epoxy with silane to improve the bondability and thermal properties of a non-conductive adhesive (NCA) for fine-pitch thermocompression (TC) bonding. The main objectives of this modification were to improve the silica dispersion in the NCA and its wettability to achieve a low coefficient of thermal expansion (CTE) without any filler entrapment and a robust bonding joint. A commercial diglycidyl ether of a bisphenol A and F mixture resin and 3-glycidyloxypropyl trimethoxysilane were synthesized at 250 °C for 2 h. An anhydride (hardener) and an imidazole (catalyst) were used as the NCA curing system. The CTE of the silane-modified NCA was 29.1 ppm/ °C, which was lower than that of a neat epoxy NCA (42.6 ppm/ °C), and was the result of uniform silica dispersion in the NCA matrix. The shear strength of the TC bonded joint was also improved from 31.8 MPa to 46.5 MPa (1.45 times higher) after the epoxy silane modification due to the improved wettability of the epoxy resin. Void formation in the cured NCA layer and silica filler entrapment at the Cu/Sn interface were also suppressed. Thus, this epoxy silane modification produced a robust and thermally reliable NCA material for fine-pitch interconnections.