Fine-pitch Ball Grid Array Package Research Articles

ILP-based Substrate Routing with Mismatched Via Dimension Consideration for Wire-bonding FBGA Package Design

With the rapidly growing demand for system-level integration, package substrates have become one of the most important carriers in semiconductor industry. Fine pitch ball grid array (FBGA) packaging is a widely used technology thanks to its relative cost-effectiveness compared to other advanced packaging technologies. In addition, it is also widely used in space-constrained applications, such as mobile and handheld devices. These packaging substrate interconnections are usually customized by layout engineers taking many complex and stringent design rules into consideration. However, fully net-by-net manual design for FBGA is time-consuming and error-prone. In this article, we propose an integer linear programming (ILP)-based router for wire-bonding FBGA packaging design. Our ILP formulation not only can handle design-dependent constraints but also take the problem of mismatched via dimension into account, which is caused by the mechanical processes and greatly increases design complexity. In addition to the ILP formulation for substrate routing, three optimization stages and several ILP constraint reduction techniques are also developed to boost the run time of ILP solver. Experimental results indicate that the proposed framework can achieve high routing completion rates, which could effectively reduce the cycle time of substrate layout design. In addition, in combination with the proposed optimization strategies, 278× speedup can be achieved compared to the ILP constraint optimized router.

Parametric study of thermally induced warpage of FpBGA package using finite element methods

Warpage is considered to be the major concern in ensuring the reliability and manufacturability of electronic package because a flat package is crucial for a successful formation of board level assembly process. Warpage is the out of plane displacement which is a resultant of difference in co-efficient of thermal expansion (CTE) between the adjoining packaging materials. Enormous warpage may lead to occurrence of faulty joints such as open connections, mis-shaped joints, and loss of package board-level reliability under manufacturing, thermal loading process, shock and vibration. In this paper, a Fine pitch ball grid array Package (FpBGA) which is a prominent type of electronic package offering solution for downsizing of electronic components such as mobiles and camcorders has been choose for study. Warpage of FpBGA was simulated from post cure temperature to reflow temperature using Finite Element Methods. A static thermal analysis was carried out using ABAQUS software and a parametric study was done to investigate the effect of material properties and geometric properties in minimizing the warpage. Materials properties such as CTE, Elastic modulus of substrate and die, geometric properties like thickness of die and substrate were chosen for study.

DDR4 BER Degradation Due to Crack in FBGA Package Solder Ball

This paper measures bit error rate degradation in DDR4 due to crack in fine pitch ball grid array (FBGA) package solder ball. Thermal coefficient mismatch between the package and printed circuit board material causes cracks to occur in solder balls. These cracks change the electrical model of the solder ball and introduce parallel capacitance in the electrical model. The capacitance causes higher frequency attenuation and closes the data eye. As the data rate of the DDR4 increases there are more data eye closures. The data eye closure causes bit error rate (BER) degradation as the timing margin and voltage margin decreases. This degradation reduces the reliability of the system and causes more intermittent errors. DDR4 data line is loaded with a parallel capacitive element to mimic a crack in solder ball. The measured data eye shows a decrease in eye width. Bathtub plots are created for comparison of cracked solder ball and intact solder ball. The bathtub plots show the BER degradation due to crack in solder ball.

Head-on-Pillow Defect Detection: X-Ray Inspection Limitations

Abstract Both the number and the variants of ball grid array packages (BGAs) are tending to increase on network printed board assemblies with sizes ranging from a few millimeter die size wafer level packages with low ball count to large multidie system-in-package (SiP) BGAs with 60–70 mm side lengths and thousands of I/Os. One big challenge, especially for large BGAs, SiPs, and for thin fine-pitch BGA assemblies, is the dynamic warpage during the reflow soldering process. This warpage could lead to solder balls losing contact with the solder paste and its flux during parts of the soldering process, and this may result in solder joints with irregular shapes, indicating poor or no coalescence between the added solder and the BGA balls. This defect is called head-on-pillow (HoP) and is a failure type that is difficult to determine. In this study, x-ray inspection was used as a first step to find deliberately induced HoP defects, followed by prying off of the BGAs to verify real HoP defects and the fault detection correlation between the two methods. The result clearly shows that many of the solder joints classified as potential HoP defects in the x-ray analysis have no evidence at all of HoP after pry-off. This illustrates the difficulty of determining where to draw the line between pass and fail for HoP defects when using x-ray inspection.

A 4266 Mb/s/pin LPDDR4 Interface With An Asynchronous Feedback CTLE and An Adaptive 3-Step Eye Detection Algorithm for Memory Controller

A 4266Mb/s/pin LPDDR4 interface with an asynchronous feedback continuous-time linear equalizer (AF-CTLE) and an adaptive 3-step eye detection algorithm for memory controller is presented. The AF-CTLE removes the glitch of DQS without training by applying an offset larger than the noise, and improves read margin by operating as a decision feedback equalizer in DQ path. The adaptive 3-step eye detection algorithm reduces power consumption and black-out time in initialization sequence and retraining in comparison to the 2-D full scanning. A prototype chip was implemented in a 65-nm CMOS process with fine-pitch ball grid array package and tested with commodity LPDDR4 memory. The write margin was 0.36 UI and 148 mV; and the read margin was enhanced from 0.30 UI and 76 mV without AF-CTLE to 0.47 UI and 80 mV to with AF-CTLE. The power efficiency during burst write and read were 5.68 pJ/bit and 1.83 pJ/bit, respectively.

Reliability Comparison of Aged SAC Fine-Pitch Ball Grid Array Packages Versus Surface Finishes

Pb-free solder joints exposed to elevated isothermal temperatures for prolonged periods of time undergo microstructural and mechanical evolution, which degrades the joint electrical performance. We report the effect of isothermal aging on the reliability of Sn–Ag–Cu (SAC) assemblies on three different surface finishes [immersion Ag (ImAg), electroless Ni/immersion Au (ENIG), and electroless Ni/electroless Pd/immersion Au (ENEPIG)]. The characteristic life for SAC alloys in 10- and 15-mm ball grid array packages on ImAg degraded over 40% after an 85 °C/12 months aging and over 50% during a 125 °C/12 months aging. ENIG and ENEPIG outperformed ImAg for all aging treatments. For passive components (2512 resistors) on ImAg, the reliability performance degraded 16.7%/28.1% after a 1-year aging at 85 °C/125 °C. Failure analysis showed dramatic intermetallic binary Cu–Sn and ternary Ni–Cu–Sn film growth at the bottom of the solder joint interfaces for ImAg and ENIG/ENEPIG. For 125 °C-aged samples, the cracks appeared at the corners of both package and board sides of the solder ball and propagated along (near) the intermetallic compound location. For the case of aged fine-pitch packages, the failures tended to start at the component side solder ball corner and then propagate along an angled path downward into the bulk solder.

Effect of Isothermal Aging on the Long-Term Reliability of Fine-Pitch Sn–Ag–Cu and Sn–Ag Solder Interconnects With and Without Board-Side Ni Surface Finish

The combined effects on long-term reliability of isothermal aging and chemically balanced or unbalanced surface finish have been investigated for fine-pitch ball grid array packages with Sn–3.0Ag–0.5Cu (SAC305) (wt.%) and Sn–3.5Ag (SnAg) (wt.%) solder ball interconnects. Two different printed circuit board surface finishes were selected to compare the effects of chemically balanced and unbalanced structure interconnects with and without board-side Ni surface finish. NiAu/solder/Cu and NiAu/solder/NiAu interconnects were isothermally aged and thermally cycled to evaluate long-term thermal fatigue reliability. Weibull plots of the combined effects of each aging condition and each surface finish revealed lifetime for NiAu/SAC305/Cu was reduced by approximately 40% by aging at 150°C; less degradation was observed for NiAu/SAC305/NiAu. Further reduction of characteristic life-cycle number was observed for NiAu/SnAg/NiAu joints. Microstructure was studied, focusing on its evolution near the board and package-side interfaces. Different mechanisms of aging were apparent under the different joint configurations. Their effects on the fatigue life of solder joints are discussed.

Impact of Electrical Current on the Long-Term Reliability of Fine-Pitch Ball Grid Array Packages with Sn-Ag-Cu Solder Interconnects

The interaction between electrical current and the long-term reliability of fine-pitch ball grid array packages with Sn-3.0Ag-0.5Cu (wt.%) solder ball interconnects is investigated. In this study, 0.4-mm fine-pitch packages with 300-μm-diameter Sn-Ag-Cu solder balls are used. Electrical current was applied under various conditions to two different package substrate surface finishes to compare the effects of chemically unmixed and mixed joint structures: a Cu/SAC305/Cu structure and a NiAu/SAC305/Cu structure, respectively. To study the thermal impact on the thermal fatigue performance and long-term reliability, the samples were thermally cycled from 0°C to 100°C with and without current stressing. Based on Weibull plots, the characteristic lifetime was degraded for the mixed joint structure, but little degradation was observed for the unmixed joint structure. The microstructure evolution was observed during constant current stressing and current stressing during thermal cycling. Accelerated intermetallic precipitation depletion at the package-side interface was observed in NiAu/SAC305/Cu structures due to current stressing, which was identified as the potential reason for the degradation in the thermal cycling performance.

Impact of Isothermal Aging on the Long-Term Reliability of Fine-Pitch Ball Grid Array Packages With Different Sn-Ag-Cu Solder Joints

A direct and deleterious effect on packaging reliability has been observed during elevated temperature isothermal aging for fine-pitch ball grid array (BGA) packages with Sn-1.0Ag-0.5Cu (SAC105), Sn-3.0Ag-0.5Cu (SAC305), and Sn-37Pb solder ball interconnects. Package sizes ranging from 19 mm with 0.8-mm-pitch BGAs to 5 mm with 0.4-mm-pitch μ BGAs with three different board finishes (ImSn, ImAg, and SnPb) were evaluated. The aging temperatures were 25°C, 55°C, 85°C, and 125°C, applied for a period of 6 mo. Subsequently, the specimens were thermally cycled from -40°C to 125°C with 15-min dwell times at the high temperature. Weibull analysis of failures versus cycle number show a ~ 50% reduction in package lifetimes when aged at 125 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">°</sup> C compared to the same at room temperature, with less dramatic but measurable reductions in lifetime at 85°C and even 55°C. In contrast, the reliability performance of Sn-37Pb is much more stable over time and temperature. The degradation was observed for both SAC alloys on all tested package sizes and board finishes. For the 19-mm SAC105 case, for example, there was a 53% (32%) reduction of characteristic lifetime at 125°C (85°C) compared to room temperature aging. The trends were in the expected directions; namely, the reliability was reduced when using higher aging temperatures, smaller solder balls, and SAC105. The dominant failure mode can be associated with the growth of Cu <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">6</sub> Sn <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">5</sub> intermetallic compounds during the aging, particularly on the pad side.

Simulation of Effect of Solder Balls Layout on Warpage and Interfacial Stresses of FBGA

The finite element method is used to construct the sequential processing model of the package. The model is used to simulate the warpage and interfacial stresses of FBGA (Fine-pitch Ball Grid Array) package due to the coefficient of thermal expansion mismatch between layered materials of package during assembly processes. The processing model uses the function of element birth and death to simulate the processing step of package model, considering the sequentially accumulated warpage and stresses during the processing steps. The induced package stresses can cause the delamination between die/die attach interface. In order to verify the simulation results, the simulated package warpage of a standard package is compared with the measurement of package warpage of the package. In this study, the effect of solder balls layout on the warpage and interfacial stresses at die/die attach interface is discussed by simulation results.

Optimal design of thin-profile fine-pitch ball grid array package under drop impact test

This article describes the board-level drop reliability of thin-profile fine-pitch ball grid array (TFBGA) subjected to Joint Electron Device Engineering Council (JEDEC) drop test conditions featuring an impact pulse profile with a peak acceleration of 1500 G and a pulse duration of 0.5 ms. The solder ball is assumed to be an elastoplastic model and the other components linear elastic ones. Both the global/local finite element and the finite grid region methods are introduced to improve the accuracy and the convergence during the meshing process. Meanwhile, the contact impact process during the drop test is translated into the effective support excitation load on the printed circuit board (PCB) through the support excitation scheme to simplify the analysis. By means of optimal parameters of the Taguchi robust design, the average stress of the solder ball at the PCB side surface becomes 80.9 MPa, which shows a 57 per cent reduction compared to the original stress of 189.7 MPa. As a result, the impact reliability of the TFBGA package is significantly improved. Finally, the JEDEC drop test is conducted to verify the optimal results obtained by the Taguchi method.

Impact of Isothermal Aging on Long-Term Reliability of Fine-Pitch Ball Grid Array Packages with Sn-Ag-Cu Solder Interconnects: Die Size Effects

Impact of Isothermal Aging on Long-Term Reliability of Fine-Pitch Ball Grid Array Packages with Sn-Ag-Cu Solder Interconnects: Die Size Effects

Impact of Isothermal Aging on Long-Term Reliability of Fine-Pitch Ball Grid Array Packages with Sn-Ag-Cu Solder Interconnects: Surface Finish Effects

The interaction between isothermal aging and the long-term reliability of fine-pitch ball grid array (BGA) packages with Sn-3.0Ag-0.5Cu (wt.%) solder ball interconnects was investigated. In this study, 0.4-mm fine-pitch packages with 300-μm-diameter Sn-Ag-Cu solder balls were used. Two different package substrate surface finishes were selected to compare their effects on the final solder composition, especially the effect of Ni, during thermal cycling. To study the impact on thermal performance and long-term reliability, samples were isothermally aged and thermally cycled from 0°C to 100°C with 10 min dwell time. Based on Weibull plots for each aging condition, package lifetime was reduced by approximately 44% by aging at 150°C. Aging at 100°C showed a smaller impact but similar trend. The microstructure evolution was observed during thermal aging and thermal cycling with different phase microstructure transformations between electrolytic Ni/Au and organic solderability preservative (OSP) surface finishes, focusing on the microstructure evolution near the package-side interface. Different mechanisms after aging at various conditions were observed, and their impacts on the fatigue lifetime of solder joints are discussed.

Impact of isothermal aging on fine pitch BGA packages with Sn-Ag-Cu solder interconnects

The interaction between isothermal aging and long-term reliability of fine pitch ball grid array (BGA) packages with Sn-3.0Ag-0.5Cu (wt%) solder ball interconnects are investigated. In this study, 0.4mm fine pitch packages with 0.3mm diameter Sn-Ag-Cu solder balls are used. Two different die sizes and two different package substrate surface finishes are selected to compare the internal strain impact and alloy effect, especially the Ni effect during thermal cycling. To see the thermal impact on the thermal performance and long-term reliability, the samples are isothermally aged and thermal cycled from 0 to 100°C with a 10minute dwell time. Based on weibull plots for each aging condition, the lifetime of the package reduced approximately 44% with 150°C aging precondition. The microstructure evolution is observed during thermal aging and thermal cycling with different phase microstructure transformations between electrolytic Ni/Au and OSP surface finishes, focusing on the microstructure evolution near the package side interface. Different mechanisms after aging at various conditions are observed, and their impacts on the fatigue life of solder joints are discussed.

3-D Stacked Package Technology and Trends

The need to integrate more device technology in a given board space for handheld applications such as mobile phones has driven the adoption of innovative packages which stack such devices in the vertical or third dimension (3D). Stacking of device chips in small and thin fine-pitch ball grid array packages has evolved into the stacking of packages themselves to achieve the same end. The advantage of stacking packages rather than device chips is that packages can be fully tested good prior to stacking. There are two primary ways to stack packages to achieve such vertical integration: package-on-package (PoP) and package-in-package (PiP). Innovative variations of PoP and PiP are being developed to address specific packaging needs and market trends. This paper will detail some of the key technology supporting PoP and PiP packages currently in production and the development of new variations of such packages to address future trends.

Investigation of mechanical shock testing of lead-free SAC solder joints in fine pitch BGA package

The lead-free Sn–Ag–Cu (SAC 305/405) solder that replaced the tin–lead eutectic solder tends to be more brittle in nature due to high stiffness and excessive solder interfacial reactions. This leads to higher occurrences of solder joints failure during surface mount assembly and handling operations as a result of PCB bending, shock impact and drop. In this work, mechanical tests simulating the shock impact were conducted on lead-free SAC of different weight percentages. These SAC materials were prepared for use in the solder joints of fine pitch ball grid array (BGA) components which were mounted onto the motherboard. After the mechanical shock tests, strain measurements were performed on the BGA components to gauge the solder joint integrity, which was shown to be related with the formation of intermetallics in the bulk and at the interface of the SAC solder. The ball pull tests were conducted to determine both the bulk and interfacial strength and the solder joint fracture, which was classified as either mode 1, 2 or 3. A correlation was made between the silver (Ag) and copper (Cu) weight percentages with the metallurgical reactions.

Thermo-mechanical reliability tradeoffs for deployment of area array packages in harsh environments

Fine-pitch ball grid arrays (BGAs) and underfills have been used in benign office environments and wireless applications for a number of years, however their reliability in harsh environments is not well understood. In this work, the design guidelines development effort for deployment of fine-pitch ball-grid array packages in the harsh environments have been presented. Guidelines are targeted toward government contractors, OEMs, and third party contract manufacturers who intend to select part architectures and board designs based on specified mission requirements. The guidelines are intended as an aid for understanding the sensitivity of component reliability to geometry, package architecture, material properties and board attributes in different thermal environments in order to quantitatively evaluate the impact of these parameters on the component reliability. The intent is to develop a tool for doing tradeoffs between geometry, materials and quantitatively evaluating the impact on reliability. Sensitivity relations for geometry, materials, and architectures based on statistical models and failure mechanics based closed form models have been developed. Convergence between statistical model sensitivities and failure mechanics based sensitivities has been demonstrated. Predictions of sensitivities have been validated against experimental test data.