Fine ADC Research Articles

A Low-Power DROIC With Extended-Counting ADC for Uncooled Infrared Silicon Diode Detectors

A low-power digital readout integrated circuit (DROIC) for silicon diode uncooled infrared focal plane arrays (IRFPAs) is presented. The DROIC adopts a 14-bit column-level extended-counting analog-to-digital converter (ADC) based on a cascade of a coarse continuous-time Σ-ADC and a fine single-slope ADC. While the weak detector signal is integrated, the coarse conversion is implemented by a feedback current-steering digital-to-analog converter (IDAC), which shortens the signal chain and reduces the bandwidth requirement for the op-amp, to reduce power consumption. Besides, the ramp signal of the fine conversion is generated locally by an additional column-level IDAC, which matches the coarse conversion IDAC to decrease the DNL. Also, a low-power non-uniformity calibration circuit is adopted to compensate the non-uniformity of the IRFPA and adjust the ADCfs input signal range. The DROIC with 1024 ×768 pixel array is fabricated in a 0.18μm CMOS process. The experimental results demonstrate the DROIC consumes 109mW. The noise is 1.7LSB and the equivalent input noise voltage of the column circuit is about 2.1μVrms. The INL and DNL are less than +6.1LSB/.4.4LSB and +0.40LSB/.0.38LSB, respectively.

A 6-Bit 20 GS/s Time-Interleaved Two-Step Flash ADC in 40 nm CMOS

A 6-bit 20 GS/s 16-channel time-interleaved (TI) analog-to-digital converter (ADC) using a two-step flash ADC with a sample-and-hold (S/H) sharing technique and a gain-boosted voltage-to-time converter (VTC) is presented for high-speed wireline communication systems. By sharing one S/H between coarse and fine stages in the two-step flash ADC, the input bandwidth as well as area and power efficiency can be improved without a gain error between coarse and fine ADCs. Thanks to an eight-time interpolation using the gain-boosted VTC, the fine ADC has a small gate capacitance without a speed penalty, even in a small input voltage range. A prototype ADC implemented in a 40 nm CMOS process occupies a 0.1 mm2 active area. The measured differential non-linearity (DNL) and integral non-linearity (INL) after offset and gain calibrations were 0.45 and 0.39 least significant bit (LSB), respectively. With a 9.042 GHz input, the measured signal-to-noise and distortion ratio (SNDR) and the spurious-free dynamic range (SFDR) were 30.12 and 40.23 dB, respectively. The small input capacitance of the sub-ADC enables a power-efficient track-and-hold amplifier (THA), resulting in a power consumption of 56.2 mW under a supply voltage of 0.9 V. The prototype ADC achieves a figure of merit (FoM) of 107.4 fJ/conversion-step at 20 GS/s.

A 7-Bit Two-Step Flash ADC With Sample-and-Hold Sharing Technique

A 7-bit 3 GS/s two-channel time-interleaved two-step flash analog-to-digital converter (ADC) with 7-GHz effective resolution bandwidth (ERBW) is presented. A reference-embedding flash ADC for a fine stage having only a single capacitive digital-to-analog converter improves the power efficiency and area efficiency as well as the input bandwidth. The proposed sample-and-hold sharing structure not only improves the input bandwidth by removing the effect of the input capacitance of the fine ADC (FADC) but also eliminates the gain error between the coarse ADC and the FADC. The advanced sequential slope-matching offset calibration technique in the eight-time interpolated FADC improves the gain of the voltage-to-time converter and the interpolation linearity. A prototype ADC implemented in a 40-nm CMOS process occupies 0.03 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> , including offset calibration circuitry. The measured peak differential non-linearity (DNL) and integral non-linearity (INL) after calibration are 0.53 and 0.47 LSB, respectively. With a 1.49-GHz input, the measured signal-to-noise and distortion ratio (SNDR) and spurious-free dynamic range (SFDR) are 39.94 and 55.78 dB, respectively. The ERBW without and with time skew calibration is 4.8 and 7 GHz, respectively. The power consumption is 6.8 mW under a supply voltage of 0.9 V, leading to a figure of merit (FoM) of 28 fJ/conversion-step at 3 GS/s.

A 28-nm 10-b 2.2-GS/s 18.2-mW Relative-Prime Time-Interleaved Sub-Ranging SAR ADC With On-Chip Background Skew Calibration

This article presents a relative-prime-based time-interleaved (RP TI) sub-ranging successive-approximation register (SAR) analog-to-digital converter (ADC) with on-chip background skew calibration. The proposed calibration aligns the sampling time of every fine ADC (F-ADC) to that of a particular coarse ADC (C-ADC) that works as a reference ADC. To avoid the unwanted calibration tone from the reference ADC, the C-ADC is also time-interleaved to make all samples undergo the same kick back. By setting the numbers of the time-interleaved channels of the C-ADCs and F-ADCs in a relative-prime relationship, every C-ADC can be evenly shared by every F-ADC; thus, the timing skews between the interleaved sub-ADCs are calibrated by adjusting the sampling edges of every F-ADC to the particular C-ADC working as a reference ADC. An 18-channel TI 10-bit 2.2-GS/s SAR ADC was implemented as a prototype with 28-nm CMOS. Owing to the proposed on-chip background skew calibration, the peak tone by skew was reduced by 23 dB from -40 to -63 dB, which corresponds to the residual skew reduction from 1.6 ps to 113 fs near the Nyquist input. Thus, the prototype ADC achieved a spurious free dynamic range (SFDR) over 52.8 dB and a signal-to-noise-and-distortion ratio (SNDR) over 44.9 dB with 18.2-mW power consumption, which leads to a Walden figure-of-merit (FoM) of 57.8 fJ/conversion-step.

Built-in Harmonic Prediction Scheme for Embedded Segmented-Data-Converters

Increase in manufacturing test cost is of paramount issue to chip suppliers, which has been primarily due to costly external testers and long test-time. This paper proposes a loopback-based self-test technique to cost-effectively predict the dynamic nonlinearities of on-chip segmented digital-to-analog-converter (DAC) and analog-to-digital-converter (ADC), by externally looping a DAC back to an ADC, through an external load board employing two parallel paths: a programmable-gain-amplifier (PGA) path and a bypass path for test purpose. A segmented DAC (or ADC) consists of coarse and fine DACs (or ADCs). Two loopback tests are sequentially performed. For the first loopback test, a clean and single-tone sinusoidal signal is applied to a coarse DAC, and it bypasses a fine DAC for test purpose. The obtained DAC output is then fed to a coarse ADC through a bypass path on the load board. Simultaneously, the DAC output is applied to a fine ADC through a PGA path, so that the DAC output signal can fit into the input full-scale range of the fine ADC. For the second loopback test, a sinusoid is fed to a fine DAC, and it bypasses a coarse DAC in this time. Similarly, the DAC output is then applied to a fine and a coarse ADCs through two paths on the load board, at the same time. For postprocessing in on-chip processor, the correlation equations between the dynamic nonlinearities of sub-DACs/ADCs and the aforementioned loopback responses are simultaneously solved to predict the dynamic nonlinearity for each of a DAC and an ADC. Simulation and hardware measurements verified that the proposed technique can be practically used for production testing, by showing less than 0.28-dB and 0.55-dB of the prediction errors, respectively.

A Calibration-Free 13-Bit 10-MS/s Full-Analog SAR ADC With Continuous-Time Feedforward Cascaded Op-Amps

This paper presents a calibration-free 13-bit 10-MS/s full-analog successive-approximation-register analog-to-digital converter (SAR ADC) in 40-nm CMOS, which fully utilizes the timing and power budgets in a bit-conversion cycle by eliminating the digital circuits entirely. Continuous-time feedforward cascaded (CTFC) op-amps are proposed to enhance the residue power without the necessity of high-precision quantizers. As opposed to the residue amplifiers (RAs) in multi-step/pipelined ADCs, the CTFC op-amps in the open-loop configuration are implemented with the relaxing gain–bandwidth product (GBW) and without the limitations of accurate gain, precise settling, and voltage swing. Inverter-based regenerative-amplifier (IRA)-based zero-crossing detectors (ZCDs) with self-triggered amplification-to-regeneration (A-to-R) operation are developed to perform serial full-analog SAR bit conversions. The stability in multiple negative feedback (NFB) loops formed by the CTFC op-amps and ZCDs is analyzed and confirmed. The input-referred noise (IRN) and input-referred offset (IRO) in each bit conversion are suppressed by the CTFC op-amps and tolerated by the digital-to-analog converter (DAC) radix and sub-ADC arrangements. The LSB repeating is adopted to entirely cancel out the suppressed IRO mismatches among the bit conversions in the fine ADC. This work occupies an active area of 0.013 mm2 and achieves the Nyquist-rate signal-to-noise-and-distortion ratio (SNDR), spurious-free dynamic range (SFDR), Walden figure-of-merit (FoMw), and Schreier FoM (FoMS) of 67.6 dB, 77.2 dB, 3.3 fJ/conversion-step, and 176.5 dB, respectively.

A 10-bit 100-MS/s Pipelined SAR ADC with Redundancy Generation using Capacitor-based DAC and Linearity-improved Dynamic Amplifier

A 10-bit 100-MS/s pipelined SAR ADC which consists of a 5-bit coarse SAR ADC with 1-bit redundancy, a dynamic amplifier for a residue amplifier, a 6-bit fine SAR ADC, and a digital error correction is proposed. One-bit redundancy generation for a digital error correction is designed using a capacitor-based DAC used in the 5-bit coarse SAR ADC for a sub-ADC of a pipelined ADC. The input range calibration and dynamic amplifier with gain compensation circuit are proposed to improve the linearity of the pipelined SAR ADC. The proposed pipelined SAR ADC has been implemented using a 65-nm 1-poly 8-metal CMOS process with a 1.2-V supply voltage. Its active area and power consumption are 410 μm × 425 μm and 4.35 mW, respectively. The measured SNDR are approximately 53.47 dB for a 2.4 VSUBpp/SUB differential sinusoidal input with a frequency of 9.99 MHz.

A 2.3-mW, 1-GHz, 8-Bit Fully Time-Based Two-Step ADC Using a High-Linearity Dynamic VTC

A novel fully time-based two-step analog-to-digital converter (ADC) is proposed. Two time-based ADCs (TB ADCs) are used for coarse ADC (CADC) and fine ADC (FADC), resulting in low-power operation. They are pipelined to increase the sampling frequency. A high-linearity voltage-to-time converter is also proposed to ensure that the CADC has a wide input range. It has a gain-control function to adjust the difference between the gains of the CADC and FADC due to variations in process, voltage and temperature. Moreover, an interpolation time-to-digital converter with a dynamic delayer enables low-power operation. The dynamic delayer is immediately reset when a STOP signal is activated to prevent waste-signal propagation. An 8-bit test chip fabricated with the 65-nm CMOS technology consumed 2.3 mW at 1 GS/s. It also had a sufficiently high signal-to-noise and distortion ratio (SNDR) of 44.4 dB even at the Nyquist frequency. It had a Walden figure of merit of 16 fJ/conversion step.

A 10-bit 50-MS/s SAR ADC with 1 fJ/Conversion in 14 nm SOI FinFET CMOS

A 10-bit Successive Approximation Register (SAR) Analog to Digital Converter (ADC) was implemented in a 14 nm SOI FinFET CMOS technology, achieving 59.59 dB SNDR at 50 MS/s while consuming 41.3 µW power. Several techniques were used to increase the energy efficiency while ensuring the linearity. First, a segmented architecture with a 5-bit coarse ADC and an 11-bit fine ADC was used. The aligned Switching with Skip (ASS) method was used to generate the five MSBs of the fine ADC from the computed coarse ADC bits, saving 58% switching power compared with non-segmented architecture with merged capacitor switching (MCS) method. Second, VCM-based MCS scheme is used for SAR bit resolving, saving 85.72% switching power compared with traditional SAR switching. Third, the dual supply mode with analog at 0.8 V and digital at 0.4 V was used. This reduces the total digital logic power consumption by 23% comparing with that using the single supply at 0.8 V. The differential architecture was used to minimize the common mode non-idealities. The proposed ADC has been implemented in a 14 nm SOI FinFET technology and achieved a peak Figure of Merit (FoM) of 1.07 fJ/Conversion-step with simulation results.

A 500-MS/s, 2.0-mW, 8-Bit Subranging ADC with Time-Domain Quantizer

This paper describes a novel energy-efficient, high-speed ADC architecture combining a flash ADC and a TDC. A high conversion rate can be obtained owing to the flash coarse ADC, and low-power dissipation can be attained using the TDC as a fine ADC. Moreover, a capacitive coupled ramp circuit is proposed to achieve high linearity. A test chip was fabricated using 65-nm digital CMOS technology. The test chip demonstrated a high sampling frequency of 500 MHz and a low-power dissipation of 2.0 mW, resulting in a low FOM of 32 fJ/conversion-step.

A 10-b 200-kS/s 250-nA Self-Clocked Coarse–Fine SAR ADC

A 10-b ultralow-power successive approximation register (SAR) analog-to-digital converter (ADC) implemented in a standard 0.18- $\mu\text{m}$ CMOS technology is described. The architecture consists of a coarse and a fine SAR ADC. The 2-b coarse SAR presets the two MSB capacitive arrays of the fine SAR, thus avoiding the largest sources of dynamic power consumption. The use of two low-resolution comparators in the coarse converter enables compensating for the offset mismatches between the coarse and fine ADCs. The comparator of the fine SAR ADC obtains high sensitivity and very low power owing to a gain-enhanced dynamic preamplifier. A loop delay line generates all the phases for the SAR logic and permits three different modes of operation: on-demand, self-clocked, and clocked. In the clocked mode and at 200 kS/s, this converter achieves a 9.05-b effective number of bits (ENOB) while consuming 200 nW. The resulting figure of merit (FoM) is 1.88 fJ/conversion-level.

A 1 V 186-μW 50-MS/s 10-bit subrange SAR ADC in 130-nm CMOS process**Project supported by the National Natural Science Foundation of China (Nos. 61204033, 61331015), the Fundamental Research Funds for the Central Universities (No. WK2100230015), and the Funds of Science and Technology on Analog Integrated Circuit Laboratory (No. 9140C090111150C09041).

This paper presents a 10-bit 50-MS/s subrange successive-approximation register (SAR) analog-to-digital converter (ADC) composed of a 4-bit SAR coarse ADC and a 6-bit SAR fine ADC. In the coarse ADC, multi-comparator SAR architecture is used to reduce the digital logic propagation delay, and a traditional asynchronous SAR ADC with monotonic switching method is used as the fine ADC. With that combination, power dissipation also can be much reduced. Meanwhile, a modified SAR control logic is adopted in the fine ADC to speed up the conversion and other techniques, such as splitting capacitors array, are borrowed to reduce the power consumption. Fabricated with 1P8M 130-nm CMOS technology, the proposed SAR ADC achieves 51.6-dB signal to noise and distortion ratio (SNDR) and consumes 186 μW at 50 MS/s with a 1-V supply, resulting in a figure of merit (FOM) of 12 fJ/conversion-step. The core area is only 0.045 mm2.

A Low-Power TDC-Configured Logarithmic Resistance Sensor for MLC PCM Readout

This paper proposes a low-power logarithmic resistance sensor for multi-level cell phase-change memory readout. The proposed sensor is composed of a resistance-to-current converter (R2I) and a current-to-digital converter (I2D). A simple bleeding current source pair added to the R2I enhances the current settling speed and the sensing accuracy. The two-step I2D with a time-to-digital converter-configured fine ADC could be designed with low-power consumption and small size owing to the time-reference generator that is shared by multiple channels and incorporates interpolation and size-scaling techniques. The total conversion time of the readout sensor, including the R2I conversion, is 100 ns, and the power consumption of a single-channel readout sensor is 60 μW under a 1.2 V supply. The ratio of the minimum decision step size to the full scale input current of the I2D corresponds to that of a conventional 9.6-b linear ADC. The prototype sensor is composed of 14-channels sharing a single time-reference generator, where each narrow single channel occupies 19 μm × 590 μm in a 65-nm CMOS process.

An asynchronous 12-bit 50 MS/s rail-to-rail Pipeline-SAR ADC in 0.18 μm CMOS

This paper presents a 12-bit 50MS/s asynchronous rail-to-rail Pipeline-SAR ADC. Design optimization is performed to achieve low power and high performance. The ADC consists of a 6-bit coarse SAR ADC, a residue amplifier and a 7-bit fine SAR ADC. A novel highly linear, power efficient switching scheme for the 2nd stage SAR ADC is proposed. The ADC operates asynchronously in order to simplify the design and save power. The ADC achieves low-power, high-resolution and high-speed operation without calibration. The ADC was fabricated in 0.18μm CMOS process with 1.8V power supply range. The proposed SAR ADC achieves 67.01dB SNDR and 77.13dB SFDR with sampling rate up to 50MS/s, corresponding to a figure-of-merit of 110fJ/conversion-step. The proposed ADC core occupies an active area of about 450×700µm2.

A low power 11-bit 100 MS/s SAR ADC IP

This paper presents a dual-channel 11-bit 100 MS/s hybrid SAR ADC IP. Each channel adopts flash-SAR architecture for high speed, low power and high linearity. Dynamic comparators in the coarse flash ADC and the fine SAR ADC further contribute to the reduction of power consumption. A gate-controlled ring oscillator generates a multi-phase clock for SAR logic, thereby allowing it to asynchronously trigger the comparator in the fine SAR ADC in high speed. MOM capacitors with a fully shielded structure provide enough matching accuracy without the need for calibration. This design was fabricated in SMIC 55 nm low leakage CMOS technology and the active area of dual-channel (I-Q) ADC is 0.35 mm2, while the core area is 0.046 mm2. It consumes 2.92 mA at a 1.2 V supply, for dual-channel too. The effective number of bits (ENOB) is 9.90 bits at 2.4 MHz input frequency, and 9.34 bits at 50 MHz, leading to a FOM of 18.3 fJ/conversion-step.

Design of a CMOS Image Sensor Based on a 10-bit Two-Step Single-Slope ADC

In this paper, a high-speed CMOS Image Sensor (CIS) based on a 10-bit two step Single Slope A/D Converter (SS-ADC) is proposed. The A/D converter is composed of both 5-bit coarse ADC and a 6-bit fine ADC, and the conversion speed is 10 times faster than that of the single-slope A/D convertor. In order to reduce the pixel noise, further, a Hybrid Correlated Double Sampling (H-CDS) is also discussed. The proposed A/D converter has been fabricated with 0.13um 1-poly 4-metal CIS process, and it has a QVGA (320 x 240) resolution. The fabricated chip size is 5 mm x 3 mm, and the power consumption is about 35 mW at 3.3 V supply voltage. The measured conversion speed is 10 us, and the frame rate is 220 frames/s.

10-bit Two-Step Single Slope A/D 변환기를 이용한 고속 CMOS Image Sensor의 설계

In this paper, a high-speed CMOS Image Sensor (CIS) based on a 10-bit two-step single-slope A/D converter is proposed. The A/D converter is composed of both a 5-bit coarse ADC and a 6-bit fine ADC, and the conversion speed is 10 times faster than that of the single-slope A/D converter. In order to have a small noise characteristics, further, a Digital Correlated Double Sampling(D-CDS) is also discussed. The proposed A/D converter has been fabricated with 0.13um 1-poly 4-metal CIS process, and it has a QVGA() resolution. The fabricated chip size is , and the power consumption is about 35mW at 3.3V supply voltage. The measured conversion speed is 10us, and the frame rate is 220 frames/s.

Employing Threshold Inverter Quantization (TIQ) technique in designing 9-Bit folding and interpolation CMOS analog-to-digital converters (ADC)

This paper presents design and implementation of a 9-bit folding and interpolation ADC using 0.35 µm CMOS C35B4 model under AMS-HIT Kit Library. The complete system consists of two main blocks. One of them is 4-bit flash ADC, which is based on the so-called Threshold Inverter Quantization (TIQ) technique. This part forms the coarse part of the data conversion process. The second one is the 5-bit fine ADC part of the converter. This block includes comparator, analog pre-processing and interpolation units. The designed converter works with 5 V power supply, and has analog input range of 3.4 Vpp. Analog input bandwidth is 1 MHz with clock frequency of 2 GHz for the digital part. The linearity measures of the converter include 2.9 LSB of DNL and 6.3 LSB of INL. The main purpose of this work is to investigate the possibility of employing TIQ technique in designing folding and interpolation type of ADCs. Although, the linearity measures are not satisfying for 9-bit case, the authors believe that this case study will serve as a preferred reference for the researchers who are willing to use TIQ technique in designing fast ADCs other than flash scheme especially. Key words: Threshold inverter quantization, flash analog-to-digital converter, folding and interpolation analog-to-digital converter.

Design of a 770-MHz, 70-mW, 8-bit Subranging ADC Using Reference Voltage Precharging Architecture

This paper describes a high-speed, low-power CMOS subranging analog-to-digital converter (ADC). A reference voltage precharging architecture and the introduction of a comparator with a built-in threshold voltage in the fine ADC are proposed to reduce the settling time of the reference voltage. A T/H circuit with a body-bias control circuit is employed to reduce distortion at a high sampling rate. Moreover, a <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">TH</sub> generator using a replica of the original comparator is also proposed to compensate for <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">TH</sub> deviation due to the process variations. A test chip was fabricated using 90-nm CMOS technology, and showed a high-sampling rate of 770 MS/s and a low-power consumption of 70 mW.

A 150 MS/s 10-bit CMOS Pipelined Subranging ADC with Time Constant Reduction Technique

A 150MS/s 10-bit MOS-inverter-based subranging analog-to-digital converter (ADC) dedicated to a high-speed low-power application is presented in this paper. A new time constant reduction technique is proposed in the multi-stage preamplifier design which aims to further increase the speed of the coarse ADC. A synchronized switch is introduced to minimize the sample-time mismatch in the interleaved architecture of fine ADCs. An internal pipelined scheme incorporating the double sampling and interleaving techniques in fine ADCs allows the ADC sample input signal to run on a consecutive clock, thus maximizing the throughput. The prototype ADC achieves 52dB SNDR for a 10MHz input frequency at 150MS/s. Without calibration, the measured differential nonlinearity (DNL) is 0.5 LSB, while the integral nonlinearity (INL) is 0.9 LSB. The CMOS ADC is fabricated in a 0.35µm CMOS technology, with an active area of 2.7mm2, consuming only 178mW from a single 3V supply. Comparing technology normalized figure-of-merits, it achieves better power-speed efficiency than other similar types of ADCs.