Abstract
This paper describes a novel energy-efficient, high-speed ADC architecture combining a flash ADC and a TDC. A high conversion rate can be obtained owing to the flash coarse ADC, and low-power dissipation can be attained using the TDC as a fine ADC. Moreover, a capacitive coupled ramp circuit is proposed to achieve high linearity. A test chip was fabricated using 65-nm digital CMOS technology. The test chip demonstrated a high sampling frequency of 500 MHz and a low-power dissipation of 2.0 mW, resulting in a low FOM of 32 fJ/conversion-step.
Highlights
With CMOS scaling, the performance of digital circuits has been improved dramatically
A high conversion rate can be obtained owing to the flash coarse analog-to-digital converters (ADCs), and low-power dissipation can be attained using the to-digital converter (TDC) as a fine ADC
A test chip was fabricated using 65-nm digital CMOS technology to demonstrate the effectiveness of the proposed architecture
Summary
With CMOS scaling, the performance of digital circuits has been improved dramatically. Analog LSIs operating in the millimeter wave frequency and the THz region appeared owing to the improvement in the cut-off frequency by scaling. Negative aspects due to scaling, that is, the drop in the intrinsic gain, the increase in device variation, and the decrease in the signalto-noise ratio due to low supply voltage, are revealed. A time-domain approach that expresses an analog signal in the time domain has especially attracted much attention. Time-domain signal processing is advantageous in that the signal expression is not limited to the supply voltage and in that most circuits can use digital circuits; it can enjoy the benefit of CMOS scaling.
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