Final ASIC Research Articles

Design of 2-1 Multiplexer based high-speed, Two-Stage 90 nm Carry Select Adder for fast arithmetic units

This paper proposes a new Two-Stage Carry Select Adder (TSCSA) using a single type of leaf cell i.e., a 2-1 Multiplexer. All the existing Carry Select Adders (CaSeAs) are constructed with three stages. The first stage produces the result with input carry ‘0’, the second stage generates an excess-1 result and the third stage is used to select one of the results using multiplexers. The proposed 4-, 8-, 16-, 32-, and 64-bit TSCSA are distinctly designed in two stages only. The carry propagation through adders and full adders is completely eliminated which is the main bottleneck problem for high-speed arithmetic units. A 64-bit TSCSA is distinctly decomposed for maintaining excellent cell regularity that uses one type of cell i.e., 2-1multiplexer. Ripple carry adder blocks in existing designs are replaced with half adders by eliminating the carry propagation. At the outset, the speed of TSCSA is improved by overcoming carry propagation through adder blocks, especially in higher-order adders. The area is the major concern for CaSeAs; is also reduced for TSCSA by maintaining cell regularity. Verilog HDL is used in the design of the TSCSA and existing CaSeAs. Using Cadence NCLaunch, all of the designs are functionally tested. At the 90 nm technology node, all of the designs are generated and executed using Cadence Genus and Innovus, respectively. In comparison to current designs, there is marginal improvement in area and power but there is substantial improvement in speed. The proposed 64-bit TSCSA final ASIC architecture is 9% more compact and dissipates 13% less power. According to the comparison and result analysis, TSCSAs have 69% superior speed than existing designs. As a result, TSCSA works best in low-power, small-area, and fast applications.

A 90 nm area and power efficient Carry Select Adder using 2–1 multiplexer based Excess-1 block

This paper proposes a novel architecture of excess-1 adder-based Carry Select Adder (M2CSA) using single leaf cell i.e., 2–1 Multiplexer. M2CSA is designed using a new type of Excess-1 block. The Excess-1 block is designed in a distinct way using 2–1 multiplexers. The architectures of the proposed carry select adder and its internal excess-1 blocks are completely distinct when compared to existing carry select adders. The proposed 4-, 8-, 16-, 32-, and 64-bit M2CSAs use a 2–1 multiplexer only. The complex gates such as XOR gates are eliminated which exist in existing Carry Select Adders (CaSeAs). A 64-bit M2CSA that utilises one kind of 2-1 Mux cell is clearly decomposed to retain outstanding cell regularity. In previous designs, ripple carry adder blocks are substituted with half adders by limiting carry propagation to a particular degree. By avoiding carry propagation over adder blocks, particularly in 32- and 64-bit adders, the performance of M2CSA is initially increased. For CaSeAs, the area is of primary significance; for M2CSAs, it is also diminished by preserving cell regularity. Verilog HDL is utilised in the design of the M2CSA and current CaSeAs. Using Cadence NCLaunch, all of the designs are functionally tested. At a 90nm technology node, all of the designs are generated and executed using Genus and Innovus tools, respectively. As a comparison to prior designs, the 64-bit M2CSA final ASIC architecture is on average 17% less in terms of space. The comparison and result analysis show that 64-bit M2CSA performs 20% and 19% faster than 64-bit SQCSC in terms of performance and power dissipation, respectively.. The proposed 4-, 8-, 16-, 32-, 64- bit M2CSA exhibits less PDP (Power-Delay Product) ranging from 25%–30% concerning SQCSCs. Similarly, EDP (Energy- Delay Product) values for all the designs are calculated. The improvement in EDP for the 4-, 8-, 16-, 32-, 64- bit M2CSA is 41, 38, 42, 43, and 45 percentages compared to 4-, 8-, 16-, 32-, 64- bit SQCSC respectively. Therefore, the M2CSAs outperform the existing designs in terms of EDP by 38%–45%.

Design and first tests of the Gotthard-II readout ASIC for the European X-ray Free-Electron Laser

Gotthard-II is a charge-integrating microstrip detector developed for experiments and diagnostics at free-electron lasers using hard X-rays of 5 keV–20 keV. Thanks to its excellent single photon sensitivity, large dynamic range as well as high frame rate of 4.5 MHz in burst mode, its potential scientific applications include X-ray absorption/emission spectroscopy, hard X-ray high resolution single-shot spectrometry (HiREX), beam diagnostics, as well as veto signal generation for pixel detectors. The Gotthard-II ASIC has been designed and fabricated using UMC-110 nm technology. The final ASIC design and performance in terms of noise, linearity, dynamic range, coupling between channels and speed will be discussed in the paper. In addition, a first measurement of an X-ray absorption spectrum of a standard copper sample has been done. The performance of the Gotthard-II in an experiment using energy dispersive X-rays has been demonstrated.

Silicon sensors with various pixel geometries adapted for a common readout ASIC

ATLAS is proposing to replace the entire tracking system for HL-LHC operation. The ``Letter of Intent'' baseline pixel size at higher radii was 50 × 250μm2 (φ × η), based on the FE-I4 readout chip, and this was optimized for the central barrel region. The detector tracking performance in the end-cap pixel disks can benefit from enhanced resolution in the radial direction to improve the impact parameter resolution in z-coordinate (along the beam line) for high η tracks, which is critical in the high pile-up environment of the HL-LHC. So called ``strixel'' geometries, with long narrow pixels, can be proposed at higher z in the barrel where tracks pass through at large angles. Larger pixels may also be considered for an additional pixel layer if this could reduce the requirements, and therefore costs, for the outer part of the tracker.While ATLAS pixel upgrade plans are evolving, the demonstration of providing a variety of sensor pixel shapes and sizes for a common ASIC pixel geometry will be of general application, whatever the final ASIC design.This paper will report on the development and testing of pixel sensors with several different dimensions assembled into modules with the FE-I4 readout chip. Some of these were irradiated (with protons, 1015 neq/cm2) and evaluated at the DESY test beam. These, together with the test beam results with non-irradiated sensors, will be shown, as well as the results from laboratory characterization.

Simulation and Emulation of MIMO Wireless Baseband Transceivers

The development of state-of-the-art wireless communication transceivers in semiconductor technology is a challenging process due to complexity and stringent requirements of modern communication standards such as IEEE 802.11n. This tutorial paper describes a complete design, verification, and performance characterization methodology that is tailored to the needs of the development of state-of-the-art wireless baseband transceivers for both research and industrial products. Compared to the methods widely used for the development of communication research testbeds, the described design flow focuses on the evolution of a given system specification to a final ASIC implementation through multiple design representations. The corresponding verification and characterization environment supports rapid floating-point and fixed-point performance characterization and ensures consistency across the entire design process and across all design representations. This framework has been successfully employed for the development and verification of an industrial-grade, fully standard compliant, 4-stream IEEE 802.11n MIMO-OFDM baseband transceiver.

A framework for the design, synthesis and cycle-accurate simulation of multiprocessor networks

This paper introduces a framework for the design, synthesis and cycle-accurate simulation for parallel computing networks of 128+ processors. In order to accurately characterize the network, we present a bottom-up design methodology in which each of the components are designed using a hardware description language and synthesized to an FPGA for performance estimation of the final ASIC implementation. The components are then integrated to form a parallel computing network and simulated using a cycle-accurate simulator with network traffic described by command files. This enabled us to simulate various switching techniques, three of which are presented in this paper: wormhole switching, circuit switching and a newly introduced technique called predictive circuit switching. In our experiments, four different representational traffics are generated for our simulation and, to show the flexibility of this model, we vary the cable lengths and thus their latency for all four test cases. Our results show that this hardware design, synthesis and cycle-accurate simulation methodology provides a useful method for evaluating design tradeoffs in parallel networks. A non-blocking queue, with up to 128 internal queues, and a real-time bandwidth scheduler, for up to 128 ports, were designed in hardware with hardware synthesis results presented. From our network simulation results, we conclude that predictive circuit switching exceeds the performance of packet switching for highly predictable traffic, like collective communications, and for heavily loaded unpredictable traffic with small packet sizes. As expected, predictive circuit switching significantly underperforms both packet and circuit switching for unpredictable traffic.

Efficiency studies of the front-end trigger device of the muon drift tubes for the CMS detector at LHC

Three simplified prototypes of the first-level trigger front-end device for the muon barrel drift chambers of CMS were tested on a chamber prototype. Tests were performed at several incidence angles of a muon beam and with different magnetic field configurations. The recorded drift times were also used to test a full software model reproducing the actual algorithm applied in the final ASIC being produced. The efficiency performance of this software model and of the tested prototype are presented in this paper.