Fin-shaped Field-effect Transistors Research Articles

An 8T Low-Voltage and Low-Leakage Half-Selection Disturb-Free SRAM Using Bulk-CMOS and FinFETs

In this paper, we present a new 8T design for static random access memory (SRAM) cell that is based on traditional Si technology and reduces leakage power considerably compared with a conventional design. Proposed design can be fully functional at smaller supply voltages over the conventional 6T SRAM cell. To verify the proposed design, a 32 kb SRAM is designed and simulated in 90 nm CMOS technology using the proposed 8T and conventional 6T SRAM cells. Operating at their VDD \(_{\min }\) , simulations show improvement of 58% and 67% for write and read power per operation, respectively, for our design. To address the challenge of half-selection during write operation, a new low-power internal write-back scheme is presented. Finally, designing proposed cell using fin-shaped field effect transistors shows less sensitivity to variations and also improvement of \(2.08\times \) in read static noise margin at \({\rm VDD}=1.0\) V over bulk-CMOS-based SRAM cell.

High-Performance GaN-Based Nanochannel FinFETs With/Without AlGaN/GaN Heterostructure

Two types of fin-shaped field-effect transistors (FinFETs), one with AlGaN/GaN heterojunction and the other with heavily doped heterojunction-free GaN layer operating in junctionless mode, have been fabricated and characterized. The threshold voltages of both devices shift toward positive direction from large negative value as the fin width decreases. Both devices exhibit high ON-state performance. The heterojunction-free GaN FinFETs show superior OFF-state performance because the current flows through the volume of the GaN channel layer, which can be fully depleted. The proposed GaN nanochannel FinFETs are very promising candidates not only for high performance, but also for high power applications.

DESIGN DIFFERENT TOPOLOGY FOR REDUCTION OF LOW POWER 2:1 MULTIPLEXER USING FINFET IN NANOMETER TECHNOLOGIES

The intention of this paper is to reduce power and area of 2:1 multiplexer (MUX) while maintaining the competitive performance. The various configurations are designed using different topology of 2:1 MUX such as CMOS-based MUX, transmission gate and pass transistor using fin-shaped field effect transistor (FINFET). The mobility was enhanced in devices with taller fins due to increase tensile stress. In DG, FINFET can be efficiently used to develop performance and reduce power consumption. In noncritical paths self-determining gate control can be used to join together parallel transistors. We have estimated the optimum power, optimum current, leakage power, leakage current, operating power, operating current and delay in voltage supply 0.7 V at different temperature such as 10°C, 27°C and 50°C, respectively. A 20 ns access time and frequency 0.5 GHz provide 45 nm CMOS process technology with 0.7 V power supply is employed to carry out different topology of 2:1 MUX using FINFET.

Critical dimension metrology by through-focus scanning optical microscopy beyond the 22 nm node

We present results using simulations and experiments to demonstrate metrological applications of the through-focus scanning optical microscopy (TSOM) down to features at and well below the International Technology Roadmap for Semiconductors' 22 nm node. The TSOM method shows the ability to detect sub-nanometer, three-dimensional shape variations such as line height, sidewall angle, width, and pitch in fins of fin-shaped field effect transistor structures using conventional optical microscopes. In addition, the method requires targets substantially smaller than the conventional target size. These results provide insight into the applicability of TSOM for economical critical dimension and yield enhancement metrology.

Negative Impact of Etched Si Area on Selectivity and Positive Impact of Photoelectric Current on Etched Profile in Gate Etching with Different Wafer Bias Frequencies

The effect of wafer-bias frequency on the dummy-gate fabrication of fin-shaped field-effect transistor (Fin-FET) was investigated. The clear difference in the selectivity of polycrystalline silicon to SiO2 between 400 kHz and 13.56 MHz decreased when the etched Si area increased. On the other hand, a higher frequency increased such selectivity when Si area decreased. These results can be explained by the effect of by-product deposition. As for the etched profile, the amount of side etching was much larger at 13.56 MHz than at 400 kHz. It was reported that this phenomenon is caused by local charging. It was also suggested that the charging should be suppressed by reducing the ratio of ion saturation current to photoelectric current. Therefore, in this study, we investigated the effect of such current ratio on side etching. The result confirmed that a reduction in current ratio induced by increasing gas pressure decreases the amount of side etching.

Improved modeling of gate leakage currents for fin–shaped field–effect transistors

Recently, we developed a symmetric doped double gate model for MOSFETs, which includes a direct tunneling model for gate current considering its dependence on the voltages applied to the gate and drain electrodes. Since different tunneling mechanisms can dominate the gate and drain/source leakage currents depending on the transistor operation regime, the gate stack dimensions and the insulating materials used as gate dielectric, in this work, we analyze and model specific features of such currents in SOI FinFET devices. We present an analytical model which takes into account three main conduction mechanisms of leakage currents associated with the gate structure and is valid for a wide operation range. An improved model to describe the behavior of direct tunneling is proposed to avoid the use of fitting parameters. It is shown that carriers tunneling assisted by trap states in the dielectric material of the overlap regions should be considered, as it can become predominant in the subthreshold regime. Moreover, a band-to-band tunneling model is included because of its large impact on the drain leakage current. The present improved model for gate leakage currents is validated by experimental results obtained on FinFETs with different dimensions, gate dielectric materials and performed under different bias conditions.

Heterojunction-Free GaN Nanochannel FinFETs With High Performance

Heavily doped GaN nanochannel fin-shaped field-effect transistors (FinFETs) without heterojunction have been fabricated and characterized for the first time. Simplified pragmatical technology for GaN epitaxial growth and FinFET process was used to achieve nanodevices with a channel width from 40 to 100 nm and a gate length of 1 μm. They exhibit excellent on-state performance, such as maximum drain current of 670 mA/mm and maximum transconductance of 168 mS/mm. Record off-state performance was measured: extremely low leakage current of ~ 10-11 mA and source-drain breakdown voltage of ~280 V. The subthreshold slope of 68 mV/decade is close to the theoretical limit (60 mV/decade, so far achieved only in SOI MOSFETs) and leads to very high Ion/Ioff ratio of 108 - 109. The proposed heterojunction-free nanochannel GaN FinFET is a very promising candidate not only for high-performance and high-speed integrated circuits but also for high-power applications.

Origin of the low-frequency noise in n-channel FinFETs

The origin of the low-frequency noise is investigated in n-channel fin-shaped field-effect transistors (FinFETs) in terms of the channel length and fin width. In long-channel and wide fin devices, the spectra are dominated by 1/f noise due to carrier number fluctuation, correlated with mobility fluctuations. In long-channel and narrow fin devices, the spectra are composed of both 1/f and excess generation–recombination (g–r) noise components. Analysis of the g–r noise parameters lead to the conclusion that the g–r noise originates from traps in the sidewall gate oxides and in a depletion region near the sidewall interfaces. In short-channel devices, the spectra show 1/f behavior in the weak inversion described by carrier number fluctuations and g–r noise component in the low drain current region, possibly originating from the source and drain contacts process.

Single event upset sensitivity of 45 nm FDSOI and SOI FinFET SRAM

In this work single event upset (SEU) sensitivity of 45 nm fully depleted silicon-on-insulator (FDSOI) static random access memory (SRAM) cell and that of SOI fin-shaped field-effect-transistor (FinFET) SRAM cell have been investigated by 3D TCAD simulations. The critical charges and SEU threshold linear energy transfer (LET) value of the two SRAM cells are consistent due to similar gate capacitance. The low electrical field and the high recombination rate account for the non-sensitivity to SEU in heavily doped drain region. Compared with FDSOI SRAM, SOI FinFET SRAM cell exhibits lower SEU sensitivity at the center of the gate. The smaller sensitive area in SOI FinFET SRAM cell may result in a smaller SEU saturation cross section than that of SOI FinFET SRAM.

Flicker noise in n-channel nanoscale tri-gate fin-shaped field-effect transistors

In n-channel nanoscale tri-gate fin-shaped field-effect transistors with high-k gate dielectric stack, the 1/f noise is investigated, ascribed to the carrier number fluctuations with correlated mobility fluctuations. The overall results show that the gate dielectric trap density is uniform in both top-gate and side-gates and the product Ω=αscμeffCox of the Coulomb scattering coefficient αsc, the effective carrier mobility μeff and the gate oxide capacitance per unit area Cox increase with decreasing the fin thickness due to enhancement of side-gates interface roughness effects.

Variability Analysis of Sense Amplifier for FinFET Subthreshold SRAM Applications

This paper investigates the impact of intrinsic random variability on the robustness of sense amplifier (SA) for fin-shaped field-effect transistor (FinFET) subthreshold static random access memory (SRAM) applications. We employ a model-assisted statistical approach to consider both fin line edge roughness (fin LER) and work function variation, which are regarded as the major variation sources in an advanced FinFET device. Our results indicate that fin LER dominates the overall variability of subthreshold SA robustness and sensing margin. In addition, it is observed that the offset voltage (VOS) of current latch SA calculated solely from threshold voltage (VT) mismatch underestimates the actual variation and is shown to be optimistic. For large-signal single-ended inverter sensing, we find that sense “0” hinders the allowable sensing margin and needs to be carefully designed. Compared with bulk CMOS, the superior electrostatic integrity and variability of FinFET enhance the feasibility of differential sensing in subthreshold SRAM applications.

Performance Comparisons of III–V and Strained-Si in Planar FETs and Nonplanar FinFETs at Ultrashort Gate Length (12 nm)

The exponential miniaturization of Si complementary metal-oxide-semiconductor technology has been a key to the electronics revolution. However, the downscaling of the gate length becomes the biggest challenge to maintain higher speed, lower power, and better electrostatic integrity for each following generation. Both industry and academia have been studying new device architectures and materials to address this challenge. In preparation for the 12-nm technology node, this paper assesses the performance of the In0.75Ga0.25As of III-V semiconductor compounds and strained-Si channel nanoscale transistors with identical dimensions. The impact of the channel material property and the device architecture on the ultimate performance of ballistic transistors is theoretically analyzed. Two-dimensional and three-dimensional real-space ballistic quantum transport models are employed with band structure nonparabolicity. The simulation results indicate three conclusions: 1) the In0.75Ga0.25As FETs do not outperform strained-Si FETs; 2) triple-gate Fin-shaped Field Effect Transistor (FinFET) surely represent the best architecture for sub-15-nm gate contacts, independently from the material choice; and 3) the simulations results further show that the overall device performance is very strongly influenced by the source and drain resistances.

High-performance III-V MOSFET with nano-stacked high-k gate dielectric and 3D fin-shaped structure

A three-dimensional (3D) fin-shaped field-effect transistor structure based on III-V metal-oxide-semiconductor field-effect transistor (MOSFET) fabrication has been demonstrated using a submicron GaAs fin as the high-mobility channel. The fin-shaped channel has a thickness-to-width ratio (TFin/WFin) equal to 1. The nano-stacked high-k Al2O3 dielectric was adopted as a gate insulator in forming a metal-oxide-semiconductor structure to suppress gate leakage. The 3D III-V MOSFET exhibits outstanding gate controllability and shows a high Ion/Ioff ratio > 105 and a low subthreshold swing of 80 mV/decade. Compared to a conventional Schottky gate metal–semiconductor field-effect transistor or planar III-V MOSFETs, the III-V MOSFET in this work exhibits a significant performance improvement and is promising for future development of high-performance n-channel devices based on III-V materials.

Application of inline high resolution x-ray diffraction in monitoring Si/SiGe and conventional Si in SOI fin-shaped field effect transistor processes

This study investigates the application of inline high resolution x-ray diffraction (HRXRD) for process control of Si/SiGe and conventional Si on silicon-on-insulator (SOI) fin-shaped field effect transistors (FinFETs). HRXRD measurements were taken from test pads on production wafers; the process stages under study were pre- and post-fin etch. For the pre-etch stage, HRXRD monitors the Si or Si/Ge thickness, Ge concentration (%), and crystal quality. For thickness, HRXRD results matched the fin height from a corresponding device within 2 Å. When equipped with a 1D detector, the typical measurement time can be as short as 20 min. In the post-etch stage, HRXRD monitors fin pitch with a precision of 3 nm. The choice of diffraction plane has an impact on the signal-to-noise ratio. In particular, the asymmetric 113 reciprocal space map (RSM) has better signal-to-noise than 004 for monitoring Si fins; however, pitch data obtained from these two diffraction planes matches within the measurement precision. The etch process can induce relaxation along the fin height in the Si/SiGe hetero-epitaxial fin and has a deleterious impact on the device’s drive current. Although the RSM is sensitive to such relaxation, a nanobeam diffraction measurement is still needed for quantitative strain measurements. The results show inline HRXRD is a valuable tool for monitoring pre- and post-etch processes during FinFET production. It can track vital fin parameters, including fin height, pitch, and crystal quality, which determine the final device drive current. The measurement is nondestructive and can be taken directly from testing pads in production wafers; it therefore saves testing cost and time and alleviates reliance on destructive techniques like transmission electron microscopy.

Compact Model of Drain Current in Short-Channel Triple-Gate FinFETs

An analytical compact drain current model for undoped (or lightly doped) short-channel triple-gate fin-shaped field-effect transistors (finFETs) is presented, taking into account quantum-mechanical and short-channel effects such as threshold-voltage shifts, drain-induced barrier lowering, and subthreshold slope degradation. In the saturation region, the effects of series resistance, surface roughness scattering, channel length modulation, and saturation velocity were also considered. The proposed model has been validated by comparing the transfer and output characteristics with device simulations and with experimental results. The good accuracy and the symmetry of the model make it suitable for implementation in circuit simulation tools.

Physical Insight Toward Heat Transport and an Improved Electrothermal Modeling Framework for FinFET Architectures

We report on the thermal failure of fin-shaped field-effect transistor (FinFET) devices under the normal operating condition. Pre- and post failure characteristics are investigated. A detailed physical insight on the lattice heating and heat flux in a 3-D front end of the line and complex back end of line-of a logic circuit network-is given for bulk/silicon-on-insulator (SOI) FinFET and extremely thin SOI devices using 3-D TCAD. Moreover, the self-heating behavior of both the planar and nonplanar devices is compared. Even bulk FinFET shows critical self-heating. Layout, device, and technology design guidelines (based on complex 3-D TCAD) are given for a robust on-chip thermal management. Finally, an improved framework is proposed for an accurate electrothermal modeling of various FinFET device architectures by taking into account all major heat flux paths.

A Correlative Analysis Between Characteristics of FinFETs and SRAM Performance

A correlation between the characteristics of the 30-nm <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">LG</i> fin-shaped field-effect transistors and the static random-access memory performance is precisely studied. By investigating an effect of the <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">th</sub> variation to the static noise margin (SNM) variation of two different memory states of the storage node, it is revealed that the <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">th</sub> variations of the pull-up, pull-down, and pass-gate transistors correlate with the SNM. Moreover, the contribution and the severity of each transistor variation to σSNM are clarified.

Ground plane fin-shaped field effect transistor (GP-FinFET): A FinFET for low leakage power circuits

► Proposing a GP-FinFET to decrease the power consumption and short channel effects. ► Studying the device characteristics as a function of the channel doping density and length. ► Studying the characteristics of SRAM cells. ► Performing process variation study. In this paper, a fin-shaped field effect transistor (FinFET) structure which uses ground plane concept is proposed and theoretically investigated. The ground plane reduces the coupling of electric field between the source and drain reducing drain-induced barrier lowering (DIBL). To assess the performance of the proposed structure, some device characteristics of the structure have been compared with those of silicon on insulator-FinFET (SOI-FinFET) and Bulk-FinFET structures (where the BOX layer covers all the regions except the channel region). In addition, we compare different characteristics of static random access memory (SRAM) cells based on the proposed device structure as well as SOI-FinFET and Bulk-FinFET structures. The characteristics include standby power consumption, and read static noise margin (SNM). Finally, the behavior of the proposed device in the presence of dimensional variations (channel length and thin film thickness variations) and random dopant fluctuation (RDF) are studied and compared with those of the other two structures.

Plasma atomic layer deposited TiN metal gate for three dimensional device applications: Deposition temperature, capping metal and post annealing

We evaluated plasma atomic layer deposition (ALD)-based TiN as a gate electrode for the metal-oxide-semiconductor (MOS) devices application by varying thickness, deposition temperature, subsequent metal capping layer and post forming gas anneal (FGA). Lower deposition temperature, thinner TiN, in situ processed ALD TaN capping provides more positive flatband voltage (VFB), compatible for p-type MOS devices. Equivalent oxide thickness (EOT) can be scaled down to ~1.2nm range. With post 450^oC FGA, additional negative VFB shift is observed while EOT is substantially increased (>0.2-0.3nm). Mid-gap work-function behavior is observed with plasma ALD-based TiN, indicating a strong potential candidate metal gate material for replacement gate processed three-dimensional (3-D) devices such as FiN shaped field effect transistor (FiNFET).

Drive current and hot carrier reliability improvements of high-aspect-ratio n-channel fin-shaped field effect transistor with high-tensile contact etching stop layer

A high-aspect-ratio 3D multi-gate n-channel fin-shaped field effect transistor (FinFET) has been integrated with a stressor of a highly tensile nitride film as the initial inter layer dielectric capping layer upon a (110)-orientated silicon-on-insulator wafer. Drastically enhanced electrical performances, such as 190% enhancement of peak channel mobility, 91% of peak transconductance, and 34% of saturation current, etc., are achieved for an NMOS FinFET with a gate length of 90 nm. The Ioff-Ion universal curve also demonstrates an extraordinary drive current gain of 26%. Moreover, the hot carrier injection lifetime can be increased from 7.78 × 102 to 5.26 × 103 year (yr) due to the incorporation of this high-tensile contact etching stop layer and relaxation of the Si crystalline channel layer.