Film Profile Engineering Research Articles

A low-temperature photoresist-based film-profile engineering scheme for fabricating bottom- and double-gated indium–gallium–zinc oxide TFTs

We proposed a novel low-temperature (<110 °C) process scheme based on the film-profile engineering technique for fabricating indium–gallium–zinc oxide thin-film transistors (TFTs) with both bottom-gated (BG) and double-gated (DG) configurations. An organic photoresist (PR) suspended bridge is constructed to shadow the depositing species during the deposition processes of the bottom gate-oxide, channel, and source/drain metal films. An Al2O3 layer deposited at 110 °C using atomic-layer deposition is employed as the bottom gate-oxide layer. Such a low-temperature process allows us to deposit the Al2O3 layer following the formation of the PR suspended bridge, preventing the formation of organic residues between the gate-oxide and channel layers. As a result, excellent device performance in terms of field-effect mobility of 12.1 cm2 V−1 s−1 and subthreshold swing of 141 mV/dec is achieved. Our proposed low-temperature process scheme is readily applicable for fabricating DG TFTs which show substantial enhancements in driving currents.

A novel photoresist-based film-profile engineering scheme for fabricating double-gated, recess-channel IGZO thin-film transistors

We reported an experimental fabrication of double-gated (DG) thin-film transistor (TFT) with IGZO recess-channel using a designer photoresist-based thin-film profile engineering approach. In this approach, an organic shadow mask of photoresist (PR) was formed over a p+-Si wafer that was encapsulated by an oxide layer. The lithographically-patterned PR layer is an effective mask for shadowing reactive species during the subsequent deposition steps of IGZO and Aluminum, enabling the formation of IGZO recess-channel and discrete Al source/drain pads at room-temperature. The top-gate or DG configurations with the Si substrate serving as the bottom-gate were investigated. The fabricated DG TFTs show significant improvements in both ION and IOFF as compared with single-gated TFTs. The proposed process scheme is readily applicable to the back-end-of-line of a chip. This work demonstrates the feasibility of IGZO recess-channel TFTs in various gated configurations, enabling a building block for emerging functional devices for More-than-Moore applications.

Film-profile-engineered ZnO thin-film transistor with gate/drain offset for high-voltage operation

We report the design and fabrication of ZnO thin-film transistors (TFTs) configured with designed gate-to-drain (G/D)-offset structures and an auxiliary gate (AG) in a film-profile engineering (FPE) approach for back-end-of-line high-voltage (HV) operation. The breakdown voltage (VBD) of fabricated FPE TFTs is significantly enhanced from 23 to 90 V by changing the G/D-offset length from −0.3 to 0.5 μm, whereas there is a corresponding decrease in the on-state current and transconductance (Gm). To boost the on-state current, an AG biased in the range of 0–5 V is designed to effectively modulate the resistivity of the G/D-offset region and improve Gm by a factor of 2 while keeping VBD of 65−70 V nearly unchanged. Output characteristics with drain voltage as high as 60 V have been demonstrated, evidencing the promising potential of the ZnO TFTs for HV device applications.

Submicrometer p-Type SnO Thin-Film Transistors Fabricated by Film Profile Engineering Method

We reported the fabrication of submicrometer p-type tin monoxide (SnO) thin-film transistors (TFTs) with a channel length of $0.2~\mu \text{m}$ for back-end-of-line applications using a film profile engineering (FPE) approach. Material analyses indicate that the as-deposited SnO films are amorphous, while be transformed to polycrystalline after a thermal annealing in oxygen ambient. Fabricated p-type SnO FPE-TFTs of a channel length of $0.2~\mu \text{m}$ were manifested with ON/OFF current ratio higher than 105 and subthreshold slope of 320 mV/decade, superior to the data of submicrometer SnO devices ever reported. The extracted field-effect mobility is about 0.25 ${\mathrm {cm}}^{\text {2}}/\text{V}\cdot \text{s}$ . After ruling out the influence of source/drain series resistance, the intrinsic field-effect mobility is found to be about 1 ${\mathrm {cm}}^{\text {2}}/\text{V}\cdot \text{s}$ .

Downscaling Metal—Oxide Thin-Film Transistors to Sub-50 nm in an Exquisite Film-Profile Engineering Approach

We report an exquisite, film-profile-engineering approach for producing nanometer-scale channel-length (L) ZnO thin-film transistors (TFTs). The scheme is based on a unique laminated structure in conjunction with a well-designed etching process for building a slender, suspending bridge that shadows the subsequent deposition of pivotal thin films of ZnO and gate oxide as well as simultaneously defines L of the TFTs. With the approach, we have ingeniously downscaled L of ZnO TFTs to as short as 10 nm. The experimental ZnO TFTs of L = 50 and 30 nm, respectively, exhibit excellent performance in terms of high on/off current ratio of $7.9 \times 10^{\mathrm {\mathbf {7}}}$ and $4.2 \times 10^{\mathrm {\mathbf {7}}}$ , superior subthreshold swing of 92 and 95 mV/decade, and small drain induced barrier lowering of 0.1 and 0.29 V/V. Remarkably the nanometer-scale ZnO TFTs possess excellent device uniformity. Furthermore, the precise control over the geometrical sizes for the channel length enables the fabrication of ultrashort ZnO TFTs of L as short as 10 nm with reasonable gate transfer characteristics.

Film-Profile Engineered InGaZnO Thin-Film Transistors With Self-Aligned Bottom Gates

We propose and demonstrate a method which combines film profile engineering (FPE) and a procedure of forming self-aligned bottom gates (SABGs) to fabricate InGaZnO thin-film transistors (TFTs). In the scheme, an ingenious etching procedure was implemented to form the final bottom gate self-aligned to the upper hardmask structure. The fabricated SABG devices show greatly reduced OFF-state leakage as compared with nonself-aligned ones, attributing to the reduction of gate-to-source/drain overlap areas which lowers both parasitic capacitance and gate leakage current. These merits benefit the operation of circuits consisted of TFTs implemented with FPE.

Novel InGaZnO inverters utilizing film profile engineering

In this study we cleverly employ the film profile engineering (FPE) concept to fabricate amorphous InGaZnO (a-IGZO) thin-film transistor (TFT)-based inverters with a resistor- or transistor-load. In the fabrication the profiles of major thin films in both load and drive devices can be properly tailored with designed channel dimensions and deposition conditions. Although the inverter with a resistor-load is simpler in structure and fabrication, the switching performance is found to be restricted by the passive load component. The performance can be greatly promoted as a depletion-mode transistor-load is used instead. Full-swing operation is demonstrated for the inverter with a voltage gain of 28 recorded at an operation voltage (VDD) of 5 V.

Fabrication and Characterization of Film Profile Engineered ZnO TFTs With Discrete Gates

By virtue of the film-profile engineering scheme and properly designed device structure, ZnO TFTs with discrete bottom gates and sub-micron channels were fabricated and characterized. In the fabrication, a suspended bridge constructed over the bottom gate is used to tailor the profile of subsequently deposited films. Superior electrical characteristics in terms of ultrahigh ON/OFF current ratio ( $\sim 10^{10}$ ), steep sub-threshold swing ( $66\sim 108$ mV/dec), and very low off-state leakage current are demonstrated with the fabricated devices. Effects of channel lengths on the device characteristics are also explored. Because of more effective shadowing of the depositing species with a longer suspended bridge, the deposited films become thinner at the central channel. As a result, the device shows more positive turn-on voltage and better subthreshold swing with increasing channel length.

Effects of Gate Dielectric and Process Treatments on the Electrical Characteristics of IGZO TFTs With Film Profile Engineering

In this paper, high-performance InGaZnO (IGZO) thin-film transistors were fabricated with film-profile-engineering scheme. The impacts of gate dielectric, O <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> /Ar ratio during the sputtering of the IGZO, and annealing ambient on the device performance were investigated. It is found that the turn-ON voltage of the device is closely related to the gate dielectric material. For the devices with Al <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> O <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> as the gate dielectric, decent performance in terms of high ON/OFF current ratio (>10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">8</sup> ), extremely steep subthreshold swing (62 mV/decade), and good mobility (19.8 cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> /V·s) is obtained. The influences of O <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> /Ar flow ratio are distinct for the devices with Al <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> O <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> gate oxide. Significant improvement in the stability of the devices to the environment is achieved with the anneal done in a low-pressure N <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> ambient.

Submicron organic thin-film transistors fabricated by film profile engineering method

In this work, we explore and demonstrate the feasibility of a film profile engineering (FPE) concept in fabricating pentacene-based organic thin-film transistors (OTFTs) with submicron channel length. The FPE scheme utilizes a suspended bridge built on the wafer and the specific deposition conditions to form thin films with desirable profiles. In order to form a continuous pentacene channel under the bridge, the background pressure of thermal evaporator is adjusted by pumping down the filling N2 to a specific level. The results show that, by setting the deposition pressure at 3 mtorr, functional operations of OTFTs with channel length ranging from 0.4 to 0.6 μm are obtained.

100-nm IGZO Thin-Film Transistors With Film Profile Engineering

100-nm indium-gallium-zinc-oxide (IGZO) thin-film transistors were fabricated with a one-mask process, which takes the advantage of photoresist trimming technique and the concept of film profile engineering (FPE). With I-line-based photolithography, a device with channel length of 97 nm has been successfully fabricated. The FPE device contains a conformal Al <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> O <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> gate oxide, concave IGZO channel, and discrete source/drain (S/D) Al contacts. Good device characteristics including a high-ON/OFF current ratio (>10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">7</sup> ) and good subthreshold swing (140 mV/decade) are obtained. Nonetheless, high-S/D series resistance presents a key issue that needs to be addressed for further device performance improvement.

Implementation of Film Profile Engineering in the Fabrication of ZnO Thin-Film Transistors

A novel approach, which can delicately form a desirable film profile for deposited gate oxide, channel, and source/drain contacts of oxide-based thin-film transistors (TFTs) is proposed. To demonstrate the film-profile engineering concept used in this approach, a simple one-mask process was developed for fabricating ZnO TFTs with submicrometer channel length. The fabrication takes advantage of a suspended bridge hanging across the device to tailor the desirable profile of deposited films with proper tools. The fabricated devices show high ON/OFF current ratio (>109), steep subthreshold swing (71-187 mV/decade), and high mobility (21-45 cm2/V·s). Very small variation in device characteristics among the devices with the same channel dimensions is also confirmed.