Field Programmable Logic Devices Research Articles

State Merging and Splitting Strategies for Finite State Machines Implemented in FPGA

Different strategies for the combination of merging and splitting transformation procedures for incompletely specified finite state machines implemented on field-programmable logic devices are offered. In these methods, such optimization criteria as the speed of operation, power consumption and implementation cost are considered already in the early phase of finite state machine synthesis. The methods also take into account the technological features of programmable logic devices and the state assignment method. The transformation quality ratio is calculated on the base of estimations of consumed power, critical path delay and number of utilized logic cells. The user is also able to choose the order of merging and splitting procedures and the direction of the optimization by setting weights for each criterion. The methods of the estimation of optimization criteria values are described, and the experimental results are also discussed.

Experimental research of a shared memory subsystem with limited queue length for specialized reconfigurable multiprocessor systems

Recently, reconfigurable systems based on field programmable logic devices (FPLDs) have been widely used in high-performance computing. The paper discusses issues related to the experimental research of a shared memory subsystem with a limited queue length of specialized reconfigurable multiprocessor systems using the developed mathematical modelling method. The paper presents the results of the method proposed by the authors for modelling multiprocessor systems based on open queuing networks with limited queue lengths. Based on these conditions, as well as the architectural features of the investigated processor-memory subsystem, expressions are calculated to estimate the exchange time and the resulting delays at each exchange stage. During the research, the main attention was paid to the dependence of the increase in the number of processor nodes in the processor-memory subsystem. As a result, the data obtained showed that the processor growth significantly affects the exchange time, creating a significant load on the common bus, as well as increasing delays at the stages when request transfer operation from the processor to the memory is performed. At the same time, the inadequate behaviour of experimental results and inaccuracy of their values when using the basic modelling method are explicitly tracked, which is reflected in the obtained graphs. Computational experiments were carried out to calculate the probabilistic-temporal characteristics of the "processor-memory" subsystem using the developed mathematical modelling methods. Based on the experimental results, it was determined that the delays occurring in subsystem's nodes and the time of exchange between the processor and memory modules depend on the query parameters and the processor-memory subsystem’s architectural characteristics.

Design and Performance Analysis of High Throughput and Low Power RNS-Based FIR Filter Design on FPGA

A cost-effective finite impulse response (FIR) filter is introduced in this research work through Residue Number System (RNS). The moduli set selected provides the same benefit as that of the shift and add method. The implementation Residue Number System with reduced computational complexity, as well as high-performance finite impulse response filters that employ advanced Vivado Design Suite & Artix-7 field-programmable logic (FPL) devices, are presented in this research work. For a specified 64-tap FIR filter, a classical modulo adder tree is substituted by a binary adder with enhanced accuracy pursued by a single modulo reduction stage and as a result reducing the area constraints by approximately 18%. When compared to the three-multiplier-per-tap two's complement filter, the index arithmetic complex FIR filter that is based on the Quadratic Residue Number System outperforms by approximately 75% and at the same time involving some LEs for filters with more than 8 taps. When compared to the traditional design, a 64-tap filter requires only 41% LEs.

Fast Discrete Wavelet Transformation Using FPGAs and Distributed Arithmetic

ABSTRACT The discrete wavelet transform has gained the reputation of being a very effective signal analysis tool for many practical applications. However, due to its computation-intensive nature, current implementations of the transform fall short of meeting real-time processing requirements of most applications. This paper describes a parallel implementation of the discrete wavelet transform and its inverse using high-density field programmable logic devices (FPGAs). The implementation exploits the lookup table-based architecture of Virtex FPGAs, by reformulating the wavelet computation in accordance with the distributed arithmetic algorithm. Performance results show that the distributed arithmetic formulation results in a considerable performance gain compared with the conventional arithmetic formulation of the wavelet computation. Finally, we show that the FPGA implementation outperforms alternative software implementations of the discrete wavelet transform.

Four-Step Current Commutation Strategy for a Matrix Converter Based on Enhanced-PWM MCU Peripherals

In this paper, an efficient implementation of the four-step current commutation technique for controlling bidirectional power switches in a Matrix Converter (MC) is proposed. This strategy is based on the enhanced pulse width modulation peripheral included in the C 2000 Delfino 32-bit microcontroller of Texas Instruments. By tuning the algorithmic parameters contained in this module, the four-step commutation process is carried out on the Microcontroller Unit (MCU) without overloading the full complex processor and avoiding the use of additional special hardware such as Field-Programmable Gate Arrays (FPGA) or Complex Programmable Logic Devices (CPLD) when controlling the MC. The algorithm is implemented on the TMS320F28379D MCU and operationally validated on an MC prototype, where the functionality of the proposal is demonstrated.

A synchronous serial bus for multidimensional array acoustic logging tool

In high-temperature and spatial borehole applications, a distributed structure is employed in a multidimensional array acoustic logging tool (MDALT) based on a phased array technique for electronic systems. However, new challenges, such as synchronous multichannel data acquisition, multinode real-time control and bulk data transmission in a limited interval, have emerged. To address these challenges, we developed a synchronous serial bus (SSB) in this study. SSB works in a half-duplex mode via a master–slave architecture. It also consists of a single master, several slaves, a differential clock line and a differential data line. The clock line is simplex, whereas the data line is half-duplex and synchronous to the clock line. A reliable communication between the master and the slaves with real-time adjustment of synchronisation is achieved by rationally designing the frame format and protocol of communication and by introducing a scramble code and a Hamming error-correcting code. The control logic of the master and the slaves is realized in field programmable gate array (FPGA) or complex programmable logic device (CPLD). The clock speed of SSB is 10 MHz, the effective data rate of the bulk data transmission is over 99%, and the synchronous errors amongst the slaves are less than 10 ns. Room-temperature test, high-temperature test (175 °C) and field test demonstrate that the proposed SSB is qualified for MDALT.

Multiple-tapped-delay-line hardware-linearisation technique based on wire load regulation

This article describes designing, implementation and tuning processes of multiple-tapped-delay-line (MTDL). Obtained MTDL can be implemented in various field-programmable-logic-devices (FPGA) devices and applied for time-to-digital-converters (TDC) construction. The task of tuning process is the tapped-delay-line (TDL) linearisation, and consists of two stages. The first stage depends on selecting an appropriate configurable-logic-block (CLB) for particular delay-segment realization and selecting proper connection between these blocks. The second tuning stage, that is essential from this article viewpoint, depends on inter CLBs connecting wires delay regulation realized directly by load regulation. The Load regulation depends on connecting an appropriate number of unused three-state-buffers or CLB inputs to the wire which delay is adjusted. Depending on the number of inputs connected to the wire its capacitance changes that influences its time-constant and finally changes its time-delay. The MTDL mathematical model, obtained characteristics and results of time-interval (TI) measurements are also presented. The derived TDL model provides information about how the particular wire delay should be changed and in which order the changes should be executed. This makes the designing process predictable and easy to carry out. Presented characteristics confirm the proper operation of presented linearisation technique. The proper operation of the whole measuring module is confirmed by obtained TIs histograms presentation.

A framework of embedded reconfigurable systems based on re-locatable virtual components

The use of modern field-programmable logic devices can help system designers achieve better cost-performance characteristics, in particular in the case of multi-task and multi-modal workloads. This is particularly true when the embedded systems are based on run-time and partially reconfigurable FPGA devices. Such devices permit a system to implement part of its functionality in virtual form, by storing circuits as configuration bit-streams. The use of such virtual components, however, imposes certain requirements on both the behaviour of the system as well as the components themselves. The work presented here analyses some of these requirements, and proposes a potential framework for designing embedded systems using virtual resources. Two examples of a system using virtual components are presented and the infrastructure overhead for supporting virtual components is analysed. It is found that such systems can be implemented efficiently, both in terms of hardware resources as well as timing performance.

Magnetic Flip Flops for Space Applications

The radiation environment of space presents a significant threat to the reliability of nonvolatile memory technologies. Ionizing radiation disturbs the charge stored on floating gates, and cosmic rays can permanently damage thin oxides. A new memory technology based on the magnetic tunneling junction (MTJ) appears to offer superior resistance to radiation effects and virtually unlimited write endurance. A magnetic flip flop has a number of potential applications, such as the configuration memory in field-programmable logic devices. However, using MTJs in a flip flop requires radically different circuitry for storing and retrieving data. New techniques are needed to insure that magnetic flip flops are reliable in the radiation environment of space. We propose a new radiation-tolerant magnetic flip flop that uses the inherent resistance of the MTJ to increase its immunity to single event upset and employs a robust "Pac-man" magnetic element

A miniature electrical capacitance tomograph

The paper describes a miniature electrical capacitance tomography system. This is based on a custom CMOS silicon integrated circuit comprising eight channels of signal conditioning electronics to source drive signals and measure voltages. Electrodes are deposited around a hole that is fabricated, using ultrasonic drilling, through a ceramic substrate and has an average diameter of 0.75 mm. The custom chip is interfaced to a host computer via a bespoke data acquisition system based on a microcontroller, field programmable logic device and wide shift register. This provides fast capture of up to 750 frames of data prior to uploading to the host computer. Data capture rates of about 6000 frames per second have been achieved for the eight-electrode sensor. This rate could be increased but at the expense of signal to noise. Captured data are uploaded to a PC, via a RS232 interface, for off-line imaging. Initial tests are reported for the static case involving 200 µm diameter rods that are placed in the sensor and for the dynamic case using the dose from an inhaler.

Cost-Effective Video Filtering Solution for Real-Time Vision Systems

This paper presents an efficient video filtering scheme and its implementation in a field-programmable logic device (FPLD). Since the proposed nonlinear, spatiotemporal filtering scheme is based on order statistics, its efficient implementation benefits from a bit-serial realization. The utilization of both the spatial and temporal correlation characteristics of the processed video significantly increases the computational demands on this solution, and thus, implementation becomes a significant challenge. Simulation studies reported in this paper indicate that the proposed pipelined bit-serial FPLD filtering solution can achieve speeds of up to 97.6 Mpixels/s and consumes 1700 to 2700 logic cells for the speed-optimized and area-optimized versions, respectively. Thus, the filter area represents only 6.6 to 10.5% of the Altera STRATIX EP1S25 device available on the Altera Stratix DSP evaluation board, which has been used to implement a prototype of the entire real-time vision system. As such, the proposed adaptive video filtering scheme is both practical and attractive for real-time machine vision and surveillance systems as well as conventional video and multimedia applications.

Teaching Reconfigurable Systems: Methods, Tools, Tutorials, and Projects

This paper presents an approach that has been used for teaching disciplines on reconfigurable computing and advanced digital systems, which are intended to cover such topics as architectures and capabilities of field-programmable logic devices; languages for the specification, modeling, and synthesis of digital systems; design methods; computer-aided design tools; reconfiguration techniques; and practical applications. To assist the educational process, the following units have been developed and employed in the pedagogical practice: animated tutorials, miniprojects, hardware templates, and course-oriented library of digital circuits. To stimulate the student's activity, an optional project-based evaluation technique has been applied. All the materials that are required for students are available on the university website (WebCT) and can easily be used for studying inside the university, for obtaining additional information during practical classes and for distance learning.

EFFICIENT RNS-BASED DESIGN OF PROGRAMMABLE FIR FILTERS TARGETING FPL TECHNOLOGY

FIR filters are routinely used in the implementation of modern digital signal processing systems. Their efficient implementation using commercially available VLSI technology is a subject of continuous study and development. This paper presents the residue number system (RNS) implementation of reduced-complexity and high-performance FIR filters, using modern Altera APEX20K field-programmable logic (FPL) devices. Index arithmetic over Galois fields and the Quadratic Residue Number System (QRNS), along with a selection of a small wordwidth modulus set, are the keys for attaining low complexity and high throughput in real and complex FIR filters. RNS–FPL merged FIR filters demonstrated its superiority when compared to 2C (two's complement) filters, being about 65% faster and requiring fewer logic elements for most study cases. Special attention was paid to an efficient implementation of the multi-operand modulo adders. The replacement of a classical modulo adder tree by a binary adder with extended precision followed by a single modulo reduction stage reduced area requirements by 10% for a 32-tap FIR filter. On the other hand, an index arithmetic QRNS-based complex FIR filter yielded up to 60% performance improvement over a three-multiplier-per-tap 2C filter, while requiring fewer LEs for filters having more than eight taps. Particularly, a 32-tap filter needed 24% LEs less than the classical design.

Efficient hardware architectures for computation of image moments

Geometric moments are used in numerous image analysis tasks. While several approaches have been proposed, real-time computation is still inefficient. In this paper, a mathematical formulation of the relationship of the all-pole filter output to the geometric moments is discussed. Using this formulation, architectures for implementing in hardware geometric moments of 1, 2 or 3D objects are proposed. Four implementations are programmed in field programmable logic devices (FPGA) devices with typical clock frequencies of 40 MHz. The speed of these devices is adequate for real-time applications, and they can be used to extract local as well as global geometric moments.

Guest Editors’ Introduction: Field Programmable Logic and Applications

THE impact of Field Programmable Logic on the computing community has been growing for more than a decade. Field Programmable Logic devices are no longer just a prototyping vehicle for Application-Specific Integrated Circuits (ASICs), but are increasingly found in computer systems where the user configurable logic and interconnects offer unique advantages. This special section contains seven papers reporting on a number of interesting advances in the architectures, compilation techniques, and applications of configurable computer systems, all chosen from the 13th International Conference on Field Programmable Logic and Its Applications, held on 1-3 September 2003 in Lisbon, Portugal. Two papers are selected to reflect the diversity that reconfigurable architecture can offer. The paper “The MOLEN Polymorphic Processor” by S. Vassiliadis, S. Wong, G. Gaydadjiev, K. Bertels, G. Kuzmanov, and E. Moscu Panainte presents a mixed general purpose and custom computing machine, proposing their own computing paradigm, instruction set, and compiler methodology. This paper attempts to combine both by extending a general purpose instruction set with eight special instructions to implement reconfigurable functions. This paper illustrates that the traditional barrier between the software and hardware worlds is fast diminishing. Many of the modern Field Programmable Gate Array (FPGA) architectures which include embedded processors also illustrate this new reality. The second paper, “An Asynchronous Dataflow FPGA Architecture” by J. Teifel and R. Manohar, presents an FPGA architecture able to implement highperformance asynchronous logic using the dataflow paradigm. These asynchronous circuits do not need a global clock to ensure that computation proceeds in the right sequence. Instead, all cells compute concurrently and are connected by specific communication channels which guarantee the necessary data dependencies according to a dataflow scheme. They developed a specific asynchronous FPGA device instead of utilizing conventional clocked FPGA architectures, as has been done by others in the past. Software environments and tools for reconfigurable computers can be very different from those found in conventional computers. Three papers are selected to demonstrate such differences. The first, “Operating Systems for Reconfigurable Embedded Platforms” by C. Steiger, H. Walder, and M. Platzner, addresses some issues in the design of an operating system for a reconfigurable system, focusing on the runtime environment that guarantees proper scheduling of real-time tasks. Unlike conventional software-only scheduling, this operating system requires a strong connection between the scheduling and placement of hardware modules. The second paper, “Exploiting Program Branch Probabilities in Hardware Compilation” by H. Styles and W. Luk, addresses a very interesting topic relating to the optimization of circuits implementing behaviors with branching constructs. For many years, software compilation has taken advantage of branch probabilities to optimize the average-case performance of algorithms. This paper extends the approach to compilation for reconfigurable hardware. It is demonstrated that an approach based on queuing theory can provide insights into an appropriate trade off between circuit area and circuit performance for each component in a design. As a result, the overall design has significantly improved performance under the same area constraint, compared to commonapproaches that do not consider load balancing issues. The last compilation paper by K. Shayee, J. Park, and P. Diniz considers the impact of compiler loop transformations on hardware designs implemented in reconfigurable logic. It has long been accepted that loop transformations offer a useful way to formalize and automate design space exploration. However, the impact of loop transformations on circuit performance is not always well-understood due to the simplifying architectural models often employed. This paper studies the impact of loop transformations on both area and performance measures and focuses on the particularly interesting area of loop transformations within architectures containing a limited number of memory channels. Computer systems based on Field Programmable Logic only compete favorably against conventional computer systems in specific applications. Two such applications are chosen for the last two papers. The first by C. Ebeling, C. Fisher, G. Xing, M. Shen, and H. Liu presents the design and implementation of an OFDM receiver in the RaPiD reconfigurable architecture as a case study for comparing the relative cost and performance of ASIC, programmable, FPGA, and domain-specific reconfigurable systems. The last paper, by I. Skliarova and A. Ferrari, gives a IEEE TRANSACTIONS ON COMPUTERS, VOL. 53, NO. 11, NOVEMBER 2004 1361

Adaptive video filtering framework

AbstractWe present a new 3D adaptive filtering approach capable of detecting and removing impulsive noise in image/video sequences. The proposed method takes advantage of switching median schemes and robust lower‐upper‐middle (LUM) smoothing characteristics. Simulation studies reported in this article indicate that the proposed filtering scheme achieves an excellent trade‐off between noise attenuation and detail preserving characteristics, and clearly outperforms previously introduced approaches in terms of subjective and objective image quality measures. Besides the filter analysis and the testing of its performance, an important part of this article discusses the filter implementation in Altera field programmable logic devices (FPLD). Simulation studies indicate that the proposed method can be efficiently implemented in hardware and is suitable for real‐time image/video processing applications. © 2005 Wiley Periodicals, Inc. J Imaging Syst Technol 14, 223–237, 2004; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/ima.20027

Parallel implementation of exact dilations and multi-scale skeletonization

Skeletonization has become an important pre-processing step in shape analysis and pattern recognition as it expresses the hierarchical organization of data to be analysed and simplifies the computational procedures. More recently, architectures for image processing have greatly benefitted from the use of reconfigurable devices such as field programmable gate arrays and complex programmable logic devices. We present in this work the implementation of a versatile method for Exact Dilation using reconfigurable devices. The developed method allows us to extract skeletons and other important features from an image.

Implementation of RNS-Based Distributed Arithmetic Discrete Wavelet Transform Architectures Using Field-Programmable Logic

Currently there are design barriers inhibiting the implementation of high-precision digital signal processing (DSP) objects with field programmable logic (FPL) devices. This paper explores overcoming these barriers by fusing together the popular distributed arithmetic (DA) method with the residue number system (RNS) for use in FPL-centric designs. The new design paradigm is studied in the context of a high-performance filter bank and a discrete wavelet transform (DWT). The proposed design paradigm is facilitated by a new RNS accumulator structure based on a carry save adder (CSA). The reported methodology also introduces a polyphase filter structure that results in a reduced look-up table (LUT) budget. The 2C-DA and RNS-DA are compared, in the context of a FPL implementation strategy, using a discrete wavelet transform (DWT) filter bank as a common design theme. The results show that the RNS-DA, compared to a traditional 2C-DA design, enjoys a performance advantage that increases with precision (wordlength).

RNS-based implementation of 8×8 point 2D-DCT over field-programmable devices

A new implementation of an 8×8 two-dimensional discrete cosine transform (2D-DCT) processor based on the residue number system (RNS) is presented. This architecture makes use of a fast cosine transform algorithm. It is shown that the RNS implementation of the 2D-DCT over field-programmable logic devices leads to a 129% throughput improvement over the equivalent binary system.

An introductory digital design course using a low-cost autonomous robot

This paper describes a new digital design laboratory developed for undergraduate students in this electrical and computer engineering curriculum. A top-down rapid prototyping approach with commercial computer-aided design tools and field-programmable logic devices (FPLDs) is used for laboratory projects. Students begin with traditional transistor-transistor logic-based projects containing a few gates and progress to designing a simple 16-bit computer, using very high-speed integrated circuits hardware description language (VHDL) synthesis tools and an FPLD. To help motivate students, the simple computer design is programmed to control a small autonomous robot with two servo drive motors and several sensors. The laboratory concludes with a team-based design project using the robot.