Field Programmable Logic Devices Research Articles

ISDE—an integrated systems development environment for custom-computing machines implemented in FPLDs

This paper presents a system development environment for embedded applications based on custom-computing machines implemented in field programmable logic devices (FPLDs). The concept uses the fact that FPLDs enables convenient way for implementing customised and reconfigurable digital systems. The custom-computing machines are based on a flexible instruction execution unit, which is a general-purpose microprocessor that allows addition of more complex processing elements in the form of functional units. The system development environment contains a number of tools that allow high-level description of the both processor core and functional units and produces VHDL synthesisable code, which can be processed by any VHDL compiler, and automatic generation of all basic software development tools such as customised cross-assembler and C compiler.

Field programmable spin-logic based on magnetic tunnelling elements

Spin-dependent tunnelling elements are widely studied due to their possible application in electronic devices. Here we focus on field programmable logic devices. We introduce the concepts and demonstrate experimentally the functionality of reprogrammable logic gates based on spin-dependent tunnelling elements. We further extend this demonstration to logic gates consisting of micron-sized tunnelling elements.

A Real-Time Implementation of Nonlinear Unsharp Masking with FPLDs

Real-time performance of image enhancement algorithms is required in many applications. In this paper we present a real-time image contrast enhancement scheme using non-linear unsharp masking, implemented with FPLDs (Field Programmable Logic Devices). A quadratic filter has been chosen for the nonlinear unsharp masking. The implementation performs well on real images from medical and non-medical fields. Performance figures of the nonlinear filter on mammograms show substantial improvements over software-only and other filter implementations using linear schemes, thus achieving real-time image enhancement of large images. The implementation has been tested as an application-specific co-processor to a standard PC, but can also be used as a functional unit of an application-specific image enhancement processor.

High-speed customizable fuzzy-logic processor: architecture and implementation

A generic field-programmable logic device (FPLD)-based fuzzy logic system aimed at high-speed applications that can be easily customized for practically any application is presented. It implements fuzzy logic systems that vary in terms of the numbers of inputs and outputs and their accuracy, the membership functions (MFs), fuzzy rules, and the speed at which new outputs have to be generated. This is achieved by using the sysstem's unique architecture and its parameterized description, which is based on VHDL generics. The system can be used as either a stand-alone system or as an application-specific co-processor added to standard or customized microprocessors.

Scalar-based direct algorithm mapping FPLD implementation of a Kalman filter

A methodology of the scalar-based direct algorithm mapping (SBDAM) is defined and presented. The methodology uses direct mapping of the arithmetic expressions on to a field-programmable logic device (FPLD). A Kalman filter used in multiple target tracking (MTT) applications has been implemented in FPLD via SBDAM and via the other matrix-based systolic algorithm engineering (MBSAE) approach. The comparison between SBDAM and MBSAE drawn from this example is given in terms of various performance measures such as speed of the resulting circuit, required space (resource) requirements, ease of development, and others.

Implementation of High-Performance PID Controllers Using RNS and Field-Programmable Devices

Abstract The increasing number of special applications requiring high-precision control techniques such as grinding, metrology, semiconductor manufacturing, etc. requires the development of high-performance controllers. As the Proportional-Integral-Derivative (PID) controller is used in 90-95% of control applications, it would be interesting to develop a procedure to design digital PID controllers to be used in these applications. This paper presents a PID controller design based on the Residue Number System which can operate at frequencies higher than 50MHz using medium cost Field Programmable Logic (FPL) devices.

Field-programmable logic devices with optical input–output

A field-programmable logic device (FPLD) with optical I/O is described. FPLD's with optical I/O can have their functionality specified in the field by means of downloading a control-bit stream and can be used in a wide range of applications, such as optical signal processing, optical image processing, and optical interconnects. Our device implements six state-of-the-art dynamically programmable logic arrays (PLA's) on a 2 mm x 2 mm die. The devices were fabricated through the Lucent Technologies-Advanced Research Projects Agency-Consortium for Optical and Optoelectronic Technologies in Computing (Lucent/ARPA/COOP) workshop by use of 0.5-microm complementary metal-oxide semiconductor-self-electro-optic device technology and were delivered in 1998. All devices are fully functional: The electronic data paths have been verified at 200 MHz, and optical tests are pending. The device has been programmed to implement a two-stage optical switching network with six 4 x 4 crossbar switches, which can realize more than 190 x 10(6) unique programmable input-output permutations. The same device scaled to a 2 cm x 2 cm substrate could support as many as 4000 optical I/O and 1 Tbit/s of optical I/O bandwidth and offer fully programmable digital functionality with approximately 110,000 programmable logic gates. The proposed optoelectronic FPLD is also ideally suited to realizing dense, statically reconfigurable crossbar switches. We describe an attractive application area for such devices: a rearrangeable three-stage optical switch for a wide-area-network backbone, switching 1000 traffic streams at the OC-48 data rate and supporting several terabits of traffic.

A fast variable-length decoder using plane separation

This paper has developed a fast variable-length decoder which uses a plane separation technique to reduce the processing time of the feedback path in the decoder. The developed decoder performs two shift processes and a decision process concurrently. Therefore, the processing time in the feedback path of our developed variable length decoder can be improved and determined by the longest time among the three processes, not by the sum of their processing times together. Our simulation results show that the total processing time of our developed decoder makes about 30% improvement from that of the Sun and Lei's (1991, 1992) decoder and their modified decoder when they are implemented with field programmable logic device.

A real-time encoding and decoding system for nonlinear HDTV editor

A real-time encoding and decoding system (REDS) for HDTV that can be used for nonlinear HDTV editing in studio has been developed. The intrapicture coding of motion JPEG is implemented and optimized in the REDS so that a high-quality image can be recovered for the nonlinear editing. The REDS has a parallel architecture with multiple programmable digital signal processors (DSP) and reconfigurable field programmable logic devices (FPLD). The HDTV image is spatially partitioned and concurrently processed by the multiple processors. The programmable DSPs perform the discrete cosine transform and quantization to reduce the spatial redundancy of the HDTV image, whereas the FPLDs perform the variable length coding to reduce the statistical redundancy. In addition, field-based quantization matrices are developed for HDTV images. The REDS has the programmability and the random accessibility of image frames, the two most important features for a nonlinear HDTV editing system. © 2000 John Wiley & Sons, Inc. Int J Imaging Syst Technol 11, 152–157, 2000

Rapid prototyping using field-programmable logic devices

Traditionally, undergraduates in electrical and computer engineering study the design and implementation of a simple computer and then develop their own designs. In recent years, computer design courses have for the most part taken a simulation-only approach. Rapid prototyping techniques and a new generation of large field-programmable logic devices (FPLDs) enabled an educational approach that combines modeling with hardware description languages (HDLs), extensive simulation, synthesis, and final verification on a hardware prototype. The author describes an undergraduate computer engineering curriculum using a rapid prototyping approach to simulate, synthesize, and implement digital system and computer architectures.

FLIX environment for generation of custom-configurable machines in FPLDs for embedded applications

This paper presents an environment for developing customized hardware–software solutions for intelligent embedded applications. They are based on the use of custom-configurable machines generated around a flexible instruction execution unit, called Flexible Instruction Execution Unit, or FLIX. The FLIX customization environment contains the FLIX processor core, which can be customized with a small effort to solve the software part of the solution, the standard interface, and the application specific functional units that represent hardware part of the solution. The FLIX environment allows easy modification of the FLIX instruction set, with the necessary changes of its control unit, as well as the software development support in a form of self-generating assembler. Field-Programmable Logic Devices (FPLDs) are used as the implementation technology.

Custom silicon for tomographic instrumentation

This paper addresses the issues that are appropriate when considering custom silicon for tomographic instrumentation. The whole range of mask and field programmable custom silicon options are described. These embrace full custom, mask-programmable gate array, cell-based IC and field programmable logic devices. Attention is drawn to economic considerations. It is noted that there is a shortage of previous examples of the application of custom silicon technology to tomographic instruments. Most previous reports describe accelerators for image reconstruction algorithms and, consequently, utilize digital technology. Examples of some existing custom silicon devices are briefly summarized and these involve applications to positron emission and electrical impedance tomography. Attention is drawn to the fact that different techniques may share common requirements and therefore it is conceivable that, with concerted attention, custom silicon devices may be developed that are appropriate for a broad range of tomographic applications.

A silicon-on-silicon field programmable multichip module (FPMCM) integrating FPGA and MCM technologies

Multichip module technology can dramatically increase the capability of field programmable logic devices (FPLD's) and field programmable systems (FPS). We present the special advantages that MCM's offer FPLD's and the design of our first-generation field programmable multichip module (FPMCM). Our prototype is the first silicon-on-silicon FPMCM and has a maximum capacity of 40 K gates and 256 user IO, achieving a factor of four increase in capacity over the FPLD family with which it was designed. Our FPMCM has bean demonstrated in a system that can deliver 200 MOP's of computing power for image processing applications. FPMCM's can cost-effectively deliver 4-8 times the capacity of the largest FPLD's and provide even larger reductions in the area of PCB-based field programmable systems. The upper capacity limits for FPMCM are determined mainly by the cost and defect density of the substrate technology. As CMOS processes move into the deep-submicron range, FPMCM's will even faster and denser substrates.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

A data acquisition system for flat-panel imaging arrays

An electronic data acquisition system for pixelated, two-dimensional, amorphous silicon x-ray imaging arrays has been developed. The system was designed in a modular fashion with digital control provided by field-programmable logic devices. This approach allows sections of the design to be upgraded with little impact an other aspects of the system. Good analog noise performance was obtained by matching the preamplifier design to the characteristics of the array outputs. The design of this system is presented and its performance quantified. >

Survey of field programmable logic devices

This paper discusses the rapidly developing area of field programmable logic devices (FPLD) from the perspective of a user rather than a manufacturer. It aims to introduce the reader to the families of devices that are currently available, to identify common categories having similar characteristics and to summarize the main distinguishing features of specific devices. On the basis of logic block complexity and programming technique, a distinction is made between complex PLDs and field programmable gate arrays (FPGA). The discussion is restricted to those families of devices that offer logic complexities measured in thousands of gates, have the ability to include more than 100 register elements, and include more than 100 I/O pins. The devices considered include Aglotronix CAL, Altera MAX and Flex, AMD MACH, Actel ACT, AT&T ORCA, Concurrent Logic CLi6000, Crosspoint Solutions CP20K, Intel FLEXlogic, Lattice Semiconductor pLSI, Quicklogic pASIC, Xilinx LCA and EPLD.

Fitting programmable logic

Synthesis software for user-programmable logic that relieves designers of complex design fitting, placement, and routing is examined. The program, called a device fitter, manipulates a designer's generic logic description until the best possible fit with a particular field programmable gate array (FPGA) or complex programmable logic device (PLD) is obtained. The characteristics of the newer FPGAs and PLDs, for which the software is intended, are described. >