Field Programmable Gate Array System Research Articles

RETRACTED: Simulation of heat transfer process of thermal protective clothing based on FPGA and sensor processing system

Abstract Low radiation exposure to the heat transfer of the heat flux protective clothing. Field Programmable Gate Arrays (FPGA) simulation software and the sensor are used to model the heat transfer through a particular multilayer textile structure. The transfer model is verified by comparison with experimental data. In the previous method, is Initial results with the corresponding experimental results are very consistent. The first of a series of tasks to optimize thermal performance for protective clothing in thermal comfort. It protects the skin from exposure to low-intensity aspects of thermal damage caused by heat radiation has the best performance. Exposed to heat and flame, the clothes will burn. However, these burns' nature depends mostly on the fabric, the fabric structure, garment moisture, and the heart of the finishing agent used. The proposed method improves combustion speed will not change wool than other natural fibers (e.g., cotton, linen, and silk) faster. Gas weaved or loosely woven fabric relatively intact motion of light, tight and more massive than the fabric structure to promote faster flame propagation of these materials.

RETRACTED: Animal tumor medical image analysis based on image processing techniques and embedded system

Abstract In terms of image segmentation and classification has been a lot of effort. To this end, various techniques have been employed. Image segmentation has great value, especially in the field of bio-medicine for disease diagnosis. Field Programmable Gate Arrays (FPGA) and embedded systems play a very important role in medical imaging tumors in animal studies neuroscience research. Embodiment's variety of techniques can improve the accuracy of the results of the composition. In this context, efforts to increase the diagnosis's accuracy made lists of previous studies and researchers in various targets. This study aims to propose a model for the FPGA and embedded systems to assess grayscale images' impact. Such a combination may provide better results and contribute to a more effective disease diagnosis in the shortest possible time. By introducing a more accurate and more efficient diagnosis of cancer models, the study contributed to image processing. According to this model, the present research includes other tasks: Classification and overview of a combination with other methods described. Recommendations for using segmentation techniques gradation FPGA and embedded system model. Improve diagnosis of animal tumor medical tumor for timely and effective treatment.

RETRACTED: Computer aided art design Ps course teaching based on FPGA and embedded system graphics processing

ABSTRACT Photoshop Spread through electronic media, the source of presentation to development, receipt and visual coordinators. The result of accessible media innovations has empowered visual planners to broaden these limitations of their training. In this setting, the planner is always achieving stylish success and is influenced by the modern embedded system's design and patterns in the existing method IOT (Internet of thing) based embedded system for PS (Photoshop) course teaching. In the existing method, wireless communication-based image processing is less accurate and less detection of image. So in the proposed method, art design PS (Photoshop) course teaching based FPGA (Field-programmable gate array) and embedded system graphics processing for Image Dissection Algorithm. The state of constant request, finding ways of exposure that lead to development and innovation, which are deeply respected standards for self-assessment. This exploration is based on the architect's perspective and performance observation of the wheels used in visual computerization. Contemporary planning philosophies are fundamentally examined, contradictory, and refined by the mirror action of the scientist. The refined approach to architects helps to advance the method work rehearsals, anticipating the importance of investigation and launch activities. Image Dissection Algorithm Exploration innovations exhibit some contradictions in identified approaches. Like many contemporary creators, they do not adhere to the customer base of expert planning practice, yet modern professionals influence self-produced configuration images. As FPGA (Field-programmable gate array) is confirmed by some parts of the more common planning actions, the expert finds that the architect's involvement with accidental disclosure and innovation has a critical impact on the planning cycle.

A CORDIC based real-time implementation and analysis of a respiratory central pattern generator

Central pattern generators (CPGs) are dedicated neural circuits which can generate rhythmic motor patterns even in absence of sensory input with extraordinary robustness and flexibility. In this paper, a biologically realistic model of a respiratory CPG with four neurons is implemented on a reconfigurable Field-Programmable Gate Array (FPGA) system. Considering the limitations of hardware resources, we first propose a modified respiratory CPG model with Coordinate Rotation Digital Computer (CORDIC) algorithm to save limited resources and reduce complexity. And then, all the multipliers are replaced with a method which is appropriate and effective for hardware implementation to avoid the use of the area-intensive multipliers. The implementation results show that rhythmic oscillations are successfully generated by the respiratory CPG network and the resource utilization is greatly reduced, which shows the potential for building large-scale spiking neural networks. The proposed high-performance and real-time implementation of the respiratory CPG network on the FPGA system can speed up the process to gain new insights into the respiratory network and can also be developed into applications for respiratory rhythm generation and modulation.

RETRACTED: Online intelligent course based on grid and FPGA system

Online intelligent course management is all about starting situations to boldly share information. The Grid knowledge of the goods and the ability to deliver, manage, and that they will be able to obtain the information you need about current development. FPGA (Field Programmable Gate Arrays) can cause the interface to grow faster and decline the large scale integration cycle design. A FPGA-based advanced structure has improved efficiency of another ASIC (application-specific integrated circuit) to discuss the various learning tools available online to improve the effectiveness of their learning and sharing habits to educate students with the help of social networks. Integrated field programmable based learning systems provide opportunities to create new interactive environments at a fast and affordable cost. The online intelligent course system used effective machine learning algorithm is used to improve the users or people knowledge with low cost and they spend more time on online studies to develop the skills. Based on the intelligent course method of these various architectures, grid suggestions about the limitations were observed. Further on, emphasize some of the large scale integration challenges and design issues that have been followed in order to make fruitful improvement in the intelligent online architecture system to provide the cultural aspects of online studies. Knowledge about the needed instruction is essential,so that the system can track all the technically feasible actions of the response track system. An implementation view the proposed field programmable array is used to determine the importance of online course systems from one point of view.

WITHDRAWN: Analysis of electric vehicle purchase behavior based on FPGA system and neural network

The electrical vehicle purchase behavior is one of the purchase behaviors faced by the vehicle manufacturing industry. The electric vehicle is mainly produced for non-pollution and which provides a majorly green environment and eco-friendly systems, in the previous method, based on fuzzy logic control and digital signal processing for electrical vehicle purchase behavior. And the method is uneven processing of purchase behavior and uneven behavior analysis of the electric vehicle. The proposed system is based on FPGA (Field Programmable Gate Array) and Neural Network for electrical vehicle purchase behavior. It easily interfaces with Application-Specific Integrated Circuit (ASIC) without any complexities. The neural network calculates electrical data's attribute value without any complex or any error and vehicle purchase development and key factors influencing consumers to electric vehicles. Electric vehicles are to different models and consumers' needs, which serve as a theoretical basis for the widespread use of electric vehicles and serve as a reference for consumers to choose and buy. The application-specific integrated circuit is analyzed in the vehicle manufacturing industry, and related electrical spares manufacturers should consider charging schemes to attract consumers by promoting attractive specifications rather than modification and development.

Ultra Low-Noise FPGA-Based Six-Axis Optical Force–Torque Sensor: Hardware and Software

In this article, we present the novel hardware and software architecture of a smart optical force–torque sensor. The proposed configurable, modular, and compact electronics lead to performance characteristics that cannot be reached by currently available sensors: ultra-low noise with average noise power spectral density of 15 nV/ <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$\sqrt{\text{Hz}}$</tex-math></inline-formula> over a signal bandwidth of 500 Hz, a resolution of 0.0001% full scale at a 95% confidence level, and a hardware latency of less than 100 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$\mu$</tex-math></inline-formula> s. Performance is achieved by local synchronized oversampling of the sensor's optical transducers and parallel hardware processing of the sensor data using a field-programmable gate array (FPGA). The FPGA's reconfigurability provides for easy customization and updates; for example, by increasing the FPGA system clock rate to a maximum of 160 MHz, latency can be decreased to 50 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$\mu$</tex-math></inline-formula> s, limited by the current analog-to-digital converter. Furthermore, the approach is generic and could be duplicated with other types of transducers. An inertial measurement unit and a temperature sensor are integrated into the sensor electronics for gravity, inertia, and temperature compensations. Two software development kits that allow for the use of the sensor and its integration into the robot operating system have been developed and are discussed.

Formal Analysis of Multiple-Cell Upset Failure Based on Common Cause Failure Theory

As an important component of space electronic systems, static random-access memory based field programmable gate arrays (FPGAs) are inevitably affected by single-event upsets, including single-cell upset (SCU) and multiple-cell upset (MCU), caused by space radiation. In particular, as the technology scales down, the probability of MCU increases significantly; however, the analysis of MCU remains an open challenge. Based on the common cause failure theory and continuous-time Markov chain, this article proposes a new hybrid model to quantify the coexistence effect of MCU and SCU on mitigation design modes with different combinations of strategies, such as triple modular redundancy, partition, and scrubbing. Synchronization and interleaving modeling technologies are used to construct the concurrent behavior of an FPGA system under different mitigation strategies and MCU problems. In addition, we introduce a partition factor to quantitatively explain the phenomena and laws of MCUs acting on adjacent partitions. The proposed method is demonstrated using TMR with scrubbing and partition strategies, which verify that the existence of MCU reduces the system reliability and availability, and the scrubbing and partition strategy are effective against MCU issues. More importantly, the limitations of mitigation strategies in different occurrence probabilities of MCU can be found by the proposed method. In summary, the analysis and discussion presented in this article can provide useful insights for relevant designers to select and optimize different design patterns of a system operating in a dynamic and complex radiation environment.

Scrubbing-Aware Placement for Reliable FPGA Systems

Field Programmable Gate Arrays (FPGAs) provide complex embedded blocks to ease the development of high-performance computing systems for diverse area applications, including among others space, avionics and health. Although the rich set of features is ever expanding, there is one significant shortcoming of the SRAM-based FPGAs which concerns system designers for applications demanding high reliability: their vulnerability to Single Event Upsets (SEUs) which can cause system malfunction. In this work, we propose a placement approach to improve system reliability by reducing the execution time of configuration memory scrubbing, which can be used in conjunction with other reliability mechanisms proposed in the literature. The proposed placement approach is based on i) an automated floorplanning process to shape and locate the design region(s) and ii) a modified version of the Simulated Annealing placement algorithm aiming to reduce the scrubbing time. First, we performed a set of experiments with three QUIP benchmarks to demonstrate the efficiency of the proposed approach at different device utilization levels. Moreover, we illustrated its effectiveness for three different fault tolerance schemes, where scrubbing plays a different role in each one: i) a TMR microcontroller combined with scrubbing, ii) a soft processor protected by a low-cost mitigation scheme including scrubbing and checkpointing, iii) a JPEG encoder protected by a prioritized scrubbing scheduling scheme based on module criticality levels. The experimental results showed that the proposed approach improves system reliability in all the above schemes by reducing critical timing parameters, such as mean-time-to-detect and mean-time-to-repair. This reduction leads to a modest or high reliability improvement depending on the role of scrubbing in the adopted fault tolerance (FT) scheme.

Pin Assignment Optimization for Multi-2.5D FPGA-Based Systems With Time-Multiplexed I/Os

As 2.5-D field-programmable gate arrays (FPGAs) have larger logic capacity and higher pin counts compared to conventional FPGAs, they are already deployed in some multi-FPGA systems. 2.5-D FPGA consists of multiple dies connected through an interposer. Since the interposer provides only a fraction of the amount of interconnect resources with an increased delay compared to that within individual dies, it is important to reduce the number of signal crossings between dies both for routability and timing consideration when a circuit is mapped to a 2.5-D FPGA. In a multi-2.5D FPGA system with time-multiplexed hardwired inter-FPGA connections, there can be tens of thousands of inter-FPGA signals incident with each FPGA and their pin assignment can greatly affect the amount of die-crossing signals within the FPGAs. In this article, we formulate the pin assignment problem for such systems with the objective of minimizing signal crossings between dies within the individual FPGAs. Taking into consideration of the multi-die structure of 2.5-D FPGA, we propose two different iterative refinement approaches to the problem, one based on integer linear programming (ILP) and the other algorithm C-2MCF based on clustering optimization and minimum cost flow optimization. Compared to a greedy pin assignment heuristic for minimization of signal crossings between dies, C-2MCF produced 27.1% less crossings on average. While the ILP-based algorithm has up to 1% quality advantage over C-2MCF for moderate-sized instances, C-2MCF is orders of magnitude faster and can comfortably handle very large problem instances. In addition, the proposed minimum cost flow techniques within C-2MCF can also be used in conjunction with any other possible pin assignment method to enhance the final result.

A real-time FPGA accelerated stream processing for hyperspectral image classification

Realizing real-time classification of hyperspectral imagery has attracted researchers across various scientific and engineering disciplines. Several time-critical applications of high-resolution hyperspectral imaging require analysis of hyperspectral imagery with minimal turnaround time. In this regard, field-programmable gate arrays (FPGAs) provide cost-effective performance over the other high-performance reconfigurable computing systems. Developing such efficient systems poses several technical challenges such as designing and validating the FPGA architecture. A rapid prototyping approach offers several benefits in designing and developing FPGA architectures. This paper proposes a rapid prototyping method for the design and implementation of a multi-class support vector machine (MSVM) algorithm for real-time hyperspectral imagery classification using a low-cost FPGA system. We have evaluated design performance in terms of overall accuracy, resource utilization as well as timing requirements using four different datasets containing airborne, drone, and ground-based hyperspectral imagery. Experimental results show that the proposed FPGA design performs classification under strict real-time constraints.

Ground Control Point Automatic Extraction for Spaceborne Georeferencing Based on FPGA

Feature points that are obtained from the combined speeded-up robust feature (SURF) detector and binary robust independent elementary features (BRIEF) descriptor have a highly robust performance. These points are previously considered the ground control points (GCPs) for building a connection between the image coordinates and the corresponding geodetic coordinates. This article proposes a novel architecture to automatically and intelligently extract GCPs based on field programmable gate arrays (FPGAs). The parallelization SURF detector, BRIEF descriptor, and BRIEF matching are implemented in a single Xilinx XC7VX980T FPGA system. Word length reduction, memory-efficient parallel architecture, shift and subtraction strategies, a sliding window for separable convolution, and an optimized multispacer-scale are used to optimize the SURF detector. Improved parallel adder trees are used to accelerate the BRIEF matching. The proposed system achieves 380 frame per second (fps) with a 100 MHz clock frequency, which satisfies the real-time and low-power requirements of embedded devices. The results of the experiment demonstrate that the proposed architecture, when mapped onto a Xilinx Virtex-7 XC7VX980T FPGA device, can select the robust feature points.

A New Real-Time Lucky Imaging Algorithm and its Implementation Techniques

Lucky imaging is a high-angular resolution astronomical image reconstruction technique that can effectively reduce the impact of atmospheric turbulence on image quality and improve the imaging resolution of ground-based telescopes. Its key steps include image selection, registration and superposition. However, the lucky imaging algorithms based on a central processing unit (CPU) encounter difficulty accomplishing real-time processing; thus, they are post-processing methods and cannot meet the needs of on-site observers. Taking advantage of the parallelism and flexibility of the field programmable gate array (FPGA), this paper presents a new real-time lucky imaging algorithm that features real-time processing and dynamic updating and displaying. The algorithm consists of a dynamic sorting-free image selection algorithm, an improved registration and storage method, a parallel superposition algorithm, a parallel preprocessing method for noise suppression and cosmic ray removal, and a dynamic multithreshold display scheme. The simulation results show that the algorithm is feasible, effective and efficient. Compared with other lucky imaging algorithms based on FPGAs, this algorithm shows great advantages in clock consumption and on-chip resource consumption. Furthermore, it can be implemented on a small or medium-size development board of an FPGA. Moreover, the implemented FPGA system can perform real-time and dynamic lucky imaging for more than 10,000 frames of short-exposure images with an original format of 512 × 512 pixels continuously. The experimental results not only show the validity of the proposed algorithm but also demonstrate the feasibility of the proposed implementation techniques for the FPGA-based algorithm.

A new healthcare diagnosis system using an IoT-based fuzzy classifier with FPGA

In this study, an Internet of Things (IoT)-based analysis system is proposed, which can be used to design a consumer electronic device. This IoT-based analysis system will alert the user when any of the parameters related to his/her health is above or below the normal range. The data collected using this system are uploaded to the cloud using a mobile application and then transferred to the field-programmable gate array (FPGA) analysis system. The raw data are computed and processed by the FPGA system, and pathological conditions are displayed on the patient’s wearable IoT device. The novelty of this work lies in the development of a fuzzy classifier, which indicates the pathological conditions of diseases with a higher accuracy. The FPGA implementation of the fuzzy classifier results in a lower execution time in comparison with that of previous models, such as K-nearest neighbour, decision tree, support vector machine, and naive Bayes.

Review: Recent Directions in ECG-FPGA Researches

The last few years witnessed an increased interest in utilizing field programmable gate array (FPGA) for a variety of applications. This utilizing derived mostly by the advances in the FPGA flexible resource configuration, increased speed, relatively low cost and low energy consumption. The introduction of FPGA in medicine and health care field aim generally to replace costly and usually bigger medical monitoring and diagnostic equipment with much smaller and possibly portable systems based on FPGA that make use of the design flexibility of FPGA. Many recent researches focus on FPGA systems to deal with the well-known yet very important electrocardiogram (ECG) signal aspects to provide acceleration and improvement in the performance as well as finding and proposing new ideas for such implementations. The recent directions in ECG-FPGA are introduced in this paper.

Wireless Real-Time Transistor-Based Skin Temperature Data Acquisition System

Environmental physiology studies rely on the accurate measurement of skin and internal temperatures. Many traditional skin temperature systems utilize thermistor or thermocouple measurements. However, utilizing a transistor-based sensor allows for a more linear data set, which could provide more stability, thus allowing for a more robust and accurate measurement over a range of environmental conditions. Field Programmable Gate Arrays (FPGA) are relatively low cost and low power consuming programmable hardware devices that allows for a signal to be processed and viewed in real time. Combining the processing power of the FPGA and the heightened accuracy of transistor-based analog temperature sensors, a modernized data acquisition (DAQ) system could provide linearized real time data. PURPOSE: To design a wireless patch-type transistor-based skin temperature DAQ system that will provide a more accurate and linear set of data for measurement in hot/humid/cold/altitude environments, and will be sufficiently robust for outdoor field studies. METHODS: We designed and built a prototype wireless transistor-based skin temperature DAQ that implements a precision analog temperature sensor to acquire skin temperature and FPGA technology for signal processing. The tested accuracy for the precision analog temperature sensor is ±0.05-0.1°C in a temperature range of 20°C to 42°C. By utilizing FPGA technology, the system will process, pack, and wirelessly send data to a computer for real time monitoring. RESULTS: In preliminary testing, the FPGA system showed an overall lower power consumption in addition to less variability in Voltage (V), the signal upon which temperature measurements depend. Over a 5°C temperature change it was seen that the FPGA system had a variance of 3.7*10^(-11) V, while a thermistor based temperature system had a variance of 1.3*10^(-3) V. In most settings, this will result in a substantially lower power consumption using our new system. CONCLUSION: Our data suggest that our new FPGA approach is superior to traditional skin temperature measurements in its ability to rapidly attain and maintain accurate temperature readings. Next steps include field testing the device over a wide range of temperature, wind and humidity conditions. Funded by USAMRMC; author views not official US Army or DOD policy.

Phase-locking particle image velocimetry measurement of unsteady flow behaviors: Online dynamic mode decomposition using field-programmable gate array

A novel online dynamic mode decomposition (DMD) approach using a field-programmable gate array (FPGA), which takes full advantage of the DMD to extract multiple unsteady events and the FPGA system for signal sampling and fast computation, was developed for phase-locking particle image velocimetry (PIV) measurements of unsteady flow behaviors. The turbulent separated and reattaching flow around a finite blunt plate with a length-to-height-ratio L/D = 6.0 was examined to demonstrate this novel approach. The wall-pressure field and the velocity field were measured using arrayed microphones and the conventional planar PIV setup, respectively. Offline DMD analysis of the wall-pressure fluctuation field was first used to identify the dominant modes corresponding to the energetically unsteady events. For each mode, the eigenmode and its mode coefficient reflected the spatial footprint pattern and temporal strength of the unsteady event, respectively. Next, trained machine learning of the mode coefficient was used to establish a phase prediction strategy. Finally, in the online analysis, the relevant eigenmode was cast into the FPGA device to serve as the reference mode for reconstruction with the sampled wall-pressure data, determining the phase signal to fire the PIV setup. High-resolution spatiotemporal evolutions of the dominant flow structures (i.e., the flapping separation bubble, the impinging leading-edge vortex, and the trailing-edge vortex street) were separately assembled. Further measurements demonstrated a clear panoramic view of the synchronous behavior of the enlarging separation bubble and the impinging leading-edge vortex. The proposed online FPGA-DMD approach can serve as a sophisticated strategy for phase-locking PIV measurements of unsteady flow behaviors.

Real-Time Underwater Image Recognition with FPGA Embedded System for Convolutional Neural Network.

The underwater environment is still unknown for humans, so the high definition camera is an important tool for data acquisition at short distances underwater. Due to insufficient power, the image data collected by underwater submersible devices cannot be analyzed in real time. Based on the characteristics of Field-Programmable Gate Array (FPGA), low power consumption, strong computing capability, and high flexibility, we design an embedded FPGA image recognition system on Convolutional Neural Network (CNN). By using two technologies of FPGA, parallelism and pipeline, the parallelization of multi-depth convolution operations is realized. In the experimental phase, we collect and segment the images from underwater video recorded by the submersible. Next, we join the tags with the images to build the training set. The test results show that the proposed FPGA system achieves the same accuracy as the workstation, and we get a frame rate at 25 FPS with the resolution of 1920 × 1080. This meets our needs for underwater identification tasks.

FPGA Platform applied for Facial Expression Recognition System using Convolutional Neural Networks

Emotion being a subjective thing, leveraging knowledge and science behind labeled data and extracting the components that constitute it. With the development of deep learning in computer vision, emotion recognition has become a widely-tackled research problem. In this work, we propose a Field Programmable Gate Array (FPGA) architecture applied for this task using independent method called convolutional neural network (CNN). The emotion recognition block receives the detected faces from a video stream by using VITA-2000 camera module and process the image data with the trained CNN model. The architecture is implemented on a Zynq-7000 All Programmable SoC Video and Imaging Kit. Once we have trained a network, weights from the Tensorflow model will be convert as C-arrays, to be used in Vivado HLS. After having the weights as C arrays, they can be implemented to FPGA system. We can also test the functionality of the CNN entirely, by compiling the design with C++ compiler. This method was trained on the posed-emotion dataset (FER2013). The results show that with more fine-tuning and depth, the CNN model can outperform the state-of-the-art methods for emotion recognition. We also propose some exciting ideas for expanding the concept of representational landmark features and sliding windows to improve its performance.

FPGA Dynamic and Partial Reconfiguration

Dynamic and partial reconfiguration are key differentiating capabilities of field programmable gate arrays (FPGAs). While they have been studied extensively in academic literature, they find limited use in deployed systems. We review FPGA reconfiguration, looking at architectures built for the purpose, and the properties of modern commercial architectures. We then investigate design flows and identify the key challenges in making reconfigurable FPGA systems easier to design. Finally, we look at applications where reconfiguration has found use, as well as proposing new areas where this capability places FPGAs in a unique position for adoption.