Abstract
Feature points that are obtained from the combined speeded-up robust feature (SURF) detector and binary robust independent elementary features (BRIEF) descriptor have a highly robust performance. These points are previously considered the ground control points (GCPs) for building a connection between the image coordinates and the corresponding geodetic coordinates. This article proposes a novel architecture to automatically and intelligently extract GCPs based on field programmable gate arrays (FPGAs). The parallelization SURF detector, BRIEF descriptor, and BRIEF matching are implemented in a single Xilinx XC7VX980T FPGA system. Word length reduction, memory-efficient parallel architecture, shift and subtraction strategies, a sliding window for separable convolution, and an optimized multispacer-scale are used to optimize the SURF detector. Improved parallel adder trees are used to accelerate the BRIEF matching. The proposed system achieves 380 frame per second (fps) with a 100 MHz clock frequency, which satisfies the real-time and low-power requirements of embedded devices. The results of the experiment demonstrate that the proposed architecture, when mapped onto a Xilinx Virtex-7 XC7VX980T FPGA device, can select the robust feature points.
Highlights
G EOREFERENCING is an important technique of remote sensing (RS) image for an extensive variety of tasks, and estimation of the mathematical geometric calibration function of RS image based on the ground control points (GCPs) is necessary
The results indicated that the uniform distribution of the matching points and the matching rate are affected by the number of matching points and the textures of the object
memory-efficient parallel architecture (MEPA) method is used to compute the output of the FIFO in parallel
Summary
G EOREFERENCING is an important technique of remote sensing (RS) image for an extensive variety of tasks, and estimation of the mathematical geometric calibration function of RS image based on the ground control points (GCPs) is necessary. Krajník et al [42] presented a complete hardware and software solution of an FPGA-based computer vision embedded module that can carry out the SURF image feature extraction algorithm. Yao et al [43] proposed an architecture of optimized SIFT feature detection for an FPGA implementation of image matching. In [50] and [72], a modified SURF detector and BRIEF descriptor matching algorithm based on FPGA were presented. To accelerate the SURF algorithm, an improved FAST feature point combined with the SURF descriptor matching algorithm was proposed in [51], which realized the real-time matching of target images. This article proposes a hardware architecture to automatically extract GCPs for the RS image that is georeferenced based on the FPGA, which significantly reduces the computational requirement.
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