Field Programmable Gate Arrays Routing Research Articles

New High-Rate Timestamp Management with Real-Time Configurable Virtual Delay and Dead Time for FPGA-Based Time-to-Digital Converters

Modern applications require the ability to measure time events with high resolution, a full-scale range, and multiple input channels. Time-to-Digital Converters (TDCs) are a popular option to convert time intervals into timestamps. To reduce the time-to-market and Non-Recurring Engineering (NRE) costs, a Field-Programmable Gate Array (FPGA) implementation has been chosen. The high number of requested bits and channels, however, gives rise to routing congestion issues when routed in a parallel manner. In this paper, we will propose and analyze a novel solution, the Belt-Bus (BB), which involves a parallel-to-serial conversion of the timestamp stream coming from the TDC while maintaining chronological order and a sufficient high rate, and flagging the presence of timestamp overflow. Moreover, two new useful features are added. The first is a “Virtual Delay” to compensate for offsets due to cable length and FPGA routing path mismatch. The second is a “Virtual Dead-Time” to filter out unforeseen events. Finally, the BB was tested on a Xilinx 28 nm 7-Series Kintex-7 325T FPGA, achieving an overall data rate of 199.9 Msps with very limited resource usage (i.e., lower than a total of 4.5%), consuming only 480 mW in a 16-channel implementation.

An Efficient FPGA Architecture with Turn-Restricted Switch Boxes

Abstract. Field-Programmable Gate Arrays (FPGAs) employ a large number of SRAM cells to provide a flexible routing architecture which have a significant impact on the FPGA’s area and power consumption. This flexible routing allows for a rather easy realization of the desired functionality, but our evaluations show that the full routing flexibility is not required in many occasions. In this work, we focus on what is actually needed and introduce a new switch-box realization what we call Turn-Restricted Switch-Boxes which supports only a subset of possible turns. The proposed method increases the utilization rate of FPGA switch-boxes by eliminating the unemployed resources. Experimental evaluations confirm that the area and average power consumption can be reduced by 12.8% and 14.1%, on average, respectively and the FPGA routing susceptibility to SEU and MBU can be improved by 18.2%, on average, by imposing negligible performance. 1

A Two-Stage Method for Routing in Field-Programmable Gate Arrays with Time-Division Multiplexing

Emerging applications widely use field-programmable gate array (FPGA) prototypes as a tool to verify modern very-large-scale integration (VLSI) circuits, imposing many problems, including routing failure caused by the limited number of connections among blocks of FPGAs therein. Such a shortage of connections can be alleviated through time-division multiplexing (TDM), by which multiple signals sharing an identical routing channel can be transmitted. In this context, the routing quality dominantly decides the performance of such systems, proposing the requirement of minimizing the signal delay between FPGA pairs. This paper proposes algorithms for the routing problem in a multi-FPGA system with TDM support, aiming to minimize the maximum TDM ratio. The algorithm consists of two major stages: (1) A method is proposed to set the weight of an edge according to how many times it is shared by the routing requirements and consequently to compute a set of approximate minimum Steiner trees. (2) A ratio assignment method based on the edge-demand framework is devised for assigning ratios to the edges respecting the TDM ratio constraints. Experiments were conducted against the public benchmarks to evaluate our proposed approach as compared with all published works, and the results manifest that our method achieves a better TDM ratio in comparison.

Research on Hex Programmable Interconnect Points Test in Island-Style FPGA

With the decreasing size of manufacturing process, the scale of island-style field programmable gate array (FPGA) becomes larger, which leads to the increasing complexity of FPGA routing resources, especially hex programmable interconnect points (PIPs). Hex PIPs which span six tiles of the island-style FPGA have complex interconnect rules. Accordingly, research on complete hex PIPs test is rarely involved in the study of routing resources test. Therefore, this paper analyzes the hex PIPs architecture of the island-style FPGA, summarizes the interconnect rules of the hex PIPs mathematically in a two-dimensional coordinate system, and presents two proper test algorithms at the same time. The hex PIPs are divided into three directions, that is, horizontal, vertical, and oblique. According to the proposed coordinate equations, a cycle test structure in the horizontal and vertical directions and a test structure with partial-cascade patterns in the oblique direction are designed respectively. It is concluded that the proposed methods can achieve 100% fault coverage for the hex PIPs test in all directions, and the configuration number for hex lines test with the same methods is significantly decreased than previous researches.

Accelerating FPGA Routing Through Algorithmic Enhancements and Connection-aware Parallelization

Routing is a crucial step in Field Programmable Gate Array (FPGA) physical design, as it determines the routes of signals in the circuit, which impacts the design implementation quality significantly. It can be very time-consuming to successfully route all the signals of large circuits that utilize many FPGA resources. Attempts have been made to shorten the routing runtime for efficient design exploration while expecting high-quality implementations. In this work, we elaborate on the connection-based routing strategy and algorithmic enhancements to improve the serial FPGA routing. We also explore a recursive partitioning-based parallelization technique to further accelerate the routing process. To exploit more parallelism by a finer granularity in both spatial partitioning and routing, a connection-aware routing bounding box model is proposed for the source-sink connections of the nets. It is built upon the location information of each connection’s source, sink, and the geometric center of the net that the connection belongs to, different from the existing net-based routing bounding box that covers all the pins of the entire net. We present that the proposed connection-aware routing bounding box is more beneficial for parallel routing than the existing net-based routing bounding box. The quality and runtime of the serial and multi-threaded routers are compared to the router in VPR 7.0.7. The large heterogeneous Titan23 designs that are targeted to a detailed representation of the Stratix IV FPGA are used for benchmarking. With eight threads, the parallel router using the connection-aware routing bounding box model reaches a speedup of 6.1× over the serial router in VPR 7.0.7, which is 1.24× faster than the one using the existing net-based routing bounding box model, while reducing the total wire-length by 10% and the critical path delay by 7%.

Optimizing FPGA Logic Circuitry for Variable Voltage Supplies

Unlike central processing units (CPUs), field-programmable gate arrays (FPGAs) have conventionally been powered with a fixed supply voltage ( $V_{\text {dd}}$ ). However, recent efforts have shown that adopting dynamic voltage scaling reduces FPGA power consumption significantly. In this article, we analyze the delay sensitivity of different FPGA circuit elements to supply voltage changes and determine that conventional lookup table (LUT) designs greatly impact variable ${V_{\text {dd}}}$ operation. To build FPGAs with lower delay sensitivity to ${V_{\text {dd}}}$ , we propose several new LUT designs, including gate boosting the LUT, decoding the slowest two inputs of the LUT, and using separate voltage islands for the FPGA LUTs and routing. Our fastest proposed design (decode-driver island) reduces the area-delay product of the FPGA logic plus routing tile compared to a conventional design by 12% and 52% at ${V_{\text {dd}}}$ values of 0.8 V (the nominal voltage) and 0.6 V, respectively. Since our proposed FPGA tile designs are faster and have lower delay sensitivity to voltage, they offer better ${\text {Energy-Delay} {{^{\mathrm{ 2}}}}}$ product ( ${\text {ED} {{^{\mathrm{ 2}}}}}$ ) than that of the baseline at nominal ${V_{\text {dd}}}$ and below. Our decode-driver-island FPGA achieves a 26% ${\text {ED} {{^{\mathrm{ 2}}}}}$ reduction over the conventional design at the most efficient ${\text {ED} {{^{\mathrm{ 2}}}}}$ operating point.

Designing of input/output port based on FPGA with handshaking capability

Input/output (I/O) port is a group of interfaces that has diverse functional structures of a data processing system use to interconnect with each other. I/O port with handshaking capability is one of the powerful configurations to enable digital communication. The main intention of this project is to design prototype of an input/output port with handshaking capability using Field Programmable Gate Array (FPGA). The main reason of using the FPGA technology is it has unlimited number reprogrammed, cuts developing cost and development time. Xilinx Foundation 2.1i Series software in VHDL description was used as a development tool in this project. The VHDL codes were assimilated into a design and development atmosphere to accomplish many subtasks such as FPGA synthesis, optimization, placement, and routing. The successful design was translated, mapped, routed, and placed onto FPGA Demo Board. XC4010XLPC84 Xilinx FPGA from XC4000XL family was used as a target board. In prototype design, the FPGA pins were connected to a parallel printer port by using a coupled 25-pin DB connector, with a 36-pin Centronics connector cable. The output signals were observed and analyzed by using a logic analyzer.

Exploring GPU-Accelerated Routing for FPGAs

Field Programmable Gate Arrays (FPGAs) are reconfigurable architectures able to provide a good balance between energy efficiency and flexibility with respect to CPUs and ASICs. The main drawback in using FPGAs, however, is their timing-consuming routing process, significantly hindering the designer productivity. An emerging solution to this problem is to accelerate the routing by parallelization. Existing attempts of parallelizing the FPGA routing either do not fully exploit the parallelism or suffer from an excessive quality loss. Massive parallelism using GPUs has the potential to solve this issue but faces non-trivial challenges. To cope with these challenges, this paper explores GPU-accelerated routing approach for FPGAs. We leverage the idea of problem size reduction by limiting the single-net routing in a small subgraph rather than in an entire graph, further enabling the GPU-friendly shortest path algorithm to be used in FPGA routing. We maintain the convergence after problem size reduction by using the dynamic expansion of the routing resource subgraph, where the routing region of subgraph will be progressively expanded to find a feasible solution to each net. In addition, we are based on a GPU platform to explore the fine-grained single-net parallel routing in three ways and propose a hybrid approach to combine the static and dynamic parallelization for better speedup in FPGA routing. To explore the coarse-grained multi-net parallelization, We propose a dynamic programming-based partitioning algorithm to parallelize the routing of multiple nets while generating the equivalent routing results as the original single-net routing. Experimental results show that our proposed approach can provide an average of about 21.53× speedup on a single GPU with a tolerable loss in the routing quality and maintain a scalable speedup on large-scale routing resource graphs. To our knowledge, this is the first work to demonstrate the effectiveness of GPU-accelerated routing for FPGAs.

On the Susceptibility of SRAM-Based FPGA Routing Network to Delay Changes Induced by Ionizing Radiation

This paper presents the results of investigations on the susceptibility of routing network in SRAM-based field-programmable gate arrays (FPGAs) exposed to ionizing neutron radiation creating single-event upset (SEU). A method to configure test circuits mostly with routing resources and few logic resources is presented. Full control over routing resources enables the use of different interconnection types in order to create routing-based oscillators. A method is proposed to route through the 2-D array of switch matrices inside the interconnection network and to automatically identify the involved programmable interconnection points associated with a node. An experimental setup employed to measure delay changes (DCs) induced by single-event upset to the FPGA routing resources, while it is exposed to ionizing neutron radiation, is described. The proposed setup requires no external equipment instruments for DC measurement. The experimental results show that our setup is able to measure induced DCs as low as 5 ps on higher frequency oscillators. Statistical data such as cross sections and mean time to DC are extracted from the results.

Estimating and Mitigating Aging Effects in Routing Network of FPGAs

In this paper, we present a comprehensive analysis of the impact of aging on the interconnection network of field-programmable gate arrays (FPGAs) and propose novel approaches to mitigate the aging effects on the routing network. We first show the insignificant impact of aging on data integrity of FPGAs, i.e., static noise margin and soft error rate of the configuration cells, as well as we show the negligible impact of the mentioned degradations on the FPGA performance. As such, we focus on the performance degradation of datapath transistors. In this regard, we propose a routing accompanied by a placement algorithm that prevents constant stress on transistors by evenly distributing the stress through the interconnection resources. By observing the impact of the signal probability on the aging of routing buffers, we enhance the synthesis flow as well as augment the proposed routing algorithm to converge the signal probabilities toward aging-friendly values. Experimental results over a set of industrial benchmarks and commerciallike FPGA architecture indicate the effectiveness of the proposed method with 64.3% reduction of stress duration in multiplexers and up to 45.2% improvement of the degradation of buffers. Altogether, the proposed method reduces the timing guardband by from 14.1% to 31.7%, depending on the FPGA routing architecture.

A Runtime Optimization Approach for FPGA Routing

In this paper, we present a new field-programmable gate array (FPGA) routing approach on the basis of the PathFinder routing algorithm. During each routing iteration, our approach applies a novel timing-based rerouting strategy to only reroute the illegal paths. At a lower level, each maze expansion is started from the relatively close part of current routing tree to search for the target sink on the routing resource graph. Experimental results demonstrate that on average the proposed approach reduces the routing runtime by 68.5% compared with the timing-driven router in versatile place and route FPGA placement and routing framework, with reduction of 2.5% and 1.4% in critical path delay and wirelength, respectively.

Interconnect Solutions for Virtualized Field-Programmable Gate Arrays

Contemporary datacenters are enhancing their compute capacity, power efficiency, and processing latency by integrating field-programmable gate arrays (FPGA). One would like to virtualize FPGAs to share them between multiple users and to be able to allocate incoming tasks to FPGAs without interrupting their operation. To virtualize FPGAs, their complexities, such as board-specific system-level integration and tricky I/O timing closure problems should be abstracted away from users. To this end FPGA designers have proposed the shell concept which abstracts away the board-specific details from the user and provides an easy-to-use interface to the user application. In this paper, we create several shells using a wide variety of interconnect solutions and rigorously evaluate them in terms of accelerator frequency, usable bandwidth, area-efficiency, latency, wire demand, and FPGA routing congestion. We show that virtualization of four accelerators per chip with traditional bus-based FPGA interconnect costs an average frequency drop of 24%, increases the wire demand of the shell to 2.78X, and creates significant routing congestion. We also show that while FPGA-optimized soft network on chip interconnect solutions can mitigate the reduction in accelerator frequency, they exacerbate the wire demand and routing congestion problems and offer a lower usable bandwidth. Finally, we demonstrate that hard networks on chip are a superior interconnect solution for virtualized FPGAs in all of the aforementioned evaluation criteria making them well-suited to datacenter-optimized FPGAs.

Effective Drive Current for Pass-Gate Transistors

A two-point expression of effective drive current ( $I_{\rm eff\_{}PG})$ for pass-gate (PG) transistors is proposed for the first time. We demonstrate that the proposed expression of $I_{\rm eff\_{}PG}$ estimates the PG latency with a reasonable accuracy (relative error $I_{\rm eff\_{}PG}$ provides a simple yet efficient approach for technology evaluation and projection for PG heavy applications such as field-programmable gate array routing. We also show that the previously proposed static CMOS effective drive current ( $I_{\rm eff\_{}inv})$ is not a valid figure of merit when applied to PG transistors, because PG transistors operate in a different regime from the transistors in CMOS inverters. The scaling trend of $I_{\rm eff\_{}PG}$ is discussed, which illustrates the $I_{\rm eff\_{}PG}$ does not improve from device scaling as much as CMOS saturation current ( $I_{{\mathrm{dsat}}})$ and effective drive current ( $I_{\rm eff\_{}inv})$ do.

Multiple Dice Working as One: CAD Flows and Routing Architectures for Silicon Interposer FPGAs

Large field-programmable gate array (FPGA) systems with multiple dice connected by a silicon interposer are now commercially available. However, many questions remain concerning their key architecture parameters and efficiency, as the signal count between dice is reduced and the delay between the dice is increased compared with a monolithic FPGA. We modify the versatile place and route (VPR) to target interposer-based FPGAs and investigate placement and routing changes and incorporating partitioning into the flow to improve results. Our best computer-aided design (CAD) flow reduces the routing demand for interposer FPGAs with realistic connectivity between dice by 47% and improves the circuit speed by 13% on average. Architecture modifications to add routing flexibility when crossing the interposer are very beneficial and improve routability by a further 11%. With these CAD and architecture enhancements, we find that if an interposer supplies (between dice) 20% of the routing capacity that the normal (within-die) FPGA routing channels supply, there is only a modest impact on circuit routability. Smaller interposer-routing capacities do impact routability; however, minimum channel width increases by 70% when an interposer supplies only 10% of the within-die routing. The interposer also impacts delay, increasing circuit delay by 11% on average for a 1-ns interposer signal delay and a two-die system.

Fast and Memory-Efficient Routing Algorithms for Field Programmable Gate Arrays With Sparse Intracluster Routing Crossbars

Field programmable gate array (FPGA) routing is one of the most time consuming steps in a typical computer-aided design flow. The problem itself is similar to the NP-complete problem of computing a set of disjoint paths in a graph. The routing resource graph (RRG) that represents an FPGA routing network is necessarily large, and becomes even larger when modeling modern FPGAs that integrate sparse intracluster routing crossbars. This paper introduces two scalable heuristics that reduce the runtime and memory footprint of FPGA routing: 1) selective RRG expansion (SERRGE), which employs an application-specific memory manager that stores the RRG in a compressed form, and dynamically decompresses it as the router proceeds and 2) partial prerouting (PPR) locally routes all nets within each logic cluster, followed by a global routing stage to complete the routes. PPR and SERRGE converge faster than a traditional router using a fully expanded RRG. PPR runs faster and uses less memory than SERRGE, while SERRGE yields the highest clock frequencies among the three.

Combined Architecture/Algorithm Approach to Fast FPGA Routing

We propose a new field-programmable gate array (FPGA) routing approach, which, when combined with a low-cost architecture change, results in a 40% reduction in router runtime, at the cost of a 6% area overhead and with no increase in critical path delay. Our approach begins with PathFinder-style routing, which we run on a coarsened representation of the routing architecture. This leads to fast generation of a partial routing solution where the signals are assigned to groups of wire segments rather than individual wire segments. A Boolean satisfiability (SAT)-based stage follows, generating a legal routing solution from the partial solution. We explore approximately 165 000 FPGA switch block architectures, showing that the choice of the architecture has a significant impact on the complexity of the SAT formulation, and by extension, on routing runtime. Our approach points to a new research direction, namely, reducing FPGA computer-aided design runtime by exploring FPGA architectures and algorithms together.

FPGA Design Framework Combined with Commercial VLSI CAD

The most widely used open-source field programmable gate array (FPGA) placement and routing tool is the Versatile Packing, Placement and Routing (VPR) software developed at the University of Toronto, Canada. VPR calculates area and timing using target FPGA architecture and physical information. However, it cannot be used in FPGA IP design efficiently for two reasons. First, VPR cannot directly support most newly developed FPGA architectures, and modifying the C-coded VPR so that it can be used to evaluate a number of new architectures is time consuming. Second, the accuracy of the VPR performance results is inadequate for the evaluation of a complete FPGA IP in a design that targets the production of LSI. We propose an FPGA design framework that is focused on improving FPGA IP design efficiency. A novel FPGA routing tool is developed in this framework, namely the EasyRouter which uses the C# language. When an object-oriented programming method is used, there is less source code and it is easier to manage compared to VPR, thus shortening the development time. By using simple HDL code templates, EasyRouter can automatically generate the entire HDL code for a chip and the configuration bitstream. With these files, the FPGA IP can be evaluated with commercial VLSI CAD systems with high accuracy and reliability.

A novel robust FPGA routing switch box design for ultra low power applications

Fabrication cost of application-specific integrated circuits (ASICs) is exponentially rising in deep submicron region due to rapidly rising non-recurring engineering cost. Field programmable gate arrays (FPGAs) provide an attractive alternative to ASICs but consume an order of magnitude higher power. There is a need to explore ways of reducing FPGA power consumption so that they can also be employed in ultra low power (ULP) applications instead of ASICs. Subthreshold region of operation is an ideal choice for ULP low-throughput FPGAs. The routing of an FPGA consumes most of the chip area and primarily determines the circuit delay and power consumption. There is a need to design moderate-speed ULP routing switches for subthreshold FPGA. This article proposes a novel subthreshold FPGA routing switch box (SB) that utilises the leakage voltage through transistor as biasing voltage which shows 69%, 61.2% and 30% improvement in delay, power delay product and delay variation, respectively, over conventional routing SB.

NBTI-Induced Delay Degradation Analysis of FPGA Routing Structures

Reliability issues, such as soft errors, process variations and Negative Bias Temperature Instability (NBTI), become dominant on Field Programmable Gate Arrays (FPGAs) fabricated in a nanometer process. We focus on aging degradation by NBTI, which causes threshold voltage shifts on PMOS transistors. We characterize delay degradation in the routing structures on FPGAs. The rising and falling delays vary due to NBTI and heavily depend on circuit configurations. In the independent routing switch, the delay fluctuation due to NBTI can be minimized by transistor sizing. The falling delay does not change after 10-years degradation. In the routing structures composed of the routing switches and wires, the delay fluctuation depends on the wire length and can be minimized to optimize the wire length. We also show that the signal flipping can reduce the delay degradation from 11.3% to 2.76% on the routing resources.

Accelerating FPGA Routing Through Parallelization and Engineering Enhancements Special Section on PAR-CAD 2010

We present parallelization and heuristic techniques to reduce the run-time of field-programmable gate array (FPGA) negotiated congestion routing. Two heuristic optimizations provide over 3× speedup versus a sequential baseline. In our parallel approach, sets of design signals are assigned to different processor cores and routed concurrently. Communication between cores is through the message passing interface communications protocol. We propose a geographic partitioning of signals into independent sets to help minimize the communication overhead. Our parallel implementation provides approximately 2.3× speedup using four cores and produces deterministic/repeatable results. When combined, the parallel and heuristic techniques provide over 7× speedup with four cores versus the router in the widely used Versatile Place and Route (VPR) FPGA placement/routing framework, with no significant impact on circuit speed or wirelength.