Field Programmable Gate Array Realization Research Articles

A Taguchi-Based Heterogeneous Parallel Metaheuristic ACO-PSO and Its FPGA Realization to Optimal Polar-Space Locomotion Control of Four-Wheeled Redundant Mobile Robots

This paper presents an efficient Taguchi-based heterogeneous parallel metaheuristic ant colony optimization (ACO)-particle swarm optimization (PSO), called THPACOPSO, and its field-programmable gate array (FPGA) realization to optimal polar-space locomotion control of four-wheeled redundant mobile robots. This THPACOPSO consists of one slave Taguchi-based ACO (TACO) and one slave Taguchi-based PSO (TPSO) along with a master communication operator in one chip using system-on-a-programmable chip (SoPC) methodology. This approach takes the advantages of the Taguchi quality method, ACO, PSO, parallel processing, and FPGA technique, thereby obtaining better population diversity, avoiding premature convergence and keeping parallelism. Experimental results and comparative works are conducted to present effective optimization and high accuracy of the proposed FPGA-based THPACOPSO locomotion controller for four-wheeled Swedish redundant mobile robots.

FPGA realization of a chaotic communication system applied to image processing

The hardware realization of a chaotic communication system from the description of continuous-time multi-scroll chaotic oscillators is introduced herein by using field-programmable gate arrays (FPGA). That way, two multi-scroll chaotic oscillators generating 2 and 6 scrolls are synchronized by applying Hamiltonian forms and observer approach. The synchronized master-slave topology is used to implement a secure communication system by adding chaos to an image at the transmission stage and by subtracting chaos at the recover stage. The FPGA realization begins by applying numerical methods to solve the system of equations describing the whole chaotic communication system. Further, the replacement of multipliers by single constant multiplication blocks reduces the use of hardware resources and accelerates the processing time as well. Using chaotic oscillators with 2 and 6 scrolls, three kinds of images are processed: one in black and white and two in gray tones. Finally, the experimental results confirm the appropriateness on realizing chaotic communication systems for image processing by using FPGAs.

FPGA realization of multi-scroll chaotic oscillators

Chaotic oscillators have been realized using field-programmable gate arrays (FPGAs) showing good results. However, only 2-scrolls have been observed experimentally, and all reported works use commercially-available software tools for FPGA synthesis. In this manner, as a first contribution we show the FPGA realization of two multi-scroll chaotic oscillators that are characterized by their maximum Lyapunov exponent (MLE) for generating from 2- to 6-scrolls. The first multi-scroll chaotic oscillator is based on saturated function series and the second on Chua’s circuit. As a second contribution, we show their hardware realization by applying two numerical methods: Forward Euler (FE) and Runge Kutta (RK). The advantage of realizing those multi-scroll chaotic oscillators is that one can avoid the use of multiplier entities, thus optimizing FPGA resources and increasing the processing speed, as we show by realizing single constant multiplication (SCM) blocks. The experiments are verified by performing co-simulation for an FPGA Spartan 3 of Xilinx. Finally, experimental results are shown for different values of MLE (already optimized) for both multi-scroll chaotic oscillators, and the FPGA used resources are listed for generating 6-scrolls when applying FE and RK.

ModelSim/Simulink Cosimulation and FPGA Realization of a Multiaxis Motion Controller

This paper is to implement a multiaxis servo controller and a motion trajectory planning within one chip. At first, SoPC (system on a programmable chip) technology which is composed of an Altera FPGA (field programmable gate arrays) chip and an embedded soft-core Nios II processor is taken as the development of a multiaxis motion control IC. The multiaxis motion control IC has two modules. The first module is Nios II processor which realizes the motion trajectory planning by software. It includes the step, circular, window, star, and helical motion trajectory. The second module presents a function of the multiaxis position/speed/current controller IP (intellectual property) by hardware. And VHDL (VHSIC Hardware Description Language) is applied to describe the multiaxis servo controller behavior. Before the FPGA realization, a cosimulation work by ModelSim/Simulink is applied to test the VHDL code. Then, this IP combined by Nios II processor will be downloaded to FPGA. Therefore, a fully digital multiaxis motion controller can be realized by a single FPGA chip. Finally, to verify the effectiveness and correctness of the proposed multiaxis motion control IP, a three-axis motion platform (XYZtable) is constructed and some experimental results are presented.

Performance evaluation on FPGA-implemented UWB-IR receiver for in-body to out-of-body communication systems.

In order to design an optimized transceiver structure of ultra wideband (UWB) transmission in in-body to out-of-body communications, it is necessary to make the transceiver structure be easily adjustable in order to realize a good communication performance in an experimental environment. For this purpose, we first implement our develop UWB-impulse radio (IR) receiver structure for the in-body to out-of-body communication in a field programmable gate array (FPGA) board, and evaluate the fundamental communication performance of the FPGA-implemented UWB-IR receiver by a biological-equivalent liquid phantom experiment. The FPGA configuration results indicate that our FPGA realization of the UWB-IR receiver has accomplished good communication performance with few FPGA slices. Moreover, the evaluation results in the liquid phantom experiment show that the FPGA-implemented UWB-IR receiver can achieve a bit error rate (BER) of 10(-3) up to a communication distance of 70 mm with ensuring a high data rate of 2 Mbps.

Hardware Realization of Artificial Neural Network Based Intrusion Detection & Prevention System

In the 21st century with the exponential growth of the Internet, the vulnerability of the network which connects us is on the rise at a very fast pace. Today organizations are spending millions of dollars to protect their sensitive data from different vulnerabilities that they face every day. In this paper, a new methodology towards implementing an Intrusion Detection & Prevention System (IDPS) based on Artificial Neural Network (ANN) onto Field Programmable Gate Array (FPGA) is proposed. This system not only detects different network attacks but also prevents them from being propagated. The parallel structure of an ANN makes it potentially fast for the computation of certain tasks. FPGA platforms are the optimum and best choice for the modern digital systems nowadays. The same feature makes ANN well suited for implementation in FPGA technology. Hardware realization of ANN to a large extent depends on the efficient implementation of a single neuron. However FPGA realization of ANNs with a large number of neurons is still a challenging task. The proposed multilayer ANN based IDPS uses multiple neurons for higher performance and greater accuracy. Simulation of the design in MATLAB SIMULINK 2010b by using Knowledge Discovery and Data Mining (KDD) CUP dataset shows a very good performance. Subsequently MATLAB HDL coder was used to generate VHDL code for the proposed design that produced Intellectual Property (IP) cores for Xilinx Targeted Design Platforms. For evaluation purposes the proposed design was synthesized, implemented and tested onto Xilinx Virtex-7 2000T FPGA device.

A novel productivity-driven logic element for field-programmable devices

Although various techniques have been proposed for power reduction in field-programmable devices (FPDs), they are still all based on conventional logic elements (LEs). In the conventional LE, the output of the combinational logic (e.g. the look-up table (LUT) in many field-programmable gate arrays (FPGAs)) is connected to the input of the storage element; while the D flip-flop (DFF) is always clocked even when not necessary. Such unnecessary transitions waste power. To address this problem, we propose a novel productivity-driven LE with reduced number of transitions. The differences between our LE and the conventional LE are in the FFs-type used and the internal LE organisation. In our LEs, DFFs have been replaced by T flip-flops with the T input permanently connected to logic value 1. Instead of connecting the output of the combinational logic to the FF input, we use it as the FF clock. The proposed LE has been validated via Simulation Program with Integrated Circuit Emphasis (SPICE) simulations for a 45-nm Complementary Metal–Oxide–Semiconductor (CMOS) technology as well as via a real Computer-Aided Design (CAD) tools on a real FPGA using the standard Microelectronic Center of North Carolina (MCNC) benchmark circuits. The experimental results show that FPDs using our proposal not only have 48% lower total power but also run 17% faster than conventional FPDs on average.

Area-Efficient VLSI Implementation for Parallel Linear-Phase FIR Digital Filters of Odd Length Based on Fast FIR Algorithm

In this Paper, we propose a low-power multiplier design methodology which has multiplier-andaccumulator for high speed and by adopting the new Shift and adds implementation approach. This multiplier is designed by equipping the Power Suppression Technique on DA (distributed arithmetic) algorithm. The Shift and adder will avoid the unwanted addition and thus minimize the switching power dissipation, the performance was improved. When the DA algorithm is directly applied in FPGA (field programmable gate array) to realize FIR (finite impulse response) filter, it is easy to achieve the best configuration in the coefficient of FIR filter, the storage resources and the computing speed. The parallel FIR structures can lead to significant hardware savings for symmetric convolution in odd length from the existing FFA parallel FIR filter, particularly when the length of the filter is large. According to this, the paper provides the detailed analysis and discussion in the algorithm, the memory size and the look up table speed. Also, the corresponding optimization and improvement measures are discussed. The design results of simulation and test show that this method greatly reduces the FPGA hardware resource and the high speed filtering is achieved. The design has a big breakthrough compared to the traditional FPGA realization.

Runtime Scheduling, Allocation, and Execution of Real-Time Hardware Tasks onto Xilinx FPGAs Subject to Fault Occurrence

This paper describes a novel way to exploit the computation capabilities delivered by modern Field-Programmable Gate Arrays (FPGAs), not only towards a higher performance, but also towards an improved reliability. Computation-specific pieces of circuitry are dynamically scheduled and allocated to different resources on the chip based on a set of novel algorithms which are described in detail in this article. These algorithms consider most of the technological constraints existing in modern partially reconfigurable FPGAs as well as spontaneously occurring faults and emerging permanent damage in the silicon substrate of the chip. In addition, the algorithms target other important aspects such as communications and synchronization among the different computations that are carried out, either concurrently or at different times. The effectiveness of the proposed algorithms is tested by means of a wide range of synthetic simulations, and, notably, a proof-of-concept implementation of them using real FPGA hardware is outlined.

FPGA Implementation for Real-Time Empirical Mode Decomposition

This paper presents a novel field-programmable gate array (FPGA) based method for empirical mode decomposition (EMD) in real time. Traditionally, EMD can be easily implemented and developed using a high-level computer language in a PC or DSP chip. However, it is difficult to implement EMD in a hardware environment. This paper develops EMD for real-time applications using a hardware-based FPGA. The proposed FPGA-based method calculates the upper and lower envelopes in EMD point by point by using a circular queue to temporarily store values of maxima and minima, from which the upper and lower envelopes in the EMD can be determined continuously. Additionally, an attempt is made to increase the efficiency of the computational process by cascading several identical modules as a serial pipeline structure in order to conduct an iterative loop for calculating the intrinsic mode functions in EMD. The fast process from the serial pipeline structure results in real-time computation with a sampling rate of up to 12.5 MHz and mitigation of the end effect. The proposed method is validated by the simulation results obtained by Quartus II and verified by FPGA (Altera Stratix III EP3SL150F1152C2) realization, revealing its effectiveness in real-time applications.

Portable, Flexible, and Scalable Soft Vector Processors

Field-programmable gate arrays (FPGAs) are increasingly used to implement embedded digital systems, however, the hardware design necessary to do so is time-consuming and tedious. The amount of hardware design can be reduced by employing a microprocessor for less-critical computation in the system. Often this microprocessor is implemented using the FPGA reprogrammable fabric as a soft processor which presently have simple architectures and moderate performance. Our goal is to scale the performance of existing soft processors hence expanding their suitability to more critical computation. To this end we propose extending soft processors with vector extensions to exploit the abundant data parallelism found in many embedded kernels. Such a soft vector processor can execute these kernels much faster than a single-core hence reducing the need for hardware implementations. We observe this improved execution speed through experimentation with vector extended soft processor architecture (VESPA) which is designed, implemented, and evaluated on real FPGA hardware. VESPA is shown to effectively scale performance up to 32 lanes, while providing substantial architectural flexibility to create a fine-grained design space. With these characteristics, and portability across FPGA devices, soft vector processors can provide exact-fit architectures which can efficiently and more easily implement data parallel workloads over custom FPGA hardware design.

FPGA realization of the LIRA neural classifier

Different types of neural networks can be used to classify images. We propose to apply LIRA (LImited Receptive Area) neural classifier to work with images. To accelerate the neural network functioning we propose a digital implementation of the LIRA neural classifier. We begin with a neuron design, and then continue with the neural network simulation. The advantage of neural network is its parallel structure and possibility of the training. FPGA (Field Programmable Gate Array) allows the implementation of these parallel algorithms in a single device. Speed of classification is one of the most important requirements in adaptive control systems based on computer vision. The contribution of this article is LIRA neural classifier implementation with FPGA for two classes to accelerate the training and recognition processes.

An FPGA realization of simplified turbo decoder architecture

The key issue of applying Turbo codes is to find an efficient implementation of turbo decoder. This paper addresses the implementation of a simplified and efficient turbo decoder in field programmable gate array (FPGA) technology. A simplified and efficient implementation of a Turbo decoder with minor performance loss has been proposed. An integer Turbo decoder based on the standard 2’s complement number system after considering the issues of dynamic range, truncation effect and other algorithm related subjects has been introduced. The efficient implementation comes from algorithm modification, integer arithmetic and compact hardware management. Based on the Max-Log-MAP decoding algorithm, the branch metric is modified by weighting a priori value, resulting in a significant BER improvement. The Turbo decoder takes in 8-level integer inputs generates 7-bit soft-decisions and calculates all metrics on integers, avoiding complex floating point or fixed-point arithmetic. By manipulating memory address, delay associated with interleaving and de-interleaving is eliminated, resulting in much higher throughput. Also, by taking advantage of identical decoder function, Turbo decoder is implemented in a single-decoder structure, making efficient use of memory and logic cells. Key words: Turbo, Max-Log-MAP, field programmable gate array, bit error ratio.

Behavioral simulation and synthesis of biological neuron systems using synthesizable VHDL

Neurons are complex biological entities which form the basis of nervous systems. Insight can be gained into neuron behavior through the use of computer models and as a result many such models have been developed. However, there exists a trade-off between biological accuracy and simulation time with the most realistic results requiring extensive computation. To address this issue, a novel approach is described in this paper that allows complex models of real biological systems to be simulated at a speed greater than real time and with excellent accuracy. The approach is based on a specially developed neuron model VHDL library which allows complex neuron systems to be implemented on field programmable gate array (FPGA) hardware. The locomotion system of the nematode Caenorhabditis elegans is used as a case study and the measured results show that the real time FPGA based implementation performs 288 times faster than traditional ModelSim simulations for the same accuracy.

Simulink/Modelsim Co-Simulation and FPGA Realization of Speed Control IC for PMSM Drive

PMSM (Permanent Magnetic Synchronous Motor) has been increasingly used in many high performance application due to its advantages of high power density, high power factor and efficiency. The design and implementation of a fuzzy-control based speed control IC for PMSM from Simulink/Modelsim co-simulation to FPGA (Field Programmable Gate Array) realization is presented in this paper. Firstly, a SVPWM scheme, vector control method and fuzzy controller are derived and applied in the speed control IC of PMSM drive. Secondly, the Very-High-Speed IC Hardware Description Language (VHDL) is adopted to describe the behavior of the aforementioned control algorithms. To evaluate the effectiveness and correctness of the proposed speed control IC, a co-simulation work performed by Matlab/Simulink and Modelsim is firstly conducted. Then, an experimental system by FPGA chip, Nios processor and motor driving board is set up to further validate the performance of the proposed speed control IC. Finally, the results in simulation and in experiment will be compared and discussed.

Fast KNN Classification Based On Softcore Cpu And Reconfigurable Hardware

This paper presents a novel architecture for k-nearest neighbor (kNN) classification using field programmable gate array (FPGA). In the architecture, the first k closest vectors in the design set o...

Efficient FPGA Realization of CORDIC With Application to Robotic Exploration

We present an area efficient method and field programmable gate array (FPGA) realization for two common operations in robotics, namely, the following: (1) rotating a vector in 2D and (2) aligning a vector in the plane with a specific axis. It is based on a new coordinate rotation digital computer (CORDIC) algorithm that is designed to work with a small set of elementary angles. Unlike conventional CORDIC, the proposed algorithm does not require a ROM and a full-fledged barrel shifter. The proposed CORDIC algorithm is used to design hardware efficient solutions for two mobile robotic tasks in an indoor environment without employing division and floating-point calculations. Experiments with a sole low end FPGA based robot in static as well as dynamic environments validate the power of the approach.

Subdivision and direction recognition of λ/16 of orthogonal fringes for nanometric measurement

Subdivision is one of the essential methods to improve the measurement resolution of optical instruments. A new method is proposed to solve lambda/16 bidirectional subdivision and direction recognition for orthogonal interference signals by constructing two sets of reference signals and using zero-cross detection. The experimental results prove that the method is efficient for orthogonal signals and has good real-time performance by field-programmable gate array realization. This method is easy to realize by use of electronic design automation tools and can be widely used in the signal processing system of optical measurement instruments such as a moiré fringe measurement system and laser interferometer.

FPGA Realization of an Adaptive Fuzzy Controller for PMLSM Drive

This paper presents a hardware realization of an adaptive fuzzy controller (AFC) for a permanent-magnet linear synchronous motor (PMLSM) drive system based on the field-programmable gate-array (FPGA) technology. First, a mathematics model of the PMLSM drive is defined; then, to increase the performance of the PMLSM drive system, an AFC constructed by a fuzzy basis function and a parameter-adjustable mechanism is applied to the position-control loop of the PMLSM drive system to cope with the effect of the system dynamic uncertainty and the external load. A point-to-point (PTP) motion trajectory designed with the trapezoidal velocity profile is considered to smooth the move of the PMLSM at the start and stop conditions. Second, a finite-state machine (FSM) joined by a multiplier, an adder, a lookup table, and some comparators and registers is presented to model the overall AFC, and a VHSIC hardware description language is adopted to describe the circuit of the FSM. In addition, a Nios II embedded processor is used to implement the function of the PTP motion-trajectory algorithm by software. Finally, an experimental system is established to verify the effectiveness of the proposed FPGA-based AFC and the PTP motion-control system, and some experimental results are confirmed theoretically.

A Fully Pipelined Architecture for the LOCO-I Compression Algorithm

This paper presents the design of a novel architectural implementation of the LOCO-I compression scheme, the lossless/near-lossless algorithm used inside the JPEG-LS standard. Differently from what previously reported in literature, the proposed design fully exploits the sequential nature of the algorithm by means of a pipelined architecture, without modifications to the original compression scheme. The result is a good performance circuit well fitted for field-programmable gate-array realization, thus devised for application in the wearable computers and remote sensing domains.