Field Programmable Gate Array Realization Research Articles

Comparative analysis and FPGA realization of different control synchronization approaches for chaos-based secured communication systems.

Synchronization of the chaotic systems has attracted much attention in recent years due to its vital applications in secured communication systems. In this paper, an implementation and comparative analysis of two different control approaches for synchronization between two identical four-dimensional hyperchaotic systems is presented. The two control approaches are the Adaptive nonlinear controller and the linear optimal quadratic regulator LQR. To demonstrate the effectiveness of each controller, the numerical simulation is presented using Matlab/Simulink and the control law is derived. The performance of the proposed controllers is compared based on four factors; response time, squared error integration, energy applied from the controller, and cost function. To measure the robustness of the control approaches, the performance factors are compared when there is a change in system parameters and a variation in the initial conditions. Then the proposed synchronization methods are implemented on the FPGA platform to demonstrate the utilized resources on Field Programmable Gate Array (FPGA) hardware platform and the operation speed. Finally, to generalize the results of the comparison, the study is implemented for the synchronization of another secured communication system consisting of two identical three-dimensional chaotic. The experimental results show that the LQR method is more effective than the Adaptive controller based on the performance factors we propose. Moreover, the LQR is much simpler to implement on hardware and requires fewer resources on the FPGA.

Quantization-Aware NN Layers with High-throughput FPGA Implementation for Edge AI

Over the past few years, several applications have been extensively exploiting the advantages of deep learning, in particular when using convolutional neural networks (CNNs). The intrinsic flexibility of such models makes them widely adopted in a variety of practical applications, from medical to industrial. In this latter scenario, however, using consumer Personal Computer (PC) hardware is not always suitable for the potential harsh conditions of the working environment and the strict timing that industrial applications typically have. Therefore, the design of custom FPGA (Field Programmable Gate Array) solutions for network inference is gaining massive attention from researchers and companies as well. In this paper, we propose a family of network architectures composed of three kinds of custom layers working with integer arithmetic with a customizable precision (down to just two bits). Such layers are designed to be effectively trained on classical GPUs (Graphics Processing Units) and then synthesized to FPGA hardware for real-time inference. The idea is to provide a trainable quantization layer, called Requantizer, acting both as a non-linear activation for neurons and a value rescaler to match the desired bit precision. This way, the training is not only quantization-aware, but also capable of estimating the optimal scaling coefficients to accommodate both the non-linear nature of the activations and the constraints imposed by the limited precision. In the experimental section, we test the performance of this kind of model while working both on classical PC hardware and a case-study implementation of a signal peak detection device running on a real FPGA. We employ TensorFlow Lite for training and comparison, and use Xilinx FPGAs and Vivado for synthesis and implementation. The results show an accuracy of the quantized networks close to the floating point version, without the need for representative data for calibration as in other approaches, and performance that is better than dedicated peak detection algorithms. The FPGA implementation is able to run in real time at a rate of four gigapixels per second with moderate hardware resources, while achieving a sustained efficiency of 0.5 TOPS/W (tera operations per second per watt), in line with custom integrated hardware accelerators.

Dynamics analysis, FPGA realization and image encryption application of a 5D memristive exponential hyperchaotic system

The exponential function is one of the basic elementary functions, which plays an irreplaceable role in mathematics and is also widely used in practical activities such as life and production. In this paper, a new 5D memristive exponential hyperchaotic system (MEHS) is proposed, which includes an exponential term and a nonlinear flux-controlled memristive model. Fundamental dynamics characteristics of the system are analyzed using phase diagram, Lyapunov exponential spectrum and bifurcation diagram. When appropriate parameter sets are selected, the MEHS exhibits a rich set of dynamic behaviors, including the coexistence of periodic and periodic attractors, periodic and chaotic attractors, chaotic and hyperchaotic attractors. In addition, the Field Programmable Gate Array (FPGA) is used to realize the 5D MEHS, and the experimental results are consistent with the numerical simulation results on MATLAB. Finally, an image encryption application based on the 5D MEHS is presented. The security analysis shows the feasibility and effectiveness of the image encryption algorithm.

An Efficient Multi-Secret Image Sharing System Based on Chinese Remainder Theorem and Its FPGA Realization

Multi-Secret Image Sharing (MSIS) is important in information security when multiple images are shared in an unintelligible form to different participants, where the images can only be recovered using the shares from participants. This paper proposes a simple and efficient ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$n,n$ </tex-math></inline-formula> )-MSIS system for colored images based on XOR and Chinese Remainder Theorem (CRT), where all the <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$n$ </tex-math></inline-formula> share are required in the recovery. The system improves the security by adding dependency on the input images to be robust against differential attacks, and by using several delay units. It works with even and odd number of inputs, and has a long sensitive system key design for the CRT. Security analysis and a comparison with related literature are introduced with good results including statistical tests, differential attack measures, and key sensitivity tests as well as performance analysis tests such as time and space complexity. In addition, Field Programmable Gate Array (FPGA) realization of the proposed system is presented with throughput 530 Mbits/sec. Finally, the proposed MSIS system is validated through software and hardware with all statistical analyses and proper hardware resources with low power consumption, high throughput and high level of security.

A New Hyperchaotic Two-Scroll System: Bifurcation Study, Multistability, Circuit Simulation, and FPGA Realization

With the swift advancement of chaos theory, the modeling, chaotic oscillations, and engineering applications of chaotic and hyperchaotic systems are important topics in research. In this research paper, we elucidate our findings of a new four-dimensional two-scroll hyperchaotic system having only two quadratic nonlinearities and carry out a detailed bifurcation study of the proposed dynamical model. Also, an electronic circuit has been constructed for the new system using MultiSim (Version 14). The implementation of the new 4-D hyperchaotic system in a field-programmable gate array (FPGA) is performed herein by applying two numerical methods, viz. Forward Euler Method and Trapezoidal Method. The experimental results show a good match with the simulated hyperchaotic attractors. We also provide details of the hardware resources used for an FPGA Basys 3 Xilinx Artix-7 XC7A35T-ICPG236C.

CORDIC-Based FPGA Realization of a Spatially Rotating Translational Fractional-Order Multi-Scroll Grid Chaotic System

This paper proposes an algorithm and hardware realization of generalized chaotic systems using fractional calculus and rotation algorithms. Enhanced chaotic properties, flexibility, and controllability are achieved using fractional orders, a multi-scroll grid, a dynamic rotation angle(s) in two- and three-dimensional space, and translational parameters. The rotated system is successfully utilized as a Pseudo-Random Number Generator (PRNG) in an image encryption scheme. It preserves the chaotic dynamics and exhibits continuous chaotic behavior for all values of the rotation angle. The Coordinate Rotation Digital Computer (CORDIC) algorithm is used to implement rotation and the Grünwald–Letnikov (GL) technique is used for solving the fractional-order system. CORDIC enables complete control and dynamic spatial rotation by providing real-time computation of the sine and cosine functions. The proposed hardware architectures are realized on a Field-Programmable Gate Array (FPGA) using the Xilinx ISE 14.7 on Artix 7 XC7A100T kit. The Intellectual-Property (IP)-core-based implementation generates sine and cosine functions with a one-clock-cycle latency and provides a generic framework for rotating any chaotic system given its system of differential equations. The achieved throughputs are 821.92 Mbits/s and 520.768 Mbits/s for two- and three-dimensional rotating chaotic systems, respectively. Because it is amenable to digital realization, the proposed spatially rotating translational fractional-order multi-scroll grid chaotic system can fit various secure communication and motion control applications.

Energy-Aware Real-Time Tasks Processing for FPGA-Based Heterogeneous Cloud

Cloud computing is becoming a popular model of computing. Due to the increasing complexity of the cloud service request, it often exploits heterogeneous architecture. Moreover, some service requests (SRs)/tasks exhibit real-time features, which are required to be handled within a specified duration. Along with the stipulated temporal management, the strategy should also be energy efficient, as energy consumption in cloud computing is challenging. In this paper, we have proposed a strategy, called “Efficient Resource Allocation of Service Request” (ERASER) for energy efficient allocation and scheduling of periodic real-time SRs on cloud platform. The cloud platform is consists of Field Programmable Gate Arrays (FPGAs) as Processing Elements (PEs) along with the General Purpose Processors (GPP). We have further proposed, an SR migration technique to reduce the tasks rejection by serving maximum SRs. Simulation based experimental results demonstrate that the proposed methodology is capable to achieve upto 90 percent resource utilization with only 26 percent SR rejection rate over different experimental scenarios. Comparison results with other state-of-the-art techniques reveal that the proposed strategy outperforms the existing technique with 17 percent reduction in SR rejection rate and 21 percent reduction in energy consumption. Further, the simulation outcomes have been validated on real FPGA test-bed based on Xilinx Zynq SoC with standard benchmark tasks.

FPGA Realization and Lyapunov–Krasovskii Analysis for a Master-Slave Synchronization Scheme Involving Chaotic Systems and Time-Delay Neural Networks

In this paper, the trajectory tracking control and the field programmable gate array (FPGA) implementation between a recurrent neural network with time delay and a chaotic system are presented. The tracking error is globally asymptotically stabilized by means of a control law generated from the Lyapunov–Krasovskii and Lur’e theory. The applicability of the approach is illustrated by considering two different chaotic systems: Liu chaotic system and Genesio–Tesi chaotic system. The numerical results have shown the effectiveness of obtained theoretical results. Finally, the theoretical results are implemented on an FPGA, confirming the feasibility of the synchronization scheme and showing that it is hardware realizable.

FPGA Realization of ANFIS Controller Using a Proposed Digital Design

The design and realization of Adaptive Neuro-Fuzzy Inference System (ANFIS) controller based on Field Programmable Gate Array (FPGA) is presented in this paper. The controller intended to control the temperature of medical oven. A novel design of digital ANFIS is presented here for the implementation process. Different controllers are designed and their results are compared using MATLAB program to show the ANFIS superiority. The designed controllers tested for cell cultures application at 37.5. A reduction is made for the designed digital ANFIS due to the used FPGA limitations. The reduced design minimizes the utilized slices from 366% to 3% and LUTs from 364% to 3%. The reduced design reached an optimum size for this controller to utilize a smallest memory size. A real-time FPGA implementation of the proposed digital ANFIS have been done and verified through Xilinx ISE 14.6 using the VHDL language. The VHDL code for the controller is produced, aggregated and downloaded on the FPGA Spartan 3A/AN FPGA kit. A comparison between the simulation and implementation results is made. The matching between these results proves the effectiveness and robustness of the proposed digital ANFIS and the excellent performance of the FPGA based controller.

Mathematical Model and FPGA Realization of a Multi-Stable Chaotic Dynamical System with a Closed Butterfly-Like Curve of Equilibrium Points

This paper starts with a review of three-dimensional chaotic dynamical systems equipped with special curves of balance points. We also propose the mathematical model of a new three-dimensional chaotic system equipped with a closed butterfly-like curve of balance points. By performing a bifurcation study of the new system, we analyze intrinsic properties such as chaoticity, multi-stability, and transient chaos. Finally, we carry out a realization of the new multi-stable chaotic model using Field-Programmable Gate Array (FPGA).

A New 4-D Multi-Stable Hyperchaotic System With No Balance Point: Bifurcation Analysis, Circuit Simulation, FPGA Realization and Image Cryptosystem

In this work, we describe the model of a new 4-D hyperchaotic system with no balance point and deduce that the new hyperchaotic system has a hidden attractor. We present a detailed bifurcation analysis for the new hyperchaotic dynamo system with respect to the system parameters and also exhibit that the new hyperchaotic system displays multistability with coexisting attractors. Using NI Multisim 14.0, we design an electronic circuit for the implementation of the new 4-D hyperchaotic system and present the circuit simulation results. We also show the implementation of the new 4-D hyperchaotic system by using a field programmable gate array (FPGA). The hardware resources are reduced by designing single-constant multipliers, adders, subtractors and multipliers. The FPGA design is done for three numerical methods, namely: Forward-Euler, Backward-Euler and fourth-order Runge-Kutta. We demonstrate that experimental chaotic attractors are in good agreement with theoretical simulations. To verify the ability of the presented hyperchaotic system for designing robust cryptosystems, we suggest a novel image cryptosystem using the proposed hyperchaotic system. Simulation outcomes confirm the effectiveness of the proposed image cryptosystem, and consequently, the effectiveness of the proposed 4-D hyperchaotic system in designing diverse cryptographic purposes.

A 5-D Multi-Stable Hyperchaotic Two-Disk Dynamo System With No Equilibrium Point: Circuit Design, FPGA Realization and Applications to TRNGs and Image Encryption

In this work, we devise a new 5-D hyperchaotic dynamo system by adding two feedback controllers to the Rikitake 2-disk dynamo system (1958). We show that the new 5-D hyperchaotic system does not possess any equilibrium point and deduce that the new 5-D system has a hidden hyperchaotic attractor. Using Multisim, we develop an electronic circuit design of the new 5-D hyperchaotic dynamo system for practical applications. We also exhibit the implementation of the new 5-D hyperchaotic dynamo system by using a field-programmable gate array (FPGA), which requires adders, subtractors and multipliers. The hardware resources are given for the application of three numerical methods, all of them providing results in good agreement with MATLAB simulations. As an application, we devise a dual core high speed hybrid true random number generator (TRNG) using Ring and Heun algorithm based on the new 5-D hyperchaotic oscillator on FPGA. Based on the hyperchaotic features of the proposed 5-D hyperchaotic dynamo system, we suggest a new encryption approach for colour images. Simulation outcomes of the presented encryption approach confirm that our chaotic system has good cryptographic properties and its usability in different cryptographic purposes.

Real time FPGA implementation of a high speed and area optimized Harris corner detection algorithm

Harris corner detection is an algorithm frequently used in image processing and computer vision applications to detect corners in an input image. In most modern applications of image processing, there is a need for real time implementation of algorithms such as Harris corner detection in hardware systems such as field-programmable gate arrays (FPGAs). FPGAs allow faster algorithmic throughput, which is required to match real time speeds or cases where there is a requirement to process faster data rates. High level synthesis tools offer higher abstraction level to designers with continued verification during the design flow and hence are getting popular with the design community. This paper proposes a high speed and area optimized implementation of a Harris corner detection algorithm. The proposed implementation was actualized using a novel high-level synthesis (HLS) design method based on application-specific bit widths for intermediate data nodes. Register transfer level (RTL) code was generated using MATLAB HDL coder for HLS. The generated hardware description language (HDL) code was implemented on Xilinx ZedBoard using Vivado software and verified for functionality in real time with input video stream. The obtained results are superior to those of previous implementations in terms of area(smaller gate count on target FPGA) and speed for the same target board.

Power- and Area-Optimized High-Level Synthesis Implementation of a Digital Down Converter for Software-Defined Radio Applications

In digital signal processing, digital down converters (DDCs) convert digitized, band-limited signals to lower frequency signals at a smaller sampling rate to simplify subsequent filtering stages. Software-defined radio (SDR) is a radio communication system in which components that are traditionally implemented in hardware are implemented in software on an embedded system. DDCs are widely used in modern communication systems, such as SDRs. Herein, we propose a low-power- and area-optimized implementation of a DDC for SDR applications. The DDC was designed using an innovative and novel high-level synthesis (HLS) design method based on application-specific bit widths for data nodes. The results achieved after a field programmable gate array (FPGA) implementation are superior to those obtained from hand-coded register transfer level (RTL) implementations in terms of area and power efficiency, with almost the same speed of operation. Our results were obtained using the MATLAB hardware description language (HDL) coder for HLS and Xilinx Vivado (a software for the synthesis and analysis of HDL designs) for synthesis. The DDC down-converts an input of 200 MHz signal to an output of 2 MHz signal. This implementation was conducted on a real FPGA hardware (Xilinx Kintex-7) and verified against the design specifications using an FPGA in the loop feature of HDL Verifier and MATLAB. In addition, we propose a generic methodology for improving the area, speed, and power for different application designs and HLS tools. The proposed methodology is also applicable to hand-coded RTL designs for any application.

A high‐performance FPGA‐based multicrossbar prioritized network‐on‐chip

SummaryHigh performance system‐on‐chip (SoCs) designs have led to high‐density integrated circuits using field programmable gate arrays (FPGAs) for rapid prototyping and reconfigurable digital circuits. Using FPGA reconfigurability, it is possible to design a configurable network‐on‐chip (NoC) for different applications. NoC architectures provide efficient communication infrastructures for implementing very large SoCs. In this article, we propose HiFMP, a high‐performance FPGA‐based multicrossbar prioritized NoC router. The aim followed by the proposed router is designing a low‐power NoC router with high performance in terms of energy‐efficiency, network throughput, area, and latency for efficient FPGA realization. HiFMP is a parameterizable router, and is effectively used for an FPGA‐based NoC with mesh topology. Performance evaluations include network‐level analysis and hardware exploration; the results demonstrate the effectiveness and high performance of HiFMP in terms of latency, throughput, power consumption, and area, comparing with the existing related architectures.

FPGA Realization of Deep Neural Network for Hardware Trojan Detection

With the increase in outsourcing design and fabrication, malicious third-party vendors often insert hardware Trojan (HT) in the integrated Circuits(IC). It is difficult to identify these Trojans since the nature and characteristics of each Trojan differ significantly. Any method developed for HT detection is limited by its capacity on dealing with varied types of Trojans. The main purpose of this study is to show using deep learning (DL), this problem can be dealt with some extent and the effect of deep neural network (DNN) when it is realized on field programmable gate array (FPGA). In this paper, we propose a comparison of accuracy in finding faults on ISCAS’85 benchmark circuits between random forest classifier and DNN. Further for the faster processing time and less power consumption, the network is implemented on FPGA. The results show the performance of deep neural network gets better when a large number of nets are used and faster in the execution of the algorithm. Also, the speedup of the neuron is 100x times better when implemented on FPGA with 15.32% of resource utilization and provides less power consumption than GPU.

Low-complexity blind polarization demultiplexing and frequency domain equalization for coherent passive optical network systems

Algorithmic and architectural options and trade-offs between performance and complexity/power dissipation are necessary to consider in the transfer of coherent technology from long-haul transmission to short-reach application. An adaptive equalization algorithm cascading polarization demultiplexing and frequency domain equalization is proposed to target passive optical network applications that feature extremely low computational complexity. Three coordinate rotation digital computer-based vector rotators are introduced to realize polarization demultiplexing without performing multiplications. A simplified gradient descent algorithm is proposed to search and trace the state of polarization. A nonbutterfly adaptive equalizer in the frequency domain for each polarization is designed to handle link chromatic dispersion and the imperfection of the transceiver frequency response. The performance of the proposed equalization scheme is experimentally verified by a 32-GBaud dual-polarization Nyquist quadrature phase-shift keying system over 20-km standard single-mode fiber transmission. With the proposed method, the number of hardened multipliers for field-programmable gate array realization is reduced by ∼85 % compared with a conventional 2 × 2 multiple-input multiple-output finite impulse response filter with the same receiver sensitivity.

A 3-D Multi-Stable System With a Peanut-Shaped Equilibrium Curve: Circuit Design, FPGA Realization, and an Application to Image Encryption

A new 3-D chaotic dynamical system with a peanut-shaped closed curve of equilibrium points is introduced in this work. Since the new chaotic system has infinite number of rest points, the new chaotic model exhibits hidden attractors. A detailed dynamic analysis of the new chaotic model using bifurcation diagrams and entropy analysis is described. The new nonlinear plant shows multi-stability and coexisting convergent attractors. A circuit model using MultiSim of the new 3-D chaotic model is designed for engineering applications. The new multi-stable chaotic system is simulated on a field-programmable gate array (FPGA) by applying two numerical methods, showing results in good agreement with numerical simulations. Consequently, we utilize the properties of our chaotic system in designing a new cipher colour image mechanism. Experimental results demonstrate the efficiency of the presented encryption mechanism, whose outcomes suggest promising applications for our chaotic system in various cryptographic applications.

Numerical Simulations and FPGA Implementations of Fractional-Order Systems Based on Product Integration Rules

Product integration (PI) rules are well known numerical techniques that are used to solve differential equations of integer and, recently, fractional orders. Due to the high memory dependency of the PI rules used in solving fractional-order systems (FOS), their hardware implementation is very difficult and resources-demanding. In this paper, modified versions of the PI rules are introduced to facilitate their digital implementations. The studied rules are PI rectangular, PI trapezoidal, and predict-evaluate-correct-evaluate (PECE) rules. The three modified versions of the PI rules are validated using a benchmark system of differential equations for different sizes of the memory window to show the effect of the window size on the solution accuracy. Additionally, the three modified versions of the PI rules are used to simulate a novel fractional-order chaotic system (FOCS) where its bifurcation diagrams are discussed with the window length parameter. The chaotic system is then implemented on a Field Programmable Gate Array (FPGA). There are only a few trials in literature to implement the fractional PECE algorithm on FPGA, nevertheless, the proposed FPGA realization is compared with the most recent of these trials. The FPGA implementations of the three PI rules are made using Xilinx ISE 14.7 on Artix 7 kit. The achieved throughput are 1280 Mbits/sec for PI rectangular, 128.8 Mbits/sec for PI trapezoidal, and 129.12 Mbits/sec for fractional-order PECE.

FPGA Realization of Fractional Order Neuron

In this paper fractional Hindmarsh Rose (HR) neuron, which mimics several behaviors of a real biological neuron is implemented on field programmable gate array (FPGA). The results show several differences in the dynamic characteristics of integer and fractional order Hindmarsh Rose neuron models. The integer order model shows only one type of firing characteristics when the parameters of model remains same. The fractional order model depicts several dynamical behaviors even for the same parameters as the order of the fractional operator is varied. The firing frequency increases when the order of the fractional operator decreases. The fractional order is therefore key in determining the firing characteristics of biological neurons. To implement this neuron model first the digital realization of different fractional operator approximations are obtained, then the fractional integrator is used to obtain the low power and low cost hardware realization of fractional HR neuron. The fractional neuron model has been implemented on a low voltage and low power circuit and then compared with its integer counter part. The hardware is used to demonstrate the different dynamical behaviors of fractional HR neuron for different type of approximations obtained for fractional operator in this paper. A coupled network of fractional order HR neurons is also implemented. The results also show that synchronization between neurons increases as long as coupling factor keeps on increasing.