Field Programmable Gate Array Platform Research Articles

An Integrated Real-Time FMCW Radar Baseband Processor in 40-nm CMOS

In this paper, a pipelined frequency-modulated continuous-wave (FMCW) radar baseband processor applied to real-time applications is proposed and implemented in 40-nm CMOS technology. The FMCW radar signal processing time is analyzed according to the system specifications. On the basis of the theoretical analysis and systematic considerations, a pipelined baseband architecture with internal single-port static random access memory (SRAM) is employed. The baseband processor is mainly composed of two-dimensional fast Fourier transform (2D-FFT), two-dimensional constant false alarm rate (2D-CFAR), digital beam-forming (DBF), and memory control modules. The 2D-FFT module is structured with a pipelined scheme and avoids the waste of data transferring time between modules. The 2D-CFAR module is programmable for different applications. The designed address control is proposed to depose the edge cells. The processor occupies a core chip area of 3.353 mm ×3.353 mm and has been tested on the personal computer (PC) and field programmable gate array (FPGA) platform. The power consumption and processing time are also analyzed and compared with other works. The processor consumes 55.65 mW, including SRAMs. The processing time is 12.67 ms with the maximum window size and 256 targets when operating at 125 MHz. This time is estimated based on the assumption that each chirp lasts for 0.04096 ms, and data input takes 10.48 ms. Within this period, the range FFT is completed. The Doppler FFT, 2D-CFAR with the maximum window size, and DBF with 256 targets require 0.80 ms, 1.16 ms, and 0.23 ms respectively.

A Secure Hardware Implementation for Elliptic Curve Digital Signature Algorithm

Since the end of the 1990s, cryptosystems implemented on smart cards have had to deal with two main categories of attacks: side-channel attacks and fault injection attacks. Countermeasures have been developed and validated against these two types of attacks, taking into account a well-defined attacker model. This work focuses on small vulnerabilities and countermeasures related to the Elliptic Curve Digital Signature Algorithm (ECDSA) algorithm. The work done in this paper focuses on protecting the ECDSA algorithm against fault-injection attacks. More precisely, we are interested in the countermeasures of scalar multiplication in the body of the elliptic curves to protect against attacks concerning only a few bits of secret may be sufficient to recover the private key. ECDSA can be implemented in different ways, in software or via dedicated hardware or a mix of both. Many different architectures are therefore possible to implement an ECDSA-based system. For this reason, this work focuses mainly on the hardware implementation of the digital signature ECDSA. In addition, the proposed ECDSA architecture with and without fault detection for the scalar multiplication have been implemented on Xilinx field programmable gate arrays (FPGA) platform (Virtex-5). Our implementation results have been compared and discussed. Our area, frequency, area overhead and frequency degradation have been compared and it is shown that the proposed architecture of ECDSA with fault detection for the scalar multiplication allows a trade-off between the hardware overhead and the security of the ECDSA.

Design and Development of High Voltage High Pulse Power Supply using FPGA for Dynamic Impedance Matching

High Voltage High Pulse Power Supply (HVHPPS) is designed with the goal to match fixed load, so thatprecise pulse output can be achieved. Generally the loads involve magnetron, klystron, and particle accelerators etc. The HVHPPS output pulse shape changes with load impedance variation due to various reasons. Due to changes in impedance, the performance of Pulse Power Supply degrades and reflects the power at the source end which causes component failure and system shut down. To overcome such problems, a scale down High Voltage High Pulse Power is designed and developed to match the dynamic impedance variations upto 25 % of mismatch. In earlier days, all HVHPPS were designed using microcontrollers where the problem of pulse to pulse monitoring and computational speed was compromised. The availability of variable and self-defined, Field Programmable Gate Array (FPGA) controller, which provided flexibility to design the pulse to pulse shaping and various vital parameter monitoring, made it possible. This paper presents the design and implementation of HVHPPS over an FPGA platform to meet the fast response requirement. This paper provides a solution for impedance mismatch problems associated with such types of power supply, and also presents specifications for major components in a high voltage pulse power system for various types of load ranges. An experimental test hardware was designed and developed for HVHPPS to implement dynamic impedance algorithm and validate the results.

Set-based fast gradient projection algorithm for model predictive control of grid-tied power converters

Model Predictive Control (MPC) has attracted much attention and is widely used in power electronics. However, implementing the MPC algorithm is still a difficult task due to the fast dynamics of power converters and strict time constraints. In this paper, a computationally efficient MPC algorithm for grid-tied power converters based on the fast gradient projection method and invariant set theory is proposed. The algorithm is implemented and tested through hardware-in-the-loop simulations using Texas Instruments digital signal processors and Xilinx Field Programmable Gate Arrays platforms.

Secure image encryption using high throughput architectures of PRINT cipher for radio frequency identification applications

With the enhancement of technology, data security has become incredibly significant. Nowadays, images and vital information are used in real-time, and high throughput architecture is required for internet of things and real-time applications. We mainly focus on the high throughput architecture of PRINT cipher. PRINT cipher is a lightweight block cipher with a block size of 48-bit and 96-bit. Loop-unrolled, 48-bit pipelined, and 96-bit pipelined architectures are designed and implemented on different field programmable gate array and application-specific integrated circuit platforms. The maximum operating frequency obtained for 48-bit pipelined is 259.67 MHz on Virtex-4 and 310.67 MHz for 96-bit pipelined on Virtex-5. Finally, with the help of a controller, 48-bit high throughput pipelined architecture was utilized for image encryption of both grayscale and color images. The security analysis of encrypted images for color and grayscale images using PRINT cipher shows better performance and more robust protection against statistical, entropy, and differential attacks.

A Low-Cost Control Architecture for Buck Converter Fed VSI Based BLDC Motor Drive

In this paper, a novel low-cost digital controller to drive a buck converter fed voltage source inverter (VSI) based brushless DC (BLDC) machine has been proposed. This controller is designed to be implemented solely in digital platforms and has multiple numbers of predefined discrete duty ratios. In conjunction with buck converter fed VSI, the controller is beneficial to enhance the speed and resultant torque profile of BLDC motor drive as compared to conventional bang-bang or on-off controller. The controller also incorporates a current limiter to avoid the over-current loading of the motor. The sampling time and the design of the current limiter are mathematically derived in the paper. The working efficiency of the developed controller for the BLDC motor drive has been examined for various vital and steady-state conditions. The speed ripples, settling time, tolerance to the commanded speed, and load variations are validated and presented in this paper. The proposed controller has been performed and implemented in the field-programmable gate array platform and compared to generic pre-existing controllers to validate the cost-effectiveness of the controller.

Functional emulator designs for a memristor model with programmable analog and digital platforms

Hardware validation and verification studies for emulator circuits of the memristor element usually include either analog or digital realization results. In this study, the implementation stages of a memristor element using the Joglekar window function with programmable and reconfigurable analog and digital platforms are given together in order to observe the characteristic current–voltage relationship, experimentally. Herein, a Joglekar window function-based voltage-controlled memristor has been implemented with the field-programmable analog array (FPAA) platform for the first time. In fact, the FPAA platform has attracted attention thanks to its analog nature, rapid prototyping and low hardware cost specialties, and because different nonlinear functions can be easily constructed on this device. Similarly, the field-programmable gate array (FPGA) platform has recently been recognized for its parallel processing feature in digital signal processing studies. The FPGA-based digital implementation stages of the Joglekar window function-based memristor element are also addressed in this study. Thus, the FPAA and FPGA based memristor emulator designs are presented together in order to contribute the memristor-based analog and digital applications that is required to obtain real-time signals.

Multiplierless MP-Kernel Machine for Energy-Efficient Edge Devices

We present a novel framework for designing multiplierless kernel machines that can be used on resource-constrained platforms such as intelligent edge devices. The framework uses a piecewise linear (PWL) approximation based on a margin propagation (MP) technique and uses only addition/subtraction, shift, comparison, and register underflow/overflow operations. We propose a hardware-friendly MP-based inference and online training algorithm that has been optimized for a field-programmable gate array (FPGA) platform. Our FPGA implementation eliminates the need for digital signal processor (DSP) units and reduces the number of Look-Up Tables (LUTs). By reusing the same hardware for inference and training, we show that the platform can overcome classification errors and local minima artifacts that result from MP approximation. The implementation of this proposed multiplierless MP-kernel machine on FPGA results in an estimated energy consumption of 13.4 pJ and power consumption of 107 mW with ~9 k LUTs and Flip Flops (FFs) each for a 256 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\times $ </tex-math></inline-formula> 32 sized kernel making it superior in terms of power, performance, and area compared with other comparable implementations.

Real-time post-processing for physical-layer secure key distribution in fiber networks

Physical-layer secure key distribution (PLSKD) in fiber networks provides robust security and full compatibility with current fiber infrastructure. The post-processing is generally required to improve the key consistency, security, and randomness in PLSKD. However, offline digital signal processing was generally adopted in the previous PLSKD schemes, while the real-time high-speed post-processing is necessary towards the practical PLSKD applications. In this paper, a real-time pipeline post-processing is designed and demonstrated using field-programmable gate array (FPGA) boards. A complete set of post-processing is applied, including double-threshold quantization, information reconciliation (IR) with Bose–Chaudhuri–Hocquenghem code, and privacy amplification (PA) with SM3 hash algorithm. The system architecture is detailed by combining all these processing steps, where the trade-offs for the post-processing scheme are analyzed. We also assess the performance of post-processing implementation on FPGA in terms of throughput and hardware resource utilization. The throughput of post-processing is optimized by pipeline design approach with the parallel processing capability of FPGA, where the maximum data throughputs are 50, 57.1, and 332.5 Mb/s for the quantization, IR, and PA, respectively. On the FPGA platform, the final key rate is up to 12.2 Mb/s. The proposed real-time post-processing FPGA prototype is a good candidate for the practical application of PLSKD in fiber networks.

Improved MPPT System Based on FTSMC for Thermoelectric Generator Array Under Dynamic Temperature and Impedance

The thermoelectric generator (TEG) is typically used as a clean power supply to harvest waste heat energy in applications involving a large thermal gradient, such as industrial heat removal and power electronic equipment systems. However, it is often difficult to achieve the optimal output power in the loop of the array system of the TEG owing to different output loads. This article proposes an improved fast terminal sliding-mode variable-structure control algorithm (FTSMC) to maximize power point tracking. The variable-structure sliding-mode control function used in the nonlinear sliding-mode surface of the algorithm allows us to obtain the characteristics of global stability that can enable it to converge to the sliding-mode surface at any position to reduce chatter. Digital modeling and simulation as well as experimental developmental field programmable gate array platforms were built to verify the effectiveness of the proposed FTSMC. It can attain the nonlinear sliding mode more quickly than the traditional sliding-mode algorithm. The results of experiments show that it can reach a tracking response speed of 0.08 s and a maximum conversion efficiency of 99.91%. The work here provides a new way for the efficient use of the TEG array for waste heat recovery.

Field programmable gate array implementation of multiwavelet transform based orthogonal frequency division multiplexing system

This article offers an efficient design and implementation of a discrete multiwavelet critical-sampling transform based orthogonal frequency division multiplexing (DMWCST-OFDM) transceiver using field programmable gate array (FPGA) platform. The design uses 16-point discrete multiwavelet critical-sampling transform (DMWCST) and its inverse as main processing modules. All modules were designed using a part of Vivado&lt;sup&gt;®&lt;/sup&gt; Design Suite version (2015.2), which is Xilinx system generator (XSG), and is compatible with MATLAB Simulink version R2013b. The FPGA implementation is carried out on a Zynq (XC7Z020-1CLG484) evaluation board with joint test action group (JTAG) hardware co-simulation. According to the results obtained from the implementation tools, the implemented system is efficient in terms of resource utilization and could support the real-time operations.

Power Amplifier Linearization in the Presence of Crosstalk and Measurement Noise in MIMO System

The crosstalk and transceiver noise is an intrinsic part of the multiple-input and multiple-output (MIMO) System, becoming more prominent in low-cost systems. Moreover, the power amplifiers (PAs) cause nonlinearity, propagating to the complete chain. The conventional techniques do not provide the joint method for crosstalk, transceiver noise, and PA nonlinearity. This results in the performance limitation of the digital predistortion (DPD). Hence we propose a wavelet multiscale principal component analysis (PCA) based technique to deal with such problems (crosstalk, transceiver noise, and system nonlinearities). It is reported using measurement and simulation that numerical stability issue is no longer an issue when wavelet multiscale PCA-based DPD is applied. The effect of wavelet multiscale PCA on bit-resolution of DPD is shown to be better than established DPD Models. On a field-programmable gate array and direct conversion transceiver-based platform, the performance of the proposed model is analyzed using PA. Parameters like normalized mean square error have shown an improvement of around 23 dB and adjacent channel error power ratio has shown an improvement of around 22 dBc for a ZX60-V63+ power amplifier using LTE-OFDM signals.

Efficient FPGA Parallelization of Lipschitz Interpolation for Real-Time Decision-Making

One of the main open challenges in the field of learning-based control is the design of computing architectures able to process data in an efficient way. This is of particular importance when time constraints must be met, as, for instance, in real-time decision-making systems operating at high frequencies or when a vast amount of data must be processed. In this respect, field-programmable gate array (FPGA)-based parallel processing architectures have been hailed as a potential solution to this problem. In this article, a low-level design methodology for the implementation on FPGA platforms of Lipschitz interpolation (LI) algorithms is presented. The proposed design procedure exploits the potential parallelism of the LI algorithm and allows the user to optimize the area and energy resources of the resulting implementation. Besides, the proposed design allows to know in advance a tight bound of the error committed by the FPGA due to the representation format. Therefore, the resulting implementation is a highly parallelized and a fast architecture with an optimal use of the resources and consumption and with a fixed numerical error bound. These facts flawlessly suit the desirable specifications of learning-based control devices. As an illustrative case study, the proposed algorithm and architecture have been used to learn a nonlinear model predictive control law applied to self-balance a two-wheel robot. The results show how computational times are several orders of magnitude reduced by employing the proposed parallel architecture, rather than sequentially running the algorithm on an embedded ARM-CPU-based platform.

A More Accurate and Robust Binary Ring-LWE Decryption Scheme and Its Hardware Implementation for IoT Devices

Learning with error (LWE) over the ring based on binary distribution (ring-BinLWE) has become a potential Internet-of-Things (IoT) confidentiality solution with its anti-quantum attack properties and uncomplicated calculations. Compared with ring-LWE based on discrete Gaussian distribution, the decryption scheme of ring-LWE based on binary distribution needs to be re- determined due to the asymmetry of the error distribution. The direct application of the ring-LWE decryption function based on discrete Gaussian distribution can cause serious misjudgment. In this article, we propose a more accurate and robust decryption scheme for ring-BinLWE based on 2’s complement ring. Compared with the previous decryption function, the re- derived decryption function significantly improves the decoding rate by 50%. Furthermore, based on the proposed decryption function, high-performance, and lightweight hardware architectures for terminal devices in IoT are, respectively, proposed, which are scalable and can be easily adapted to ring-BinLWE hardware deployment with other parameter sets. When the parameter set is <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$n\,\,=$ </tex-math></inline-formula> 256, <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$q\,\,=$ </tex-math></inline-formula> 256, the high-performance implementation consumes 7.6k LUTs, 6.2k FFs, and 2.3k SLICEs on Spartan 6 field-programmable gate array (FPGA) platform. Compared with the previous implementation, our resource overhead increases by only 23% while the decryption accuracy is significantly improved by 50%. The lightweight implementation for parameter set <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$n\,\,=$ </tex-math></inline-formula> 256, <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$q\,\,=$ </tex-math></inline-formula> 256 consumes only 230 LUTs, 338 FFs, and 84 SLICEs on the Spartan 6 FPGA platform. Compared with the previous work, the area <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\times $ </tex-math></inline-formula> time (AT) is reduced by 47.8%, which is more suitable for deployment on resource-constrained IoT nodes.

A Highly Unified Reconfigurable Multicore Architecture to Speed Up NTT/INTT for Homomorphic Polynomial Multiplication

The ring learning with error (RLWE)-based fully homomorphic encryption (FHE) scheme has become one of the most promising FHE schemes. However, its performance is limited by the homomorphic multiplication, especially the polynomial multiplication which occupies major computing resources. Therefore, efficient implementation of polynomial multiplication is crucial for high-performance FHE applications. In this article, we present an area-efficient and highly unified reconfigurable multicore number theoretic transform (NTT)/inverse NTT (INTT) architecture (named MCNA), which employs NTT and INTT for polynomial multiplier with a variable number of reconfigurable processing elements. To reduce latency, MCNA merges the preprocessing and postprocessing into the constant-geometry NTT and INTT, respectively. Also, a reconfigurable modular multiplier based on digital signal processor (DSP) is proposed to speed up the modular multiplication. In order to avoid designing independent memory access pattern for INTT, a unified read/write structure of NTT/INTT is presented. Furthermore, a novel memory access pattern named “cyclic-sharing” is proposed to reduce 25% memory capacity. MCNA is evaluated on a Xilinx Virtex-7 field-programmable gate array (FPGA) platform. Running at 250-MHz clock frequency, the throughput of MCNA for NTT/INTT achieves <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$2.78\times \sim 9.32\times $ </tex-math></inline-formula> improvements in comparison to prior works, while the area efficiency of lookup table (LUT) and flip-flop (FF) is improved by <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$1.25\times \sim 4.79\times $ </tex-math></inline-formula> . For polynomial multiplication, the throughput of MCNA achieves <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$3.73\times \sim 7.69\times $ </tex-math></inline-formula> enhancements, as well as <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$1.13\times \sim 14.8\times $ </tex-math></inline-formula> area efficiency improvements.

FPGA-Based High-Throughput CNN Hardware Accelerator With High Computing Resource Utilization Ratio.

The field-programmable gate array (FPGA)-based CNN hardware accelerator adopting single-computing-engine (CE) architecture or multi-CE architecture has attracted great attention in recent years. The actual throughput of the accelerator is also getting higher and higher but is still far below the theoretical throughput due to the inefficient computing resource mapping mechanism and data supply problem, and so on. To solve these problems, a novel composite hardware CNN accelerator architecture is proposed in this article. To perform the convolution layer (CL) efficiently, a novel multiCE architecture based on a row-level pipelined streaming strategy is proposed. For each CE, an optimized mapping mechanism is proposed to improve its computing resource utilization ratio and an efficient data system with continuous data supply is designed to avoid the idle state of the CE. Besides, to relieve the off-chip bandwidth stress, a weight data allocation strategy is proposed. To perform the fully connected layer (FCL), a single-CE architecture based on a batch-based computing method is proposed. Based on these design methods and strategies, visual geometry group network-16 (VGG-16) and ResNet-101 are both implemented on the XC7VX980T FPGA platform. The VGG-16 accelerator consumed 3395 multipliers and got the throughput of 1 TOPS at 150 MHz, that is, about 98.15% of the theoretical throughput ( 2 ×3395 ×150 MOPS). Similarly, the ResNet-101 accelerator achieved 600 GOPS at 100 MHz, about 96.12% of the theoretical throughput ( 2 ×3121 ×100 MOPS).

An Optimization on the Neuronal Networks Based on the ADEX Biological Model in Terms of LUT-State Behaviors: Digital Design and Realization on FPGA Platforms.

Simple SummaryThe brain is an incredibly complex system possessing outstanding abilities to perform difficult tasks through a vast number of densely interconnected neurons. Aimed at discovering the underlying mechanisms of the brain, a number of spiking neural networks have been proposed to mimic biological neural dynamics. Subsequently, to perceive how the neural networks in the brain work, simulation and hardware realization of large-scale systems, similar to the brain, is an essential requirement. Behavior of a single neuron can be described by the mathematical equations in different levels of computing and biological accuracy. In this approach, a new modified ADEX model is presented based on sampling frequency by the nonlinear functions of the original model. This new model is capable for reproducing all aspects of the original model in low-error and high-degree of similarity conditions. Finally, the proposed model can be implemented on digital hardware platforms to have a real digital system. Digital results show the increase in system speed (frequency) and overall saving in hardware resources (compared by the original model and other similar works). This low-cost digital hardware is applied in large-scale neuronal networks.Design and implementation of biological neural networks is a vital research field in the neuromorphic engineering. This paper presents LUT-based modeling of the Adaptive Exponential integrate-and-fire (ADEX) model using Nyquist frequency method. In this approach, a continuous term is converted to a discrete term by sampling factor. This new modeling is called N-LUT-ADEX (Nyquist-Look Up Table-ADEX) and is based on accurate sampling of the original ADEX model. Since in this modeling, the high-accuracy matching is achieved, it can exactly reproduce the spiking patterns, which have the same behaviors of the original neuron model. To confirm the N-LUT-ADEX neuron, the proposed model is realized on Virtex-II Field-Programmable Gate Array (FPGA) board for validating the final hardware. Hardware implementation results show the high degree of similarity between the proposed and original models. Furthermore, low-cost and high-speed attributes of our proposed neuron model will be validated. Indeed, the proposed model is capable of reproducing the spiking patterns in terms of low overhead costs and higher frequencies in comparison with the original one. The properties of the proposed model cause can make it a suitable choice for neuromorphic network implementations with reduced-cost attributes.

Design and Acceleration of Field Programmable Gate Array-Based Deep Learning for Empty-Dish Recycling Robots

As the proportion of the working population decreases worldwide, robots with artificial intelligence have been a good choice to help humans. At the same time, field programmable gate array (FPGA) is generally used on edge devices including robots, and it greatly accelerates the inference process of deep learning tasks, including object detection tasks. In this paper, we build a unique object detection dataset of 16 common kinds of dishes and use this dataset for training a YOLOv3 object detection model. Then, we propose a formalized process of deploying a YOLOv3 model on the FPGA platform, which consists of training and pruning the model on a software platform, and deploying the pruned model on a hardware platform (such as FPGA) through Vitis AI. According to the experimental results, we successfully realize acceleration of the dish detection using a YOLOv3 model based on FPGA. By applying different sparse training and pruning methods, we test the pruned model in 18 different situations on the ZCU102 evaluation board. In order to improve detection speed as much as possible while ensuring detection accuracy, for the pruned model with the highest comprehensive performance, compared to the original model, the comparison results are as follows: the model size is reduced from 62 MB to 12 MB, which is only 19% of the origin; the number of parameters is reduced from 61,657,117 to 9,900,539, which is only 16% of the origin; the running time is reduced from 14.411 s to 6.828 s, which is only less than half of the origin, while the detection accuracy is decreased from 97% to 94.1%, which is only less than 3%.

Designing Deep Learning Hardware Accelerator and Efficiency Evaluation.

With the swift development of deep learning applications, the convolutional neural network (CNN) has brought a tremendous challenge to traditional processors to fulfil computing requirements. It is urgent to embrace new strategies to improve efficiency and diminish energy consumption. Currently, diverse accelerator strategies for CNN computation based on the field-programmable gate array (FPGA) platform have been gradually explored because they have edges of high parallelism, low power consumption, and better programmability. This paper first illustrates state-of-the-art FPGA-based accelerator design by emphasizing the contributions and limitations of existing research works. Subsequently, we demonstrated significant concepts of parallel computing (PC) in the convolution algorithm and discussed how to accomplish parallelism based on the FPGA hardware structure. Eventually, with the proposed CPU+ FPGA framework, we performed experiments and compared the performance against traditional computation strategies in terms of the operation efficiency and energy consumption ratio. The results revealed that the efficiency of the FPGA platform is much higher than that of the central processing unit and graphics processing unit.

Time-Resolved Determination Of Velocity Fields On The Example Of A Simple Water Channel Flow, Using A Real-Time Capable FPGA-Based Camera Platform

Field Programmable Gate Arrays (FPGAs) have become a widely available computational resource for real-time image processing and can be used in time-critical optical process measurements. This study investigates the applicability of the spatial filtering technique for time-resolved velocity field determination, on the example of a simple water channel flow. Therefore, the spatial filtering technique was implemented for a custom FPGA platform and analyzed regarding the effect of spatial and temporal resolution on the accuracy of the results. It was possible to prove the algorithm as suitable for velocity field estimation and identify algorithm parameters, which allow increasing the accuracy of the results.