Field Programmable Gate Array Technology Research Articles

Didactic Platform for Image Processing Experiments based on Digital Design

This paper presents the development of an educational platform, which can be used for Image Processing Experiments using Field Programmable Gate Arrays (FPGAs). This project aims to the development of a real embedded system by means of a set of phases of modular development and their subsequent integration into a single system, the proposal is intended for use in a semester-long course in order to give an overview of how the FPGA technology is integrated into a digital system, and expose the difficulties and challenges in the designing. The hardware description for each practice is driven in VHDL standard and implemented using an FPGA Spartan-3E-500k, embedded in a Nexys2 Kit, which represents a midrange and low-cost device. Some methodologies and hardware implementation details are presented. The system performs a comparison between MATLAB simulations and FPGA.

Design and Implementation of a MASH2-0 Electromechanical Sigma–Delta Modulator for Capacitive MEMS Sensors Using Dual Quantization Method

In this paper, a new control structure based on the dual quantization technique is presented for an electromechanical sigma–delta modulator (EM- $\Sigma \Delta \text{M}$ ) applied to a microelectromechanical system (MEMS) accelerometer. The modulator adopts a 2-0 multistage noise shaping structure (MASH2-0), taking the advantage of the intrinsic linearity of single-bit quantization and the reduced quantization error of multibit quantization in a single modulator. The sensor system is studied by the system-level modeling and the hardware implementation based on the field-programmable gate array technology. The study shows that, MASH2-0 shares the benefits of a MASH2-2 architecture of having an inherent stability, a high overload input level, and a high dynamic range compared with single-loop EM- $\Sigma \Delta \text{M}$ . However, the MASH2-0 architecture benefits from a considerably simpler implementation, while achieving a higher dynamic range and a higher signal-to-noise ratio compared with a MASH2-2 and a fourth-order single-loop $\Sigma \Delta \text{M}$ architecture. A capacitive MEMS accelerometer was designed and employed with this control system. Within a bandwidth of 1 kHz, the sensor achieved a noise floor level of −130 dB and a bias instability as low as $20~\mu \text{g}$ at an integration time of 40 s. Simulation estimated a full scale of ±20 g acceleration. The investigation confirms the concept of the MASH2-0 structure and shows its potential as a closed-loop interface for high-performance capacitive MEMS accelerometers. [2015-0071]

Real-time abnormal cell detection using a deformable snake model

Abnormal cell detection by optical microscopy is widely used, and a large number of biopsies required where the process of determining cell’s position in the histological sample image are very time consuming. In this paper, a proof-of-concept study was done to segmented abnormal cells in real time with high performance metrics focusing on minimizing cost and maximizing efficiency. We developed an improved snake/active contour method for fast cancer cells detection by integrated Canny approach. The implementation of this algorithm on Field-Programmable Gate Array (FPGA) technology substantially decreases the required time for identifying abnormal cells. It also allows an efficient and fast computation of active contour in high throughput image analysis applications where time performance is critical. In order to demonstrate the feasibility of this approach, we implemented the architecture on Xilinx Virtex-FPGAs technology which offers for a scalable and a totally embedded on Chip FPGA. The proposed architecture was validated using 30 images from each histopathological type of colon cells, namely, Benign Hyperplasia (BH), Intraepithelial Neoplasia (IN) and Carcinoma (Ca). This method successfully detected the different cell types with computation time in the order of milliseconds. It was compared with manual cells segmented by using the performance metrics of similarity. The experimental results showed that the proposed snake implementation on FPGA produced accurate and stable results. It was able to rapidly identify multiple cellular types from optical microscope images, and effectively addressed difficult problems such as irregular shapes in carcinoma cells. The short computation time in this method makes it applicable to real-time cancer cell detection.

The Real-Time, High Precision Phase Difference Measurement of Electron Density in HL-2A Tokamak**supported by National Natural Science Foundation of China (Nos. 11375195, 11075048) and the National Magnetic Confinement Fusion Science Program of China (No. 2013GB104003)

This paper introduces a real-time high precision measurement of phase difference based on Field Programmable Gate Array (FPGA) technology, which has been successfully applied to laser grating interference measurement and real-time feedback of plasma electron density in HL-2A tokamak. It can track the changes of electron density while setting the starting point of the density curve to zero. In a laboratory test, the measuring accuracy of phase difference is less than 0.1°, the time resolution is 80 ns, and the feedback delay is 180 μs.

Modular design and implementation of field-programmable-gate-array-based Gaussian noise generator

ABSTRACTThe modular design of a Gaussian noise generator (GNG) based on field-programmable gate array (FPGA) technology was studied. A new range reduction architecture was included in a series of elementary function evaluation modules and was integrated into the GNG system. The approximation and quantisation errors for the square root module with a first polynomial approximation were high; therefore, we used the central limit theorem (CLT) to improve the noise quality. This resulted in an output rate of one sample per clock cycle. We subsequently applied Newton's method for the square root module, thus eliminating the need for the use of the CLT because applying the CLT resulted in an output rate of two samples per clock cycle (>200 million samples per second). Two statistical tests confirmed that our GNG is of high quality. Furthermore, the range reduction, which is used to solve a limited interval of the function approximation algorithms of the System Generator platform using Xilinx FPGAs, appeared to have a higher numerical accuracy, was operated at >350 MHz, and can be suitably applied for any function evaluation.

Advanced Features and Industrial Applications of FPGAs—A Review

Field programmable gate arrays (FPGAs) have established themselves as one of the preferred digital implementation platforms in a plethora of current industrial applications, and extensions and improvements are still continuously being included in the devices. This paper reviews recent advancements in FPGA technology, emphasizing the novel features that may significantly contribute to the development of more efficient digital systems for industrial applications. Special attention is paid to the design paradigm shift caused by the availability of increasingly powerful embedded (and soft) processors, which transformed FPGAs from hardware accelerators to very powerful system-on-chip (SoC) platforms. New analog resources, floating-point operators, and hard memory controllers are also described, because of the great advantages they provide to designers. Software tools are being strongly influenced by the design paradigm shift, which requires from them a much better support for software developers. Focusing mainly on this issue, recent advancements in software resources [intellectual property (IP) cores and design tools] are also reviewed. The impact of new FPGA features in industrial applications is analyzed in detail in three main areas, namely digital real-time simulation, advanced control techniques, and electronic instrumentation, with focus on mechatronics, robotics, and power systems design. The way digital systems are being currently designed in these areas is comprehensively reviewed, and a critical analysis of how they could significantly benefit from new FPGA features is presented.

Comparative study of LDPC coding schemes and FPGA implementation for inter‐vehicle communications

A novel comparative study of different low-density parity-check (LDPC) coding algorithms and implementation issues through field-programmable gate arrays (FPGAs) technology for wireless vehicular applications is presented. A key development in LDPC codes is the iterative decoding algorithm which uses the belief propagation algorithm. A comprehensive investigation of the performance of different coding schemes was carried out. Four different decoding techniques were tested by computer-based simulations of messages modulated under the binary phase-shift keying modulation scheme and transmitted through a vehicular channel model. Finally, the best performance ratio against complexity algorithm was chosen to be implemented on a Xilinx FPGA platform.

Multiplicative finite impulse response filters: implementations and applications using field programmable gate arrays

This paper describes how modern field programmable gate array (FPGA) technology can be used to build practical and efficient multiplicative finite impulse response (MFIR) filters with low-pass, high-pass, band-pass and band-stop characteristics. This paper explains how MFIR structures can be built with or without linear phase characteristics and implemented efficiently on modern FPGA architectures using fixed-point arithmetic without incurring stability problems or limit cycles which commonly occur when using equivalent infinite impulse response structures. These properties have a particular importance for applications such as tunable resonators, narrow band rejectors and linear phase filters which have demanding, narrow transition band requirements. The results presented in this paper indicate that MFIR filters are, for some applications, a viable alternative to existing filter structures when implemented on an FPGA.

A Review on Implementation of QAM on FPGA

Quadrature Amplitude Modulation (QAM) is used in both analog and digital communication. In this technique, both amplitude and phase varies of carrier wave with respect to digital data or information. It provides high data rate for transmission. QAM is used in many application like color television, Wi-Max, OFDM (Orthogonal Frequency Division Multiplexing), and in digital satellite communication system. FPGAs (Field Programmable Gate Arrays) provide magnificent platform for implementation of many type of algorithms. The FPGA technology has been playing a vital role in portable and mobile communication due to the feature of configurability in designing and Implementation. This paper represents the review of implementation and optimization techniques of QAM on different FPGA development boards.

System assessment of an FPGA-based RPS for ABWR nuclear power plant

The instrumentation and control (I&C) systems for the Lungmen nuclear power plant (LMNPP) are fully digitized based on microprocessor and software technology, and extensively utilize multiplexing networks. That is, undetectable software faults and common cause failures due to software errors may occur, and that will defeat the redundancy of a nuclear power plant (NPP). A diverse backup implementation for the digital I&C systems is an important means to defense against undetectable software faults.This paper presents system assessment of a quad-redundant reactor protection system (RPS) design for an Advanced Boiling Water Reactor (ABWR) by utilizing the field programmable gate array (FPGA) technology. The FPGA-based RPS has been assessed by using a full-scope engineering simulator for the LMNPP. Accident scenarios and abnormal conditions are inserted into the engineering simulator in order to activate the function of the FPGA-based RPS. In this study, conceptual design of the proposed quad-redundant FPGA-based RPS, including preliminary hardware architecture, software design and system assessment will be presented. The results demonstrate that the FPGA-based RPS system is a practical approach to implement a diverse backup for the digital I&C system of nuclear power plant applications.Also, the sensitivity study of probabilistic risk assessment (PRA) shows that RPS combined with ARI (Alternative Rod Insertion) contributes significant influence on the core damage frequency (CDF) calculation of LMNPP. The PRA sensitivity study is independent of the RPS technology.

Studies on the Necessity to Integrate the FPGA (Field Programmable Gate Array) Circuits in the Digital Electronics Lab Didactic Activity

The FPGA (Field Programmable Gate Array) circuits contain programmable logic components and are increasingly popular in implementing the applications for obtaining and processing signals. FPGA represents a modern development trend in digital electronics. The integration in the work with students of this trend is a difficult task, but also useful, because many students face problems when they must use a design environment. The application of FPGA technology can be useful to students either for the laboratory work on advanced topics, or for obtaining skills to use an industry standard design environment. The purpose of this paper is to conduct studies on the need to integrate the FPGA digital electronics trend in the laboratory didactic activity of the students. As case study, we present the design of a control circuit and its implementation in a FPGA, i.e. on a Basys2 board with Xilinx programming environment.

An Enhanced WLAN Security System With FPGA Implementation for Multimedia Applications

Maintaining a high level of data security with a low impact on system performance is more challenging in wireless multimedia applications. Protocols that are used for wireless local area network (WLAN) security are known to significantly degrade performance. In this paper, we propose an enhanced security system for a WLAN. Our new design aims to decrease the processing delay and increase both the speed and throughput of the system, thereby making it more efficient for multimedia applications. Our design is based on the idea of offloading computationally intensive encryption and authentication services to the end systems' CPUs. The security operations are performed by the hosts' central processor (which is usually a powerful processor) before delivering the data to a wireless card (which usually has a low-performance processor). By adopting this design, we show that both the delay and the jitter are significantly reduced. At the access point, we improve the performance of network processing hardware for real-time cryptographic processing by using a specialized processor implemented with field-programmable gate array technology. Furthermore, we use enhanced techniques to implement the Counter (CTR) Mode with Cipher Block Chaining Message Authentication Code Protocol (CCMP) and the CTR protocol. Our experiments show that it requires timing in the range of 20–40 $\mu\mbox{s}$ to perform data encryption and authentication on different end-host CPUs (e.g., Intel Core i5, i7, and AMD 6-Core) as compared with 10–50 ms when performed using the wireless card. Furthermore, when compared with the standard WiFi protected access II (WPA2), results show that our proposed security system improved the speed to up to 3.7 times.

New Digital Testing of Analogue Circuits

This paper presents a new parametric fault detection approach for analogue circuits based on the digital signature analysis. This approach has two main parts, an analogue test pattern generator (ATPG), and an analogue test response compactor (ATRC). The proper ATPG is designed to sweep the applying sinusoidal frequencies to match the frequency domain of the analogue circuit under test (ACUT). The output test response of the ACUT is acquired via the analogue-to-digital converter (ADC). The ATRC accumulates digital samples of the output response from the ADC to generate a digital signature that can characterize the situation of the ACUT. The signature comparison is achieved based on signature boundaries and the worst-case analysis. In addition, the signature curve for each component variations inthe ACUT is presented. It combines effective parameters of the transfer function of the ACUT with respect to the component variations. These parameters are the band-width and the passband transmission. In this paper, the hardware implementation is achieved using the field programmable gate array (FPGA) technology as the digital part and the analogue part that includes the data conversion. The digital test controller is designed to enable the proper control and synchronization of the analogue test cycle for stable digital signature generation. The presented testing approach is applied to the ACUT in the range of biomedical applications to validate it. Based on the presented hardware implementation, the signature curve for each component of the ACUT is derived for the ACUT judgment.

능동위상배열 레이더 적용을 위한 FPGA 기반 실시간 적응 빔 형성기 설계 및 구현

위상배열 레이더 시스템에서 간섭과 재밍을 제거하기 위하여 적응빔 형성 알고리즘이 폭넓게 사용되고 있다. 최근에 와서 FPGA 기술의 발전으로 적응빔 형성 알고리즘의 실시간 처리가 가능하게 되었다. 본 논문에서는 능동위상배열 레이더를 개발하기 위해 전단신호처리기에 적용한 적응빔 형성기의 FPGA 기반 실시간 구현방법을 제안하였다. 개방형 VPX 벡플레인을 통한 통신의 상용 FPGA 보드를 활용하여 콤팩트한 적응빔 형성기를 개발하였다. 이 적응빔 형성기는 역행렬을 구하기 위해 QR 분해와 역 치환을 포함한 수많은 고속의 복소 신호처리와 벡터 및 행렬 연산으로 구성하였다. 구현 결과, FPGA를 통한 적응빔 형성 결과와 매트랩을 통한 시뮬레이션 결과가 일치함을 보였다. 또한, FPGA를 통한 적응빔 형성 알고리즘의 실시간 처리가 가능하여 능동위상배열 레이더 시스템에 적용 가능함을 확인하였다. Adaptive beamforming algorithms have been widely used to remove interference and jamming in the phased array radar system. Advances in the field programmable gate array(FPGA) technology now make possible the real time processing of adaptive beamforming (ABF) algorithm. In this paper, the FPGA based real-time implementation method of adaptive beamforming system(beamformer) in the pre-processor module for active electronically scanned array(AESA) radar is proposed. A compact FPGA-based adaptive beamformer is developed using commercial off the shelf(COTS) FPGA board with communication via OpenVPX(Virtual Path Cross-connect) backplane. This beamformer comprises a number of high speed complex processing including QR decomposition & back substitution for matrix inversion and complex vector/matrix calculations. The implemented result shows that the adaptive beamforming patterns through FPGA correspond with results of simulation through Matlab. And also confirms the possibility of application in AESA radar due to the real time processing of ABF algorithm through FPGA.

Development of gamma spectroscopy employing NaI(Tl) detector 3 inch × 3 inch and readout electronic of flash-ADC/FPGA-based technology

Abstract In this article the development of a gamma spectroscopy system is described using a scintillation detector NaI(Tl) of 3 inch × 3 inch. The readout electronic for the spectroscopy is built from the fast analog-digital conversion of Flash Analog-Digital Converter (Flash-ADC) 250 MHz – 8 bits resolution, and the embedded Field-Programmable Gate Array (FPGA) technology. The embedded VHSIC Hardware Description Language (VHDL) code for FPGA is built in such a way that it works as a multi channel analyser (MCA) with 4096 Digital Charge Integration (DCI) channels. A pulse generator with frequency varying from Hz up to 12 kHz is used to evaluate the time response of the system. Two standard radioisotope sources of 133Ba and 152Eu with multi gamma energies ranging from several tens keV to MeV are used to evaluate the linearity and energy resolution of the system.

An ultra-low cost NMR device with arbitrary pulse programming

Ultra-low cost, general purpose electronics boards featuring microprocessors or field programmable gate arrays (FPGA) are reaching capabilities sufficient for direct implementation of NMR spectrometers. We demonstrate a spectrometer based on such a board, implemented with a minimal need for the addition of custom electronics and external components. This feature allows such a spectrometer to be readily implemented using typical knowledge present in an NMR laboratory. With FPGA technology, digital tasks are performed with precise timing, without the limitation of predetermined hardware function. In this case, the FPGA is used for programming of arbitrarily timed pulse sequence events, and to digitally generate required frequencies. Data acquired from a 0.53T permanent magnet serves as a demonstration of the flexibility of pulse programming for diverse experiments. Pulse sequences applied include a spin–lattice relaxation measurement using a pulse train with small-flip angle pulses, and a Carr–Purcell–Meiboom–Gill experiment with phase cycle. Mixing of NMR signals with a digitally generated, 4-step phase-cycled reference frequency is further implemented to achieve sequential quadrature detection. The flexibility in hardware implementation permits tailoring this type of spectrometer for applications such as relaxometry, polarimetry, diffusometry or NMR based magnetometry.

RIO EPICS device support application case study on an ion source control system (ISHP)

Experimental Physics and Industrial Control System (EPICS) is a software tool that during last years has become relevant as a main framework to deploy distributed control systems in large scientific environments. At the moment, ESS Bilbao uses this middleware to perform the control of their Ion Source Hydrogen Positive (ISHP) project. The implementation of the control system was based on: PXI Real Time controllers using the LabVIEW-RT and LabVIEW-EPICS tools; and RIO devices based on Field-Programmable Gate Array (FPGA) technology. Intended to provide a full compliant EPICS IOCs for RIO devices and to avoid additional efforts on the system maintainability, a migration of the current system to a derivative Red Hat Linux (CentOS) environment has been conducted. This paper presents a real application case study for using the NIRIO EPICS device support (NIRIO-EDS) to give support to the ISHP. Although RIO FPGA configurations are particular solutions for ISHP performance, the NIRIO-EDS has permitted the control and monitoring of devices by applying a well-defined design methodology into the previous FPGA configuration for RIO/FlexRIO devices. This methodology has permitted a fast and easy deployment for the new robust, scalable and maintainable software to support RIO devices into the ISHP control architecture.

The Control System Based on FPGA Technology For Fatigue Test Stand MZGS-100 PL

Abstract The paper presents a solution of the control system for fatigue test stand MZGS- -100 PL, comprising the integrated Real-Time controller based on FPGA (Field- Programmable Gate Array) technology with LabVIEW software. The described control system performs functions such as continuous regulation of speed induction motor, measuring strain of the lever machine and the test specimen, displacement of the polyharmonic vibrator, as well as the elimination of interferences, overload protection and emergency stop of the machine. The fatigue test stand also allows to set the pseudo-random history of energy parameter W(t).

Development of Power Interface With FPGA-Based Adaptive Control for PEM-FC System

This paper presents the development of a power interface for a fuel cell (FC) system supplying an ac load. The proposed system comprises a two stages conditioning system, including a switched capacitor dc-dc boost converter and a full bridge insulated-gate bipolar transistor (IGBT) single-phase inverter (dc-ac converter). A fully digital control structure is proposed to manage both power converters using the same control device. The control strategy takes advantage of the parallelism of the field programmable gate arrays (FPGA) technology to share in real-time the controller's information addressing the common problem of low-frequency ripple of FC current when supplying ac loads. The control system has been implemented and evaluated by co-simulation, and by experimentation with a proton exchange membrane fuel cell (PEM-FC) system. The results show that the proposed system allows a safe operation of the FC by limiting the current ripple under 3%. These results also confirm that the transient response of the conversion system permits to correctly supply the ac load.

Three Ages of FPGAs: A Retrospective on the First Thirty Years of FPGA Technology

Since their introduction, field programmable gate arrays (FPGAs) have grown in capacity by more than a factor of 10 $\thinspace$000 and in performance by a factor of 100. Cost and energy per operation have both decreased by more than a factor of 1000. These advances have been fueled by process technology scaling, but the FPGA story is much more complex than simple technology scaling. Quantitative effects of Moore's Law have driven qualitative changes in FPGA architecture, applications and tools. As a consequence, FPGAs have passed through several distinct phases of development. These phases, termed “Ages” in this paper, are The Age of Invention, The Age of Expansion and The Age of Accumulation. This paper summarizes each and discusses their driving pressures and fundamental characteristics. The paper concludes with a vision of the upcoming Age of FPGAs.