Field Programmable Gate Array Technology Research Articles

An Energy-Efficient Field-Programmable Gate Array Rapid Implementation of a Structural Health Monitoring System

System health monitoring (SHM) of a ball screw laboratory system using an embedded real-time platform based on Field-Programmable Gate Array (FPGA) technology was developed. The ball screw condition assessment algorithms based on machine learning approaches implemented on multiple platforms were compared and evaluated. Studies on electric power consumption during the processing of the proposed structure of a neural network, implementing SHM, were carried out for three hardware platforms: computer, Raspberry Pi 4B, and Kria KV260. It was found that the average electrical power consumed during calculations is the lowest for the Kria platform using the FPGA system. However, the best ratio of the average power consumption to the accuracy of the neural network was obtained for the Raspberry Pi 4B. The concept of an efficient and energy-saving hardware platform that enables monitoring and analysis of the operation of the selected dynamic system was proposed. It allows for easy integration of many software environments (e.g., MATLAB and Python) with the System-on-a-Chip (SoC) platform containing an FPGA and a CPU.

Performance Analysis of Approximate Parallel Prefix Adders Realized with Field-programmable Gate Array Technology

Introduction: Parallel prefix adders are widely used in high-speed arithmetic circuits due to their ability to perform additions in logarithmic time. However, the high area and delay of exact parallel prefix adders prompted the development of approximate parallel prefix adders. These adders are a promising solution for high-speed arithmetic circuits because they sacrifice accuracy for reduced area and delay. Methods: This paper presents a performance analysis of five approximate parallel prefix adders realized with field programmable gate array technology. The five approximate parallel prefix adders are the Kogge-Stone adder, the Sklansky adder, the Brent-Kung adder, the Han-Carlson adder, and the Ladner-Fisher. Each adder is implemented in a Xilinx Artix-7 FPGA. The area and delay of five approximate parallel prefix adders are evaluated. The Kogge-Stone approximate parallel prefix adder, out of five approximate parallel prefix adders, consumes the least delay, irrespective of the number of bits. Results: The Sklansky approximate parallel prefix adder out of five approximate parallel prefix adders consumes the least area irrespective of the number of bits in addition. Overall, our research sheds light on the trade-offs between area, power delay, and power delay products of five approximate parallel prefix adders implemented with FPGA technology. Conclusion: This analysis can help choose the best approximate parallel prefix adder for specific high-speed arithmetic applications. In the case of 16- and 32-bit five approximate parallel prefix adders, Ladner-fisher shows the best power delay product, whereas 64- and 128-bit five approximate parallel prefix adders, Sklansky adder shows the best power delay product.

An Edge Computing System with AMD Xilinx FPGA AI Customer Platform for Advanced Driver Assistance System.

The convergence of edge computing systems with Field-Programmable Gate Array (FPGA) technology has shown considerable promise in enhancing real-time applications across various domains. This paper presents an innovative edge computing system design specifically tailored for pavement defect detection within the Advanced Driver-Assistance Systems (ADASs) domain. The system seamlessly integrates the AMD Xilinx AI platform into a customized circuit configuration, capitalizing on its capabilities. Utilizing cameras as input sensors to capture road scenes, the system employs a Deep Learning Processing Unit (DPU) to execute the YOLOv3 model, enabling the identification of three distinct types of pavement defects with high accuracy and efficiency. Following defect detection, the system efficiently transmits detailed information about the type and location of detected defects via the Controller Area Network (CAN) interface. This integration of FPGA-based edge computing not only enhances the speed and accuracy of defect detection, but also facilitates real-time communication between the vehicle's onboard controller and external systems. Moreover, the successful integration of the proposed system transforms ADAS into a sophisticated edge computing device, empowering the vehicle's onboard controller to make informed decisions in real time. These decisions are aimed at enhancing the overall driving experience by improving safety and performance metrics. The synergy between edge computing and FPGA technology not only advances ADAS capabilities, but also paves the way for future innovations in automotive safety and assistance systems.

Enhancing Regular Expression Processing through Field-Programmable Gate Array-Based Multi-Character Non-Deterministic Finite Automata

This work investigates the advantages of FPGA-based Multi-Character Non-Deterministic Finite Automata (MC-NFA) for enhancing regular expression processing over traditional software-based methods. By integrating Field-Programmable Gate Arrays (FPGAs) within a data processing framework, our study showcases significant improvements in processing efficiency, accuracy, and resource utilization for complex pattern matching tasks. We present a novel approach that not only accelerates database and network security applications, but also contributes to the evolving landscape of computational efficiency and hardware acceleration. The findings illustrate that FPGA’s coherent access to main memory and the efficient use of resources lead to considerable gains in processing times and throughput for handling regular expressions, unaffected by expression complexity and driven primarily by dataset size and match location. Our research further introduces a phase shift compensation technique that elevates match accuracy to optimal levels, highlighting FPGA’s potential for real-time, accurate data processing. The study confirms that the benefits of using FPGA for these tasks do not linearly correlate with an increase in resource consumption, underscoring the technology’s efficiency. This paper not only solidifies the case for adopting FPGA technology in complex data processing tasks, but also lays the groundwork for future explorations into optimizing hardware accelerators for broader applications.

Voltage Scaled Low Power DNN Accelerator Design on Reconfigurable Platform

The exponential emergence of Field-Programmable Gate Arrays (FPGAs) has accelerated research on hardware implementation of Deep Neural Networks (DNNs). Among all DNN processors, domain-specific architectures such as Google’s Tensor Processor Unit (TPU) have outperformed conventional GPUs (Graphics Processing Units) and CPUs (Central Processing Units). However, implementing low-power TPUs in reconfigurable hardware remains a challenge in this field. Voltage scaling, a popular approach for energy savings, can be challenging in FPGAs, as it may lead to timing failures if not implemented appropriately. This work presents an ultra-low-power FPGA implementation of a TPU for edge applications. We divide the systolic array of a TPU into different FPGA partitions based on the minimum slack value of different design paths of Multiplier Accumulators (MACs). Each partition uses different near-threshold (NTC) biasing voltages to run its FPGA cores. The biasing voltage for each partition is roughly calculated by the proposed static schemes. However, further calibration of biasing voltage is performed by the proposed runtime scheme. To overcome the timing failure caused by NTC, the MACs with higher minimum slack are placed in lower-voltage partitions, while the MACs with lower minimum slack paths are placed in higher-voltage partitions. The proposed architecture is implemented in a commercial platform, namely Vivado with Xilinx Artix-7 FPGA and academic platform VTR with 22 nm, 45 nm and 130 nm FPGAs. Any timing error caused by NTC can be caught by the Razor flipflop used in each MAC. The proposed voltage-scaled, partitioned systolic array can save 3.1% to 11.6% of dynamic power in Vivado and VTR tools, respectively, depending on the FPGA technology, partition size, number of partitions and biasing voltages. The normalized performance and accuracy of benchmark models running on our low-power TPU are very competitive compared to existing literature.

Remote field-programmable gate array laboratory for signal acquisition and design verification

A remote laboratory utilizing field-programmable gate array (FPGA) technologies enhances students’ learning experience anywhere and anytime in embedded system design. Existing remote laboratories prioritize hardware access and visual feedback for observing board behavior after programming, neglecting comprehensive debugging tools to resolve errors that require internal signal acquisition. This paper proposes a novel remote embedded-system design approach targeting FPGA technologies that are fully interactive via a web-based platform. Our solution provides FPGA board access and debugging capabilities beyond the visual feedback provided by existing remote laboratories. We implemented a lab module that allows users to seamlessly incorporate into their FPGA design. The module minimizes hardware resource utilization while enabling the acquisition of a large number of data samples from the signal during the experiments by adaptively compressing the signal prior to data transmission. The results demonstrate an average compression ratio of 2.90 across three benchmark signals, indicating efficient signal acquisition and effective debugging and analysis. This method allows users to acquire more data samples than conventional methods. The proposed lab allows students to remotely test and debug their designs, bridging the gap between theory and practice in embedded system design.

Analysis and prospects of automobile intelligent assisted driving characteristics based on FPGA technology

This article provides a comprehensive exploration of the pivotal role that field-programmable gate arrays (FPGAs) play in the advancement of autonomous driving technology. FPGAs, which made their debut in the early 1980s, have emerged as a crucial component in this field, owing to their robust parallel processing capabilities, real-time data analysis capabilities, and exceptional customizability. With the ever-increasing demand for autonomous driving solutions, the adoption of FPGAs has become indispensable in meeting the requirements for high-speed data processing and instantaneous response times. Within these pages, we delve into the significant role that FPGAs assume in elevating intelligent driving systems, offering a deep dive into this subject through meticulous case studies and technical insights. This article casts a spotlight on several compelling instances where FPGAs shine, notably in adaptive cruise systems, obstacle recognition, automatic emergency braking, and intelligent parking assistance, achieved through seamless integration with YOLO technology. These real-world examples serve to underscore the pivotal role that FPGAs play in ensuring road safety and propelling technological advancement in the realm of autonomous driving.

A comparative study of FPGA and CGRA technologies in hardware acceleration for deep learning

With the rapid growth of deep neural networks, their increasing demand for computing resources poses significant challenges to resource-constrained edge devices. Field Programmable Gate Array (FPGA) and Coarse-Grained Reconfigurable Arrays (CGRA) have emerged as promising solutions due to their parallelism and energy efficiency advantages. This paper conducts a comprehensive comparative analysis of FPGA and CGRA for accelerating deep learning workloads. It begins by introducing convolutional neural network architecture and optimization techniques. Various dataflow strategies are discussed for memory access optimization. The paper then analyzes representative cases to clarify FPGA and CGRA architectural advantages, along with optimization techniques through different dataflow strategies. The comparison reveals that FPGA offers higher throughput with fine-grained programmability for flexible bit-level operations and dataflow control. In contrast, CGRA excels in energy efficiency and area consumption with coarse-grained custom processing units and optimized on-chip interconnection networks. Quantitative comparisons are provided for throughput, energy efficiency, and area occupation. These insights can serve as a reference for selecting the appropriate architecture when designing custom hardware accelerators for deep learning workloads.

Real-Time Direction Judgment System for Dual-Frequency Laser Interferometer.

Current real-time direction judgment systems are inaccurate and insensitive, as well as limited by the sampling rate of analog-to-digital converters. To address this problem, we propose a dynamic real-time direction judgment system based on an integral dual-frequency laser interferometer and field-programmable gate array technology. The optoelectronic signals resulting from the introduction of a phase subdivision method based on the amplitude resolution of the laser interferometer when measuring displacement are analyzed. The proposed system integrates the optoelectronic signals to increase the accuracy of its direction judgments and ensures these direction judgments are made in real time by dynamically controlling the integration time. Several experiments were conducted to verify the performance of the proposed system. The results show that, compared with current real-time direction judgment systems, the proposed system makes accurate judgements during low-speed motions and can update directions within 0.125 cycles of the phase difference change at different speeds. Moreover, a sweep frequency experiment confirmed the system's ability to effectively judge dynamic directions. The proposed system is capable of accurate and real-time directional judgment during low-speed movements of a table in motion.

Development and Implementation of an FPGA-Embedded Multimedia Remote Monitoring System for Information Technology Server Room Management

Conventional data acquisition systems face challenges in achieving high acquisition speeds and rapid storage of large data volumes using microcontrollers. In contrast, field-programmable gate arrays (FPGAs) offer numerous advantages, including high clock frequencies, minimal internal delays, fast operational speeds, abundant internal RAM resources, and simplified control of complex peripheral circuits. This study presents the design of an FPGA-based multimedia remote monitoring system for information technology server rooms. The proposed system utilizes an FPGA as the primary controller and incorporates environmental sensors, electrical energy sensors, carbon monoxide sensors, smoke sensors, and A/D converter modules to monitor multiple locations within the server room. Simultaneously, the FPGA transmits the collected data from each monitoring point via a serial port to an LCD serial screen for display. An alarm is triggered if any environmental anomalies are detected, indicating abnormal statuses. Additionally, the system employs the fast Fourier transform algorithm and butterfly operations to derive voltage and current AC quantities, while utilizing relative temperature differences to identify equipment faults within the server room. The system is evaluated in terms of functionality, user-friendliness, and reliability. Experimental results demonstrate that all performance measures align with expectations, fulfilling the initial design objectives and highlighting the potential applicability and relevance of FPGA technology in the monitoring field. In addition, a comparison between FPGA and traditional microcontroller systems is performed, showcasing the superior processing speed and performance of the FPGA-based system. This comparative analysis further validates the advantages of using FPGA technology in high-speed data acquisition and monitoring applications.

On-board drone classification with Deep Learning and System-on-Chip implementation

In recent years the increasing use of drones has raised significant concerns on safety and make them dramatic threats to security. To address these worries Counter-UAS Systems (CUS) are capturing the interest of research and of industry. Consequently, the development of effective drone detection technologies has become a critical research focus. The proposed work explores the application of edge computing to drone classification. It tunes a Deep Learning model, You Only Look Once (YOLO), and implements it on a Field Programmable Gate Array (FPGA) technology. FPGAs are considered advantageous over conventional processors since they enable parallelism and can be used to create high-speed, low-power, and low-latency circuit designs and so to satisfy the stringent Size, weight and Power (SWaP) requirements of a drone-based implementation. In details, two different YOLO neural networks YOLO v3 and v8 are trained and evaluated on a large data set constructed with drones’ images at various distances. The two models are then implemented on a System-on-Chip (SoC). In order to demonstrate the feasibility of a drone on board image Artificial Intelligence processing, the evaluation assesses the accuracy of classification and the computational performances such as latency.

Implementation of a High-Sensitivity Global Navigation Satellite System Receiver on a System-on-Chip Field-Programmable Gate Array Platform.

This paper presents the design, proof-of-concept implementation, and preliminary performance assessment of an affordable real-time High-Sensitivity (HS) Global Navigation Satellite System (GNSS) receiver. Specifically tailored to capture and track weak Galileo E1b/c signals, this receiver aims to support research endeavors focused on advancing GNSS signal processing algorithms, particularly in scenarios characterized by pronounced signal attenuation. Leveraging System-on-Chip Field-Programmable Gate Array (SoC-FPGA) technology, this design merges the adaptability of Software Defined Radio (SDR) concepts with the the robust hardware processing capabilities of FPGAs. This innovative approach enhances power efficiency compared to conventional designs relying on general-purpose processors, thereby facilitating the development of embedded software-defined receivers. Within this architecture, we implemented a modular GNSS baseband processing engine, offering a versatile platform for the integration of novel algorithms. The proposed receiver undergoes testing with live signals, showcasing its capability to process GNSS signals even in challenging scenarios with a carrier-to-noise density ratio (C/N0) as low as 20 dB-Hz, while delivering navigation solutions. This work contributes to the advancement of low-cost, high-sensitivity GNSS receivers, providing a valuable tool for researchers engaged in the development, testing, and validation of experimental GNSS signal processing techniques.

Investigating the efficiency and performance gains of FPGA-accelerated Convolutional Neural Networks

With the rise of big data and artificial intelligence (AI), Convolutional Neural Networks (CNNs) have become instrumental in numerous applications, from image and speech recognition to natural language processing. However, these networks computational demands often exceed the capabilities of traditional processing units, leading to a search for more effective computing platforms. This research aims to evaluate the potential of Field-Programmable Gate Array (FPGA) technology in accelerating CNN computations, considering FPGAs unique attributes such as reprogrammability, energy efficiency, and custom logic potential. The primary aim of this research is to compare the efficiency and performance of FPGA acceleration of CNNs with conventional processing units like CPUs and GPUs and to explore its potential for future AI applications. This research employs a mixed-methods approach, including an integrated literature review and comparative analysis. This paper reviews state-of-the-art research on FPGA-accelerated CNNs, benchmark performance metrics of FPGA, CPU, and GPU platforms across various CNN models, and compare FPGA-based AI applications with other real-world AI applications. The findings suggest a significant potential for FPGA-accelerated CNNs, particularly in scenarios requiring real-time computation or power-limited environments. However, challenges persist in the areas of development complexity and limited on-chip memory. Future work must focus on surmounting these barriers to unlock the full potential of FPGA-accelerated CNNs.

An FPGA‐based tool for supporting the design, modeling, and evaluation of hybrid object recognition systems on computer engineering courses

AbstractThe field of computer vision is characterized by computationally intensive algorithms and techniques with strict real‐time requirements. Field programmable gate arrays (FPGAs) are based on a concurrent paradigm which allows the design of efficient hardware architectures and has positioned FPGAs as an ideal device for implementing compute‐intensive applications. For this reason, FPGA technology has had a great impact in areas such as computer vision, where one of the main objectives for researchers working in this field is to create efficient automatic object recognition systems. Therefore, the need to provide undergraduates with the necessary skills to design FPGA‐based object recognition systems is evident. With this aim in mind, it is essential that specialization courses related to the design of these systems include the required resources for the student to apply the theoretical knowledge in solving practical problems. In this article, we present a development tool designed to help students, teachers, and researchers during the design‐modeling‐implementation process of object recognition systems based on FPGAs. The proposed tool operates under a modular approach as this facilitates the working on any of the phases of a recognition system and it is considered as a hybrid because the other phases can be developed using a software language. An empirical evaluation involving undergraduates enrolled in a Computer Engineering program was conducted to create a hardware architecture for the DAISY descriptor that uses the homogeneous features of objects immersed in images to produce an efficient representation. By considering similar descriptors such as Scale‐Invariant Feature Transform (SIFT) and Histogram of Oriented Gradients (HOG), DAISY is computed by convolving orientation maps instead of using weighted sums of gradient norms, which offers the same kind of invariance at a lower computational cost for the dense case. The results obtained during such an evaluation indicated that students consider this FPGA‐based tool to be an alternative to receiving practical training on designing systems for solving problems related to the area of object recognition.

Development of embedded fuzzy control using reconfigurable FPGA technology

The purpose of this work is to investigate the construction of fuzzy embedded control systems combining fast execution and parallel processing capabilities provided by Field Programmable Gate Arrays (FPGAs) and Reconfigurable Inputs/Outputs (RIO) chips. A fixed-point fuzzy controller is developed and implemented on a fast mechatronic system with high-speed control and high channel count on an FPGA target. This paper provides a brief introduction to deploying Fuzzy Logic Control (FLC) methods using RIO-FPGA technology. It suggests a technique for implementing the three stages that constitute the FLC and the PD-like FLC and PID-like FLC structures into practice. Controllers with 1 and 2 degrees of freedom are developed and tested experimentally. Parallel loops, key challenging advantage of LabVIEW programming, are utilized for decoding feedback signals, generating pulse trains for actuator's drivers and for calculation of control gains. An NI-SbRIO board that combines deployable devices with a real-time processor, a re-configurable FPGA, and analogue and digital input–output ports is used. The experimental work demonstrates the significant enhancement of implementing reconfigurable embedded fuzzy control upon such mechatronic systems.

An improved CFAR algorithm for multiple environmental conditions

AbstractThe primary objective of radar digital signal processing is to detect and identify targets in complicated situations, such as those involving clutter or several closely positioned targets. The constant false alarm rate (CFAR) method is more effective for target recognition and has better control over the false alarm rate. Many studies have been conducted on the design of CFAR, but previous CFAR algorithms have not been effective in all or most environmental fields and target scenarios. In this study, an algorithm called Censored Mean Clutter Map CFAR (CM-CM CFAR) has been developed and tested for various environmental conditions. When compared to a fixed false alarm rate, the suggested CFAR algorithm’s Monte Carlo simulation results demonstrated a high detection probability in a variety of environments. This work designs a real-time CM-CM CFAR processor using field-programmable gate array (FPGA) technologies. Xilinx ARTIX 7 FPGA technology is used to develop and map a scalable parallel framework. Consequently, the implementation required 23,741 LUTs and 1825 FF. It is verified that the complexity and operating speed of the suggested CFAR processor are extremely appropriate for real-time implementation when compared to the results of the previously proposed FPGA implementation.

Hardware Acceleration for Object Detection using YOLOv5 Deep Learning Algorithm on Xilinx Zynq FPGA Platform

Object recognition presents considerable difficulties within the domain of computer vision. Field-Programmable Gate Arrays (FPGAs) offer a flexible hardware platform, having exceptional computing capabilities due to their adaptable topologies, enabling highly parallel, high-performance, and diverse operations that allow for customized reconfiguration of integrated circuits to enhance the effectiveness of object detection accelerators. However, there is a scarcity of assessments that offer a comprehensive analysis of FPGA-based object detection accelerators, and there is currently no comprehensive framework to enable object detection specifically tailored to the unique characteristics of FPGA technology. The You Only Look Once (YOLO) algorithm is an innovative method that combines speed and accuracy in object detection. This study implemented the YOLOv5 algorithm on a Xilinx® Zynq-7000 System on a Chip (SoC) to perform real-time object detection. Using the MS-COCO dataset, the proposed study showed an improvement in resource utilization with approximately 42 thousand (78%) look-up tables, 56 thousand (52%) flip-flops, 65 (46%) BRAMs, and 19 (9%) DSPs at a frequency of 250 MHz, improving the effectiveness compared to previous simulated results.

An FPGA-Based Adaptive Solution for Synchronous Configuration in UART Communication

To address the challenges associated with data reception failures, which arise due to abrupt alterations in the baud rate and the data format of the transmission signal in traditional Universal Asynchronous Receiver-Transmitter (UART) scenarios, this study presents an adaptive UART parameter solution underpinned by Field-Programmable Gate Array (FPGA) technology. Initially, this manuscript elucidates the underlying principles of UART communication and delineates the pivotal constituents of the UART protocol. Subsequently, it offers an in-depth analysis, from the transmission perspective, of how specific parameters influence the effectiveness of the UART protocol. Based on the software and hardware embodiments associated with the dual primary functions – baud rate adaptation and data format adaptation – this paper extensively details the flow chart for baud rate adaptation, the circuitry for edge detection, methodologies for baud rate computation, and the parameter eigenvalue approach. Following this, Verilog, a hardware description language, is employed for coding and subsequent simulation within the Quartus II environment. Empirical evidence corroborates the efficacy of the proposed design in achieving synchronous configuration between the baud rate and the data format. The findings of this research bear substantial implications for augmenting both the adaptability and dependability of UART communication systems.

Efficient lightweight cryptography for resource-constrained WSN nodes

In Wireless Sensor Networks (WSN), where resources are scarce, lightweight cryptography is crucial and difficult. The Constrained Application Protocol (CoAP), Field-Programmable Gate Array (FPGA) technology, and a modified RC5 algorithm are used in this study to achieve efficient encryption for WSN nodes. WSN are essential for monitoring temperature, humidity, vibrations, and seismic activity. However, processing capacity, memory, and energy constraints make data security difficult in these networks. CoAP, FPGA, and a modified RC5 algorithm provide security, computational load reduction, and energy efficiency in resource-limited WSN. This research is crucial because it creates cryptographic mechanisms that accommodate WSN unique needs. By protecting data integrity and confidentiality, these mechanisms ensure data transmission security and privacy. Data security and efficiency in WSN require innovative cryptographic, FPGA-based hardware acceleration, and protocol optimization solutions. These methods could improve these vital sensing networks. This research lays the foundation for protecting the accuracy and security of WSN node data collected and transmitted with limited resources while optimizing resource allocation.

Symmetry, Multistability and Antimonotonicity of a Shinriki Oscillator with Dual Memristors

In this paper, a type of modified dual memristive Shinriki oscillator is constructed with a flux-controlled absolute-type memristor and a voltage-controlled generic memristor, and the proposed oscillator with abundant dynamical behaviors, including the multistability and antimonotonicity, is comprehensively studied through dynamical distribution graphs, bifurcation diagrams, Lyapunov exponents and phase portraits. It is found that the passive/active state of memristor, which means different characteristics in the [Formula: see text]–[Formula: see text] domain with positive and negative parameters of the elements, can affect the state of the oscillator. For example, if the memristor is active, the oscillator will change more frequently in the multistable region. Also, it is noted that, for inherent initial-related symmetry and circuit structures with duality, both phenomena have strong symmetric characteristics and opposite evolution trends modulated by values of corresponding components. Especially, the bubbles, which are symmetric about parameters with duality and own complex evolution laws, have rarely been explored in previous works. In addition, the memristive oscillator is modularized based on field programmable gate array (FPGA) technology, and the multiple coexisting attractors are captured, which verifies the accuracy of the numerical results.