Field Programmable Gate Array System Research Articles

Optimization of Deep Neural Networks Using SoCs with OpenCL.

In the optimization of deep neural networks (DNNs) via evolutionary algorithms (EAs) and the implementation of the training necessary for the creation of the objective function, there is often a trade-off between efficiency and flexibility. Pure software solutions implemented on general-purpose processors tend to be slow because they do not take advantage of the inherent parallelism of these devices, whereas hardware realizations based on heterogeneous platforms (combining central processing units (CPUs), graphics processing units (GPUs) and/or field-programmable gate arrays (FPGAs)) are designed based on different solutions using methodologies supported by different languages and using very different implementation criteria. This paper first presents a study that demonstrates the need for a heterogeneous (CPU-GPU-FPGA) platform to accelerate the optimization of artificial neural networks (ANNs) using genetic algorithms. Second, the paper presents implementations of the calculations related to the individuals evaluated in such an algorithm on different (CPU- and FPGA-based) platforms, but with the same source files written in OpenCL. The implementation of individuals on remote, low-cost FPGA systems on a chip (SoCs) is found to enable the achievement of good efficiency in terms of performance per watt.

A Modified Algorithm for QRS Complex Detection for FPGA Implementation

This work is part of the Psypocket project which aims to conceive an embedded system able to recognize the stress state of an individual based on physiological and behavioural modifications. In this paper, one of the physiological data, the electrocardiographic (ECG) signal, is focused on. The QRS complex is the most significant segment in this signal. By detecting its position, the heart rate can be learnt. In this paper, a field-programmable gate array (FPGA) architecture for QRS complex detection is proposed. The detection algorithm adopts the integer Haar transform for ECG signal filtering and a maximum finding strategy to detect the location of R peak of the QRS complex. The ECG data are originally recorded by double-precision decimal with the sampling frequencies of 2000 Hz. For the FPGA implementation, they should be converted to integers with rounding operation. To find the best multiplying factor for rounding, the comparison is performed in MATLAB. Besides, to reduce the computation load in FPGA, the feasibility of the reduction in the sampling frequency is tested in MATLAB. The FPGA Cyclone EP3C5F256C6 is used as the target chip, and all the components of the system are implemented in VHSIC hardware description language. The testing results show that the proposed FPGA architecture achieves a high detection accuracy (98.41%) and a good design efficiency in terms of silicon consumption and operation speed. The proposed architecture will be adopted as a core unit to make a FPGA system for stress recognition.

From Pthreads to Multicore Hardware Systems in LegUp High-Level Synthesis for FPGAs

In the last decade, processor speeds have remained fairly stagnant, and to improve performance further, the industry started to increase the number of processor cores. The use of specialized hardware, such as field-programmable gate arrays (FPGAs), has also been on the rise. The traditional design methodology for FPGAs, however, requires hardware knowledge, which makes the platform inaccessible to software engineers. High-level synthesis (HLS) tools aim to resolve this issue by allowing software design methodologies to be used for FPGAs. However, HLS remains difficult to use for many software engineers, as there are tasks, such as system integration, which is still mostly a manual process. Consequently, creating a multicore hardware system on an FPGA is not feasible for most software engineers. To this end, we provide an HLS framework, which can automatically generate a multicore hardware system from software. We provide support for POSIX threads, which can be compiled to concurrently executing hardware cores that can be used in a processor–accelerator hybrid system, or in a hardware-only system without a processor. With this, we show that we can create multicore FPGA systems that can provide significant benefits in performance and energy-efficiency compared with hardware executing sequentially, and software executing on MIPS/ARM/ x86 processors.

Increasing feasibility of the field-programmable gate array implementation of an iterative image registration using a kernel-warping algorithm

Image registration is a fundamental image processing technique. It is used to spatially align two or more images that have been captured at different times, from different sensors, or from different viewpoints. There have been many algorithms proposed for this task. The most common of these being the well-known Lucas–Kanade (LK) and Horn–Schunck approaches. However, the main limitation of these approaches is the computational complexity required to implement the large number of iterations necessary for successful alignment of the images. Previously, a multi-pass image interpolation algorithm (MP-I2A) was developed to considerably reduce the number of iterations required for successful registration compared with the LK algorithm. This paper develops a kernel-warping algorithm (KWA), a modified version of the MP-I2A, which requires fewer iterations to successfully register two images and less memory space for the field-programmable gate array (FPGA) implementation than the MP-I2A. These reductions increase feasibility of the implementation of the proposed algorithm on FPGAs with very limited memory space and other hardware resources. A two-FPGA system rather than single FPGA system is successfully developed to implement the KWA in order to compensate insufficiency of hardware resources supported by one FPGA, and increase parallel processing ability and scalability of the system.

Pattern Classification of Fabric Defects Using a Probabilistic Neural Network and Its Hardware Implementation using the Field Programmable Gate Array System

This study proposes a fabric defect classification system using a Probabilistic Neural Network (PNN) and its hardware implementation using a Field Programmable Gate Arrays (FPGA) based system. The PNN classifier achieves an accuracy of 98 ± 2% for the test data set, whereas the FPGA based hardware system of the PNN classifier realises about 94±2% testing accuracy. The FPGA system operates as fast as 50.777 MHz, corresponding to a clock period of 19.694 ns.

FPGA system for QRS complex detection based on difference operation method

The detection of QRS complex is the start point for almost all electrocardiogram (ECG) applications. However, due to the complexity and non-causality of their mathematical computation, lots of QRS detectors can only be operated by using software but in a non-real-time fashion. This paper implements a real-time QRS complex detection system based on the difference operation method (DOM) and its efficient hardware architecture design. After simulations verified by MATLAB programs, we used the Verilog HDL (hardware description language) to perform the task of hardware design using the FPGA (field programmable gate array) system. The hardware design was tested with ECG records in the MIT-BIH (Massachusetts Institute of Technology- Beth Israel Hospital) arrhythmia database. The achievable accuracy exceeds 99% for records including typical and worst cases in the database.

Bio-Inspired Controller on an FPGA Applied to Closed-Loop Diaphragmatic Stimulation.

Cervical spinal cord injury can disrupt connections between the brain respiratory network and the respiratory muscles which can lead to partial or complete loss of ventilatory control and require ventilatory assistance. Unlike current open-loop technology, a closed-loop diaphragmatic pacing system could overcome the drawbacks of manual titration as well as respond to changing ventilation requirements. We present an original bio-inspired assistive technology for real-time ventilation assistance, implemented in a digital configurable Field Programmable Gate Array (FPGA). The bio-inspired controller, which is a spiking neural network (SNN) inspired by the medullary respiratory network, is as robust as a classic controller while having a flexible, low-power and low-cost hardware design. The system was simulated in MATLAB with FPGA-specific constraints and tested with a computational model of rat breathing; the model reproduced experimentally collected respiratory data in eupneic animals. The open-loop version of the bio-inspired controller was implemented on the FPGA. Electrical test bench characterizations confirmed the system functionality. Open and closed-loop paradigm simulations were simulated to test the FPGA system real-time behavior using the rat computational model. The closed-loop system monitors breathing and changes in respiratory demands to drive diaphragmatic stimulation. The simulated results inform future acute animal experiments and constitute the first step toward the development of a neuromorphic, adaptive, compact, low-power, implantable device. The bio-inspired hardware design optimizes the FPGA resource and time costs while harnessing the computational power of spike-based neuromorphic hardware. Its real-time feature makes it suitable for in vivo applications.

An alternative carry-save arithmetic for new generation field programmable gate arrays

In this work, a double carry-save addition operation is proposed, which is efficiently synthesized for 6-input LUT-based field programmable gate arrays (FPGAs). The proposed arithmetic operation is based on redundant number representation and provides carry propagation-free addition. Using the proposed arithmetic operation, a compact and fast multiply and accumulate unit is designed. To our knowledge, the proposed design provides the fastest multiply-add operation for 6-input LUT-based FPGA systems. A finite impulse response filter implementation is given to show the performance of the proposed structure. The proposed implementation provides a dramatic performance increase, which is at least 2 times faster than conventional binary multiply-add implementations.

A Nearest Neighbor Classifier Employing Critical Boundary Vectors for Efficient On-Chip Template Reduction.

Aiming at efficient data condensation and improving accuracy, this paper presents a hardware-friendly template reduction (TR) method for the nearest neighbor (NN) classifiers by introducing the concept of critical boundary vectors. A hardware system is also implemented to demonstrate the feasibility of using an field-programmable gate array (FPGA) to accelerate the proposed method. Initially, k -means centers are used as substitutes for the entire template set. Then, to enhance the classification performance, critical boundary vectors are selected by a novel learning algorithm, which is completed within a single iteration. Moreover, to remove noisy boundary vectors that can mislead the classification in a generalized manner, a global categorization scheme has been explored and applied to the algorithm. The global characterization automatically categorizes each classification problem and rapidly selects the boundary vectors according to the nature of the problem. Finally, only critical boundary vectors and k -means centers are used as the new template set for classification. Experimental results for 24 data sets show that the proposed algorithm can effectively reduce the number of template vectors for classification with a high learning speed. At the same time, it improves the accuracy by an average of 2.17% compared with the traditional NN classifiers and also shows greater accuracy than seven other TR methods. We have shown the feasibility of using a proof-of-concept FPGA system of 256 64-D vectors to accelerate the proposed method on hardware. At a 50-MHz clock frequency, the proposed system achieves a 3.86 times higher learning speed than on a 3.4-GHz PC, while consuming only 1% of the power of that used by the PC.

A Low Active Leakage and High Reliability Phase Change Memory (PCM) Based Non-Volatile FPGA Storage Element

The high leakage current has been one of the critical issues in SRAM-based Field Programmable Gate Arrays (FPGAs). In recent works, resistive non-volatile memories (NVMs) have been utilized to tackle the issue with their superior energy efficiency and fast power-on speed. Phase Change Memory (PCM) is one of the most promising resistive NVMs with the advantages of low cost, high density and high resistance ratio. However, most of the reported PCM-based FPGAs have significant active leakage power and reliability issues. This paper presents a low active leakage power and high reliability PCM based non-volatile SRAM (nvSRAM). The low active leakage power and high reliability are achieved by biasing PCM cells at 0 V during FPGA operation. Compared to the state-of-the-art, the proposed nvSRAM based 4-input look up table (LUT) achieves 174 times reduction in active leakage power and 15000 times increase in retention time. In addition, the proposed nvSRAM-based FPGA system significantly accelerates the loading speed to less than 1 ns with 2.54 fJ/cell loading energy.

Improving Energy Efficiency in FPGA Through Judicious Mapping of Computation to Embedded Memory Blocks

Field-programmable gate arrays (FPGAs) are being increasingly used as a preferred prototyping and accelerator platform for diverse application domains, such as digital signal processing (DSP), security, and real-time multimedia processing. However, mapping of these applications to FPGA typically suffers from poor energy efficiency because of high energy overhead of programmable interconnects (PI) in FPGA devices. This paper presents an energy-efficient heterogenous application mapping framework in FPGA, where the conventional application mappings to logic and DSP blocks (for DSP-enhanced FPGA devices) are combined with judicious mapping of specific computations to embedded memory blocks. A complete mapping methodology including functional decomposition, fusion, and optimal packing of operations is proposed and efficiently used to reduce the large energy overhead of PIs. Effectiveness of the proposed methodology is verified for a set of common applications using a commercial FPGA system. Experimental results show that the proposed heterogenous mapping approach achieves significant energy improvement for different input bit-widths (e.g., more than 35% of energy savings with 8 bit or smaller bit inputs compared to the corresponding mapping in configurable logic blocks). For further reduction of energy, we propose an energy/accuracy tradeoff approach, where the input operand bit-width is dynamically truncated to reduce memory area and energy at the expense of modest degradation in output-accuracy. We show that using a preferential truncation method, up to 88.6% energy savings can be achieved in a 32-tap finite impulse response filter with modest impact on the filter performance.

FPGAs operating in a radiation environment: lessons learned from FPGAs in space

Field Programmable Gate Arrays (FPGAs) are increasingly being used as a key component of digital systems because of their in-fieldreprogrammability, low non-recurring engineering costs (NRE), andrelatively short design cycle. Recently, there has been greatinterest in using FPGAs within spacecraft. FPGAs, like allsemiconductor devices, are susceptible to the effects of radiation.There is an active research community investigating the effects ofradiation on FPGAs and developing methods to mitigate against theseeffects. There has been significant progress over the last decade inthe understanding and developing FPGA technology that is resistant tothe effects of radiation. The success of FPGAs within spacecraftsuggests that FPGAs may be used in particle physics experiments whereradiation levels are considerable higher than the conventionalterrestrial earth environment. This paper will summarize the effectsof radiation on FPGAs, methods to mitigate against these effects,provide a case study of a successful FPGA system operating in space,and discuss the issues that will affect the use of FPGAs withinparticle physics experiments.

2-DOF PIEZOELECTRIC ACTUATOR CONTROLLER BASED ON FPGA

This article presents the method for controlling the piezolegs motor with the application of the FPGA (Field-programmable gate array) system and presents the results of conducted tests of the motor slider displacement, with various steering signal configurations. It includes also the review of piezoelectric motors solutions and characteristics of systems, based on FPGA systems. Suggested steering solution can be used for subsequent tests on piezolegs drives and can constitute positioning system element.

Pipelined CPU Design With FPGA in Teaching Computer Architecture

This paper presents a pipelined CPU design project with a field programmable gate array (FPGA) system in a computer architecture course. The class project is a five-stage pipelined 32-bit MIPS design with experiments on the Altera DE2 board. For proper scheduling, milestones were set every one or two weeks to help students complete the project on time. The goal of the project is to educate students effectively via hands-on learning, rather than having them achieve a complete and flawless CPU design. This study reveals that 21 MIPS instructions are enough to achieve the purpose. With the addition in 2010 of the properly enforced scheduling and the FPGA system, many more students successfully completed the class project than was the case in 2009. A student survey and the independent samples t-test reveal the effectiveness of the methodology with the FPGA system. This work differs from previous work in that the devised project requires the implementation of a real CPU instead of utilizing simulators or just experimenting with ready-made complete CPU models.

Use of FPGA or GPU-based architectures for remotely sensed hyperspectral image processing

Hyperspectral imaging is a growing area in remote sensing in which an imaging spectrometer collects hundreds of images (at different wavelength channels) for the same area on the surface of the Earth. Hyperspectral images are extremely high-dimensional, and require advanced on-board processing algorithms able to satisfy near real-time constraints in applications such as wildland fire monitoring, mapping of oil spills and chemical contamination, etc. One of the most widely used techniques for analyzing hyperspectral images is spectral unmixing, which allows for sub-pixel data characterization. This is particularly important since the available spatial resolution in hyperspectral images is typically of several meters, and therefore it is reasonable to assume that several spectrally pure substances (called endmembers in hyperspectral imaging terminology) can be found within each imaged pixel. In this paper we explore the role of hardware accelerators in hyperspectral remote sensing missions and further inter-compare two types of solutions: field programmable gate arrays (FPGAs) and graphics processing units (GPUs). A full spectral unmixing chain is implemented and tested in this work, using both types of accelerators, in the context of a real hyperspectral mapping application using hyperspectral data collected by NASA's Airborne Visible Infra-Red Imaging Spectrometer (AVIRIS). The paper provides a thoughtful perspective on the potential and emerging challenges of applying these types of accelerators in hyperspectral remote sensing missions, indicating that the reconfigurability of FPGA systems (on the one hand) and the low cost of GPU systems (on the other) open many innovative perspectives toward fast on-board and on-the-ground processing of remotely sensed hyperspectral images.

Fuzzy logic applied to control a one degree of freedom (DOF) pneumatic robot

For many years, the vast majority of robots have been built with electrical actuators, and pneumatic actuators are not considered to control the position of a manipulator robot. Instead, electrical actuators are used. The main concern with pneumatic actuators is the highly non linear behavior, due to the high compressibility of the air. This work is focused on a one degree of freedom (DOF) robot, with pneumatic actuator to control the angle of the arm. A dynamic mathematical model of the manipulator is used, including the thermo-mechanical model. The air flow through the pneumatic cylinder is controlled by a 5/3 electro-valve. A pulse width modulation (PWM) signal is used to activate each coil of the electro-valve, where the duty cycle is set by a fuzzy logic algorithm. The fuzzy system is implemented into field-programmable gate array (FPGA), including the digital interface with a computer, an optical encoder and four seven-segment displays. This work is focused on the hardware implementation of fuzzy logic algorithm into FPGA system using the Sugeno algorithm, into a FPGA device, applied to the pneumatic electro-valve, with 25 ms of sample time. Key words: Field-programmable gate array (FPGA) hardware, fuzzy logic, pneumatic robot, dynamic.

An analytical model for multilevel performance prediction of Multi-FPGA systems

Power limitations in semiconductors have made explicitly parallel device architectures such as Field-Programmable Gate Arrays (FPGAs) increasingly attractive for use in scalable systems. However, mitigating the significant cost of FPGA development requires efficient design-space exploration to plan and evaluate a range of potential algorithm and platform choices prior to implementation. The authors propose the RC Amenability Test for Scalable Systems (RATSS), an analytical model which enables straightforward, fast, and reasonably accurate performance prediction prior to implementation by extending current modeling concepts to multi-FPGA designs. RATSS provides a comprehensive strategic model to evaluate applications based on the computation and communication requirements of the algorithm and capabilities of the FPGA platform. The RATSS model targets data-parallel applications on current scalable FPGA systems. Three case studies with RATSS demonstrate nearly 90% prediction accuracy as compared to corresponding implementations.

Fuzzy irrigation greenhouse control system based on a field programmable gate array

Fuzzy logic provides a methodology to represent, manipulate, and implement heuristic knowledge to control a system. In this work, the development of a fuzzy irrigation control system based on a field programmable gate array (FPGA) to control greenhouse fertigation was presented. Factors involved in crop nutrition were discussed first. Further, the description of the fuzzy control system was presented, followed by the analysis and design of the fuzzy controller, and its implementation, a FPGA-integrated circuit. The FPGA system is not only flexible (it can be easily reconfigured and reused for different designs), but it also provides rapid prototyping and offers the capability to perform multiple operations at the same time, producing positive economic returns. The design, compilation, and simulation of the system were developed in Active-hardware description language (HDL) using the hardware description language, very high-speed integrated circuit hardware description language (VHDL). Results from simulation and experiments showed the simplicity of the design, the viability of its implementation, and the low cost that the use of a fuzzy logic controller and FPGA system represents. Key words: Fuzzy logic controller, irrigation system, field programmable gate array (FPGA).

Embedded System Implementation on FPGA System With μCLinux OS

Embedded systems are taking on more complicated tasks as the processors involved become more powerful. The embedded systems have been widely used in many areas such as in industries, automotives, medical imaging, communications, speech recognition and computer vision. The complexity requirements in hardware and software nowadays need a flexibility system for further enhancement in any design without adding new hardware. Therefore, any changes in the design system will affect the processor that need to be changed. To overcome this problem, a System On Programmable Chip (SOPC) has been designed and developed using Field Programmable Gate Array (FPGA). A softcore processor, NIOS II 32-bit RISC, which is the microprocessor core was utilized in FPGA system together with the embedded operating system(OS), μClinux. In this paper, an example of web server is explained and demonstrated

Computerised Speech Processing in Hearing Aids using FPGA Architecture

The development of computerized speech processing system is to mimic the natural functionality of human hearing, because of advent of technology that used Very Large Scale Integration (VLSI) devices such as Field Programmable Gate Array (FPGA) to meet the challenging requirement of providing 100% functionality of the damaged human hearing parts. Here a computerized laboratory speech processor based on Xilinx Spartan3 FPGA system was developed for hearing aids research and also presented comparison details of the commercially available Hearing Aids. The hardware design and software implementation of the speech processor are described in detail. The FPGA based speech processor is capable of providing high- rate stimulation with 12 electrodes against conventional 8 electrodes in earlier research. Using short biphasic pulses presented either simultaneously or in an interleaved fashion. Different speech processing algorithms including the Continuous Interleaved Sampling (CIS) strategy were implemented in this processor and tested successfully.