Field Programmable Gate Array Platform Research Articles

FPGA-based process, voltage, and temperature insensitive picosecond resolution timing generators with offset correction for automatic test equipment.

This paper presents the implementation of a picosecond resolution timing generator (TG) insensitive to process, voltage, and temperature (PVT) variations for automatic test equipment. The TG is implemented in field-programmable gate arrays (FPGAs) using two-stage time interpolation, which utilizes a multi-phase generator, IDELAY3, and carry-chain resources. To enhance the test rate, each channel of the proposed TG consists of four parallel operating edge generators. The TG performance will deteriorate severely without offset correction due to its sensitivity to PVT variations. To improve the adaptability of the TG, we design a robust offset canceler to ensure stable performance of the TG, resilient to PVT variations. With the proposed architecture and offset canceler, the PVT-insensitive TG achieves a time resolution of 5ps and offers a maximum dynamic range of 10s. It also shows improved worst case integral non-linearity ranging from -4.7 to +4.6ps with the operating temperature continuously varying from 15 to 65 °C and voltage ranging from 0.95 to 1.01V in FPGAs. The proposed TG can be implemented in the Ultrascale or Ultrascale+ FPGA platform.

Enhanced global navigation satellite system signal processing using field programmable gate array and system-on-chip based software receivers

This paper presents a new approach to improving global navigation satellite system (GNSS) signal processing by using baseband processing techniques on field-programmable gate array (FPGA) platforms and a system-on-chip (SoC)-based GNSS software receiver. By leveraging the flexibility and computational power of FPGAs and the integration capabilities of SoC platforms, the method significantly enhances signal acquisition, tracking accuracy, and overall system performance. The integration of the ADFMCOMMS3-EBZ RF front end with the Zynq 7000 SoC board, along with high-speed parallel I/O and serial peripheral interface (SPI) for data management and configuration, enables efficient processing of high-speed signals. The study also explores wavelet transform techniques, such as the discrete wavelet transform (DWT), to improve filtering and noise reduction in GNSS signals. The results show that the proposed baseband processing algorithm for GNSS software-defined radio (SDR) reduces acquisition time and enhances tracking accuracy compared to traditional personal computer (PC)-based systems. Additionally, the SoC-based receiver is more energy-efficient and uses fewer resources. Comparative analysis shows that the proposed method provides more received samples, fewer dropped samples, and a lower data loss rate, confirming its effectiveness in boosting GNSS signal processing reliability and efficiency.

CHIRP: C ompact and H igh-Performance FPGA Implementation of Un i fied Hardware Accelerators for R ing-Binary-LWE-based P QC

Post-quantum cryptography (PQC) has drawn significant attention from the hardware design research community, especially on field-programmable gate array (FPGA) platforms. In line with this trend, in this paper, we present a novel FPGA-based PQC design work (CHIRP), i.e., C ompact and high- P erformance FPGA implementation of un I fied accelerators for R ing-Binary-Learning-with-Errors (RBLWE)-based P QC, a promising lightweight PQC suited for related applications like Internet-of-Things. The proposed accelerators offer flexibility across the available two security levels, thus expanding their application potential. In total, we presented four distinct hardware accelerators tailored to different performance and resource requirements, ranging from resource-constrained devices to high-throughput applications. Our innovation encompasses three key efforts: (i) we derived four optimized algorithms for RBLWE-ENC’s unified operation (covering the available two security levels), allowing flexible switching of security sizes while boosting calculations; (ii) we then presented the four novel accelerators (CHIRP) targeting FPGA platforms, featuring dedicated hardware structures; (iii) we finally conducted a comprehensive evaluation to validate the efficiency of the proposed accelerators on various FPGA devices. Compared to the existing unified design, the proposed accelerator demonstrated up to 91.4% reduction in area-delay product (ADP) on the Straix-V device. Even when compared with the state-of-the-art single security designs, the proposed accelerator (best version) obtains much better resource usage and ADP performance while unified operation (flexibly switching between two security levels) is considered on both AMD-Xilinx and Intel devices. We anticipate the findings of this research will foster advancements in FPGA implementation techniques for lightweight PQC development.

Accelerating Deep Learning-Based Morphological Biometric Recognition with Field-Programmable Gate Arrays

Convolutional neural networks (CNNs) are increasingly recognized as an important and potent artificial intelligence approach, widely employed in many computer vision applications, such as facial recognition. Their importance resides in their capacity to acquire hierarchical features, which is essential for recognizing complex patterns. Nevertheless, the intricate architectural design of CNNs leads to significant computing requirements. To tackle these issues, it is essential to construct a system based on field-programmable gate arrays (FPGAs) to speed up CNNs. FPGAs provide fast development capabilities, energy efficiency, decreased latency, and advanced reconfigurability. A facial recognition solution by leveraging deep learning and subsequently deploying it on an FPGA platform is suggested. The system detects whether a person has the necessary authorization to enter/access a place. The FPGA is responsible for processing this system with utmost security and without any internet connectivity. Various facial recognition networks are accomplished, including AlexNet, ResNet, and VGG-16 networks. The findings of the proposed method prove that the GoogLeNet network is the best fit due to its lower computational resource requirements, speed, and accuracy. The system was deployed on three hardware kits to appraise the performance of different programming approaches in terms of accuracy, latency, cost, and power consumption. The software programming on the Raspberry Pi-3B kit had a recognition accuracy of around 70–75% and relied on a stable internet connection for processing. This dependency on internet connectivity increases bandwidth consumption and fails to meet the required security criteria, contrary to ZYBO-Z7 board hardware programming. Nevertheless, the hardware/software co-design on the PYNQ-Z2 board achieved an accuracy rate of 85% to 87%. It operates independently of an internet connection, making it a standalone system and saving costs.

A Recursive Trigonometric Technique for Direct Digital Frequency Synthesizer Implementation

This paper presents a novel recursive trigonometry (RT) technique for direct digital frequency synthesizer (DDFS) implementations. Traditional DDFS systems on field programmable gate arrays (FPGAs) either require a substantial amount of read-only memory (ROM) space to store reference values or depend on intricate angle rotation functions to approximate trigonometric values. The proposed RT technique offers a DDFS architecture without using the lookup table (LUT) method, and it can enhance signal accuracy and minimize power consumption. The effectiveness of the proposed RT technique has been implemented in a 13.5 kHz 16-bit DDFS with a minimum of 18.91 mW and was tested on a Lattice FPGA. The effectiveness of the proposed RT technology is assessed by using different FPGA platforms in terms of accuracy, hardware resource efficiency, and power consumption, especially in generating cosine waveforms.

Radar and communication integration under FPGA platform: real-time waveform generation with time division multiplexing and waveform sharing strategy

Abstract The integration of radar and communication technologies is gaining prominence in electronic information systems. This paper explores advanced waveform strategies—LFM (Linear Frequency Modulation) + MSK (Minimum Shift Keying) based on time-division multiplexing and LFM-MSK utilizing waveform sharing. These methods enhance spectrum efficiency and system capabilities in detecting targets and transmitting data reliably amidst complex environments. Based on the FPGA (Field Programmable Gate Array) platform, this study proposes real-time waveform generation methods for integrated radar communication waveforms, specifically LFM+MSK and LFM-MSK. It focuses on discussing FPGA implementation solutions for these methods and validates their effectiveness. This research addresses a critical gap in the field and provides practical insights for radar communication integration systems.

FPGA-Based Sparse Matrix Multiplication Accelerators: From State-of-the-Art to Future Opportunities

Sparse matrix multiplication (SpMM) plays a critical role in high-performance computing applications, such as deep learning, image processing, and physical simulation. Field-Programmable Gate Arrays (FPGAs), with their configurable hardware resources, can be tailored to accelerate SpMMs. There has been considerable research on deploying sparse matrix multipliers across various FPGA platforms. However, the FPGA-based design of sparse matrix multipliers still presents numerous challenges. Therefore, it is necessary to summarize and organize the current work to provide a reference for further research. This article first introduces the computational method of SpMM and categorizes the different challenges of FPGA deployment. Following this, we introduce and analyze a variety of state-of-the-art FPGA-based accelerators tailored for SpMMs. In addition, a comparative analysis of these accelerators is performed, examining metrics including compression rate, throughput, and resource utilization. Finally, we propose potential research directions and challenges for further study of FPGA-based SpMM accelerators.

STEP-NC compliant 3-axis CNC machine controller based on Field-Programmable Gate Arrays

ABSTRACT Manufacturing processes have gone through several transformations in history. Previously, G&M codes served as a common programming language for CNC machines. Codes of CNC machines contain the information related to the tools and trajectories. G&M codes are machine-specific and vendors must customize them for the tools installed on a particular machine. STEP-NC, described by ISO-14649, provides an alternative to G&M codes aiming at generic interoperability of CNC machine codes. STEP-NC includes information on both the trajectories and the tool’s specifications making it generic and machine-independent. STEP-NC is an emerging area and a gateway to intelligent machining targeting ‘design anywhere and develop anywhere’. Therefore, several researchers have developed software-based decoders and interpreters. They are difficult to implement on a serial pipelined processor limiting their use for real-time applications. This paper presents a Field Programmable Gate Array (FPGA)-based STEP-NC controller implemented and validated on a SPARTAN-3E kit. To the best of the author’s knowledge, this is the first FPGA-based implementation of STEP-NC. The main contribution of this work is a generic state-machine representation of the STEP-NC entities suitable for implementation on different FPGA platforms. The developed decoder was successfully tested and evaluated on a three-axis CNC machine for an example given in ISO-14649-11 for compliance.

High-throughput systolic array-based accelerator for hybrid transformer-CNN networks

In this era of Transformers enjoying remarkable success, Convolutional Neural Networks (CNNs) remain highly relevant and useful. Indeed, hybrid Transformer-CNN network architectures, which combine the benefits of both approaches, have achieved impressive results. Vision Transformer (ViT) is a significant neural network architecture that features a convolutional layer as its first layer, primarily built on the transformer framework. However, owing to the distinct computation patterns inherent in attention and convolution, existing hardware accelerators for these two models are typically designed separately and lack a unified approach toward accelerating both models efficiently. In this paper, we present a dedicated accelerator on a field-programmable gate array (FPGA) platform. The accelerator, which integrates a configurable three-dimensional systolic array, is specifically designed to accelerate the inferential capabilities of hybrid Transformer-CNN networks. The Convolution and Transformer computations can be mapped to a systolic array by unifying these operations for matrix multiplication. Softmax and LayerNorm which are frequently used in hybrid Transformer-CNN networks were also implemented on FPGA boards. The accelerator achieved high performance with a peak throughput of 722 GOP/s at an average energy efficiency of 53 GOPS/W. Its respective computation latencies were 51.3 ms, 18.1 ms, and 6.8 ms for ViT-Base, ViT-Small, and ViT-Tiny. The accelerator provided a 12× improvement in energy efficiency compared to the CPU, a 2.3× improvement compared to the GPU, and a 1.5× to 2× improvement compared to existing accelerators regarding speed and energy efficiency.

Review of neural network model acceleration techniques based on FPGA platforms

Neural network models, celebrated for their outstanding scalability and computational capabilities, have demonstrated remarkable performance across various fields such as vision, language, and multimodality. The rapid advancements in neural networks, fueled by the deep development of Internet technology and the increasing demand for intelligent edge devices, introduce new challenges, including significant model parameter sizes and increased storage pressures. In this context, Field-Programmable Gate Arrays (FPGA) emerge as a preferred platform for accelerating neural network models, thanks to their exceptional performance, energy efficiency, and the flexibility and scalability of the system. Building FPGA-based neural network systems necessitates bridging significant differences in objectives, methods, and design spaces between model design and hardware design. This review article adopts a comprehensive analytical framework to thoroughly explore multidimensional technological implementation strategies, encompassing optimizations at the algorithmic and hardware levels, as well as compiler optimization techniques. It focuses on methods for collaborative optimization between algorithms and hardware, identifies challenges in the collaborative design process, and proposes corresponding implementation strategies and key steps. Addressing various technological dimensions, the article provides in-depth technical analysis and discussion, aiming to offer valuable insights for research on optimizing and accelerating neural network models in edge computing environments.

Design of a discrete memristive chaotic map: fractional-order memory, dynamics and application

In this paper, a discrete fracmemristor (DFM) model is derived based on the Caputo difference, and a new fractional-order chaotic map is designed. Dynamics of the proposed map is investigated in detail by means of Lyapunov exponent spectra, bifurcation diagrams, PE complexity and multistability analyses. Compared with the coupled discrete integer-order memristor (DIM), the map coupled with the DFM products richer dynamics, including larger attractor distribution, fewer numerically periodic windows, and higher complexity. Besides, the order becomes additional bifurcation parameter. Finally, the proposed map is implemented on Field-Programmable Gate Array (FPGA) platform, and applied in a pseudorandom number generator (PRNG), which further demonstrates its application value.

A Human-Computer Interaction Strategy for An FPGA Platform Boosted Integrated "Perception-Memory" System Based on Electronic Tattoos and Memristors.

The integrated "perception-memory" system is receiving increasing attention due to its crucial applications in humanoid robots, as well as in the simulation of the human retina and brain. Here, a Field Programmable Gate Array (FPGA) platform-boosted system that enables the sensing, recognition, and memory for human-computer interaction is reported by the combination of ultra-thin Ag/Al/Paster-based electronic tattoos (AAP) and Tantalum Oxide/Indium Gallium Zinc Oxide (Ta2O5/IGZO)-based memristors. Notably, the AAP demonstrates exceptional capabilities in accommodating the strain caused by skin deformation, thanks to its unique structural design, which ensures a secure fit to the skin and enables the prolonged monitoring of physiological signals. By utilizing Ta2O5/IGZO as the functional layer, a high switching ratio is conferred to the memristor, and an integrated system for sensing, distinguishing, storing, and controlling the machine hand of multiple human physiological signals is constructed together with the AAP. Further, the proposed system implements emergency calls and smart homes using facial electromyogram signals and utilizing logical entailment to realize the control of the music interface. This innovative "perception-memory" integrated system not only serves the disabled, enhancing human-computer interaction but also provides an alternative avenue to enhance the quality of life and autonomy of individuals with disabilities.

Optimized Hardware-Software Co-Design for Kyber and Dilithium on RISC-V SoC FPGA

Kyber and Dilithium are both lattice-based post-quantum cryptography (PQC) algorithms that have been selected for standardization by the American National Institute of Standards and Technology (NIST). NIST recommends them as two primary algorithms to be implemented for most use cases. As the applications of RISC-V processors move from specialized scenarios to general scenarios, efficient implementations of PQC algorithms on general-purpose RISC-V platforms are required. In this work, we present an optimized hardware-software co-design for Kyber and Dilithium on the industry’s first RISC-V System-on-Chip (SoC) Field Programmable Gate Array (FPGA) platform. The performance of both algorithms is enhanced through the utilization of hardware acceleration and software optimization, while a certain level of flexibility is still maintained. The polynomial arithmetic operations in Kyber and Dilithium are accelerated by the customized accelerators. We employ a unified high-level architecture to depict their shared characteristics and design dedicated underlying modular multipliers to explore their distinctive features. The hashing functions are optimized using RISC-V assembly instructions, resulting in improved performance and reduced code size without additional hardware resources. For other operations involving matrices and vectors, we present a multi-core acceleration scheme based on the multi-core RISC-V Microprocessor Sub-System (MSS). Combining these acceleration and optimization methods, experimental results show that the overall performance of Kyber and Dilithium across different security levels improves by 3 to 5 times, while the utilized FPGA resources account for less than 5% of the total resources provided by the platform.

The application of Verilog in the development of casual games

Verilog is a hardware description language (HDL) that is widely used in digital circuit design and simulation. Its development is closely related to computer science and electrical engineering. Verilog gained popularity in the early 1980s as digital circuit designs became increasingly complex, requiring more efficient circuit design and verification tools. At the same time, rapid advances in computer hardware also stimulated the demand for digital circuit design languages. Furthermore, the popularity and adoption of Verilog highlight the growing necessity for digitisation, automation, and intelligence in modern society. As digital technology continues to advance across various industries, the need for effective and dependable digital circuit design languages is also increasing. This paper delves into the complex process of recreating the timeless arcade classic Pac-Man on the Spartan 3E FPGA platform using hardware description and digital circuit techniques and the Verilog programming language. Through a comprehensive review of existing literature and research, this study investigates the fusion of traditional game design principles with state-of-the-art hardware programming methods, demonstrating the seamless integration of software-driven game mechanics with hardware-based implementation. Through careful design and coding strategies, Pac-Man's basic functionality, such as maze traversal, ghost AI, and pellet consumption, is faithfully replicated using Verilog modules customized for the Spartan 3E FPGA board. By bridging the realms of game development and hardware engineering, this paper not only showcases the versatility of Field Programmable Gate Array (FPGA) technology in entertainment applications but also underscores the interdisciplinary nature of modern computing endeavours.

A High-Performance and Ultra-Low-Power Accelerator Design for Advanced Deep Learning Algorithms on an FPGA

This article addresses the growing need in resource-constrained edge computing scenarios for energy-efficient convolutional neural network (CNN) accelerators on mobile Field-Programmable Gate Array (FPGA) systems. In particular, we concentrate on register transfer level (RTL) design flow optimization to improve programming speed and power efficiency. We present a re-configurable accelerator design optimized for CNN-based object-detection applications, especially suitable for mobile FPGA platforms like the Xilinx PYNQ-Z2. By not only optimizing the MAC module using Enhanced clock gating (ECG), the accelerator can also use low-power techniques such as Local explicit clock gating (LECG) and Local explicit clock enable (LECE) in memory modules to efficiently minimize data access and memory utilization. The evaluation using ResNet-20 trained on the CIFAR-10 dataset demonstrated significant improvements in power efficiency consumption (up to 22%) and performance. The findings highlight the importance of using different optimization techniques across multiple hardware modules to achieve better results in real-world applications.

FPGA-Based Acceleration of Polar-Format Algorithm for Video Synthetic-Aperture Radar Imaging

This paper presents a polar-format algorithm (PFA)-based synthetic-aperture radar (SAR) processor that can be mounted on a small drone to support video SAR (ViSAR) imaging. For drone mounting, it requires miniaturization, low power consumption, and high-speed performance. Therefore, to meet these requirements, the processor design was based on a field-programmable gate array (FPGA), and the implementation results are presented. The proposed PFA-based SAR processor consists of both an interpolation unit and a fast Fourier transform (FFT) unit. The interpolation unit uses linear interpolation for high speed while occupying a small space. In addition, the memory transfer is minimized through optimized operations using SAR system parameters. The FFT unit uses a base-4 systolic array architecture, chosen from among various fast parallel structures, to maximize the processing speed. Each unit is designed as a reusable block (IP core) to support reconfigurability and is interconnected using the advanced extensible interface (AXI) bus. The proposed PFA-based SAR processor was designed using Verilog-HDL and implemented on a Xilinx UltraScale+ MPSoC FPGA platform. It generates an image 2048 × 2048 pixels in size within 0.766 s, which is 44.862 times faster than that achieved by the ARM Cortex-A53 microprocessor. The speed-to-area ratio normalized by the number of resources shows that it achieves a higher speed at lower power consumption than previous studies.

Dynamics modeling of a memristor-based Rucklidge chaotic system: Multistability, offset boosting control and FPGA implementation

The complex dynamics greatly contributes to the application of chaos, especially the memristor chaotic systems that have emerged very recently. In this paper, a novel four-dimensional continuous chaotic system is developed by introducing a generalized memristor model into the classical Rucklidge system, and the rich dynamical traits are confirmed by theories and numerical simulations. System Hamilton energy is deduced and analyzed to expose the underlying energy evolution and chaos mechanism. And then, realizing the offset boosting control of the system promotes its engineering applications. Numerical simulations verify that the offset boosting controller can directly change the polarity of the chaotic signal. Specifically, bifurcation diagram, Lyapunov spectra, system complexity evolution diagram and dynamic evolution map are adopted to expound the rich dynamics. Meanwhile, the extreme multi-stability with various initial values resulting in an infinite number of coexisting attractors is also revealed. Finally, the proposed attractor is implemented using the Field Programmable Gate Array (FPGA) platform and building analog circuit based on Multisim. Among which, the former is potentially used to design the Pseudo-random signal generator in information encryption, while the latter is for verifying the existence of the proposed chaotic system.

A novelty detection method for efficient data storage in smart grids

This work presents a new novelty detection method for efficiently storing electrical power system data. The proposed method makes innovative use of the Cycle-by-Cycle Difference (CCD) and the Mathematical Morphology (MM) techniques to identify novelties in the voltage of an electrical power system. Once the novelties are identified, the frames where they occur are extracted from the signal, and the other frames are discarded. Among the extracted frames, those containing power quality (PQ) disturbances are fully stored, while the frames that represent stationary states have only their main parameters stored, contributing to efficient storage. The proposed method exhibited low computational complexity in the operational phase, which was evaluated via a field-programmable gate array (FPGA) platform implementation using a customized embedded processor. The method was evaluated with real and simulated signals. The results indicate that the developed method attained high detection probabilities alongside low false alarm probabilities, resulting in a competitive Area Under the Curve (AUC) exceeding 0.976 (except for interharmonics). Comparison with other methods revealed that our approach yielded competitive results with the lowest computational cost. We concluded that the proposed method may be useful for monitoring PQ disturbances in smart grids, where the data volumes are too large.

SoC-FPGA Based Concept of Hardware Aided Quantum Simulation

Contemporary industry and science expectations towards technological solutions set the bar high. Current approaches to increasing the computing power of standard systems are reaching the limits of physics known to humankind. Fast, programmable systems with relatively low power consumption are a different concept for performing complex calculations. Highly parallel processing opens up a number of possibilities in the context of accelerating calculations. Application of SoC (System On Chip) with FPGA (Field-Programmable Gate Array) enables to delegate of a part of computations to the gates matrix, thereby expediting processing by using parallelization of hardware operations. This paper presents the general concept of using SoC FPGA systems to support CPU (Central Processing Unit) in many modern tasks. While some tasks might be really hard to implement on an FPGA in a reasonable time, the SoC FPGA platform allows for easy low-level interconnections, and with such virtualized access to the hardware computing resources, it is seen as making FPGAs, or hardware in general, more accessible to engineers accustomed to high-level solutions. The concept presented in the article takes into account the limited resources of cheaper educational platforms, which, however, still provide an interesting and alternative hybrid solution to the problem of parallelization and acceleration of data processing. This allows to overcome encountered limitations and maintain the flexibility known from high-level solutions and high performance achieved with low-level programming, without the need for a high financial background.

A New Optimized Hybridization Approach for in silico High Throughput Molecular Docking on FPGA Platform.

The development process of a new drug should be a subject of continuous evolution and rapid improvement as drugs are essential to treat a wide range of diseases of which many are life-threatening. The advances in technology resulted in a novel track in drug discovery and development known as in silico drug design. The molecular docking phase plays a vital role in in silico drug development process. In this phase, thousands of 3D conformations of both the ligand and receptor are generated and the best conformations that create the most stable drug-receptor complex are determined. The speed in finding accurate and high-quality complexes depends on the efficiency of the search function in the molecular docking procedure. The objective of this research is to propose and implement a novel hybrid approach called hABCDE to replace the EMC searching part inside the BUDE docking algorithm. This helps in reaching the best solution in a much accelerated time and higher solution quality compared to using the ABC and DE algorithms separately. In this work, we have employed a new approach of hybridization between the Artificial Bee Colony (ABC) algorithm and the Differential Evolution (DE) algorithm as an alternative searching part of the Bristol University Docking Engine (BUDE) in order to accelerate the search for higher quality solutions. Moreover, the proposed docking approach was implemented on Field Programmable Gate Array (FPGA) parallel platform using Vivado High-Level Synthesis Tool (HLST) in order to optimize and enhance the execution time and overall efficiency. The NDM-1 protein was used as a model receptor in our experiments to demonstrate the efficiency of our approach. The NDM-1 protein was used as a model receptor in our experiments to demonstrate the efficiency of our approach. The results showed that the execution time for the BUDE with the new proposed hybridization approach was improved by 9,236 times. Our novel approach was significantly effective to improve the functionality of docking algorithms (Bristol University Docking Engine (BUDE)).