Field Programmable Gate Array Implementation Research Articles

Energy efficient noise error pattern generator for guessing decoding in bursty channels

For the hard guessing random additive noise decoding Markov order (GRAND-MO) algorithm, it is crucial to develop an efficient noise error patterns (NEPs) generator to facilitate its application in bursty channels. This paper proposes a practical hardware realization by generating the NEPs in a sequential manner. Based on classification of the four types of NEPs, we propose to iteratively calculate the “1" and the “0" permutations in the same time. Then, the novel “0" permutation regularization and bit flipping techniques are employed, through which the generation of the four types of NEPs is uniformed at the same way. Moreover, the proposed NEPs generator can generate all NEPs by using the “1" burst parameters, and is suitable for the guessing decoding of any linear block codes. Built on field programmable gate array (FPGA) implementation and comparison with existing benchmark, we show the proposed NEPs generator is a power-efficient architecture for realization. This work presents a new solution for the hardware implementation of the NEPs generator in GRAND-MO.

An improved CFAR algorithm for multiple environmental conditions

The primary objective of radar digital signal processing is to detect and identify targets in complicated situations, such as those involving clutter or several closely positioned targets. The constant false alarm rate (CFAR) method is more effective for target recognition and has better control over the false alarm rate. Many studies have been conducted on the design of CFAR, but previous CFAR algorithms have not been effective in all or most environmental fields and target scenarios. In this study, an algorithm called Censored Mean Clutter Map CFAR (CM-CM CFAR) has been developed and tested for various environmental conditions. When compared to a fixed false alarm rate, the suggested CFAR algorithm’s Monte Carlo simulation results demonstrated a high detection probability in a variety of environments. This work designs a real-time CM-CM CFAR processor using field-programmable gate array (FPGA) technologies. Xilinx ARTIX 7 FPGA technology is used to develop and map a scalable parallel framework. Consequently, the implementation required 23,741 LUTs and 1825 FF. It is verified that the complexity and operating speed of the suggested CFAR processor are extremely appropriate for real-time implementation when compared to the results of the previously proposed FPGA implementation.

Efficient FPGA Implementation of Convolutional Neural Networks and Long Short-Term Memory for Radar Emitter Signal Recognition

In recent years, radar emitter signal recognition has enjoyed a wide range of applications in electronic support measure systems and communication security. More and more deep learning algorithms have been used to improve the recognition accuracy of radar emitter signals. However, complex deep learning algorithms and data preprocessing operations have a huge demand for computing power, which cannot meet the requirements of low power consumption and high real-time processing scenarios. Therefore, many research works have remained in the experimental stage and cannot be actually implemented. To tackle this problem, this paper proposes a resource reuse computing acceleration platform based on field programmable gate arrays (FPGA), and implements a one-dimensional (1D) convolutional neural network (CNN) and long short-term memory (LSTM) neural network (NN) model for radar emitter signal recognition, directly targeting the intermediate frequency (IF) data of radar emitter signal for classification and recognition. The implementation of the 1D-CNN-LSTM neural network on FPGA is realized by multiplexing the same systolic array to accomplish the parallel acceleration of 1D convolution and matrix vector multiplication operations. We implemented our network on Xilinx XCKU040 to evaluate the effectiveness of our proposed solution. Our experiments show that the system can achieve 7.34 giga operations per second (GOPS) data throughput with only 5.022 W power consumption when the radar emitter signal recognition rate is 96.53%, which greatly improves the energy efficiency ratio and real-time performance of the radar emitter recognition system.

Designing hardware for a robust high-speed cryptographic key generator based on multiple chaotic systems and its FPGA implementation for real-time video encryption

Recent advancements in communication technologies have highlighted the pivotal role of information security for all individuals and entities. In response, researchers are increasingly focusing on cryptographic solutions to ensure the reliability of confidential information. Recognizing the superiority of chaotic systems preference as entropy source of cryptographic systems, this paper proposes a novel true random number generator (TRNG) design by combining four different chaotic systems outputs, tailored for real-time video encryption application. These chaotic systems are continuous-time Lorenz and fractional-order Chen-Lee systems, as well as discrete-time Logistic and Tent maps. This study generates true random bit (TRB) sequences at a high bit rate (25 Mbps) through the hardware implementations of four distinct chaotic systems to have the best statistical randomness in the resulting output. Then, the cryptographic true random key bits (8-bit at 25 MHz frequency) are employed in the post-processing with real-time video data by using the XOR operation, a fundamental post-processing algorithm. The real-time video encryption application is executed on an experimental assembly, composed of a Field Programmable Gate Array (FPGA) development kit, an OV7670 camera module, a VGA monitor, and prototype circuit boards for the chaotic systems. To evaluate the effectiveness of the proposed encryption system, several security assessments are conducted. These include NIST SP 800 − 22 statistical tests, FIPS 140-1 standards, chi-square tests, histogram and correlation analysis, and NPCR and UACI differential attack resilience tests. Consequently, the findings suggest that the presented real-time embedded cryptosystem is robust and suitable for secure communications, particularly in the realm of video transmission.

Dynamic analysis and FPGA implementation of a 5D multi-wing fractional-order memristive chaotic system with hidden attractors

In this paper, inspired by a 3D multi-wing chaotic system proposed by Sahoo et al. in 2022, we presented a 5D multi-wing fractional-order memristive chaotic system with hidden attractors by increasing dimensionality and introducing memristor. Firstly, the equilibrium point of the 5D fractional-order memristive chaotic system was analyzed, and it was found that it has hidden attractors. The adomian decomposition algorithm was used to decompose the nonlinear term of the system. Then, the dynamic behavior of the system was analyzed using phase diagrams, Lyapunov exponent spectrums, and bifurcation diagrams. The hardware circuit of the 5D multi-wing fractional-order chaotic system was implemented using a field programmable gate array (FPGA) and experimentally verified. The experimental results are consistent with the numerical simulation results in MATLAB. Finally, the good randomness of the system was verified through NIST testing.

FPGA implementation of an improved envelope detection approach for bearing fault diagnosis

This study presents an enhanced envelope detection technique implemented on a field-programmable gate array (FPGA) to diagnose bearing faults in rotating machinery. Bearing faults frequently result in machinery breakdowns, incurring substantial downtime and maintenance expenses. In our approach, we employ the Teager energy operator (TEO) to extract the vibration signal envelope. Subsequently, we subject the envelope signal to the fast Fourier transform (FFT) to generate the envelope spectrum of the vibration signal. Finally, we further refine the envelope spectrum using TEO for a second time, resulting in a pronounced fault peak that facilitates early fault detection. We evaluate the effectiveness and performance of the proposed method using two distinct types of bearing vibration signals, one being simulated and the other measured. Our findings reveal that the suggested approach outperforms traditional envelope detection methods, leading to a substantially enhanced fault diagnosis capability. For instance, when we assess the characteristic frequency ratio (FCFR) for faults in the inner and outer rings of the bearing using the proposed method, we observe that the FCFR values are significantly elevated, ranging from 160 to 330% higher compared to the analysis performed by the TEO and HT methods. Consequently, this indicates that the proposed approach has the ability to detect faults at an earlier stage than other methods. Furthermore, the FPGA-based implementation makes it suitable for critical industrial applications where rapid fault detection is essential to prevent catastrophic failures.

Dynamics analysis, synchronization and FPGA implementation of multiscroll Hopfield neural networks with non-polynomial memristor

The number of attractors in a memristor-based multiscroll Hopfield Neural Network (HNN) is typically coupled with the number of polynomials, which leads to a coupling between the computational complexity and resource utilization in circuit implementation. To decouple this relationship, we propose a non-polynomial memristor that satisfies the Lipschitz condition. Regardless of whether it is used to simulate synaptic behavior, simulate the impact of electromagnetic radiation, or a combination of both scenarios, it can conveniently control the generation of single-direction or multiple-direction multiscroll attractors without adding or reducing any terms. By constructing Lyapunov functions, the sufficient condition for these multiscroll memristor HNNs to be bounded is obtained. After improving the feasibility of linear matrix inequalities, a strongly adaptive observer is proposed. After uniting an adaptive sliding mode control method, we propose a new adaptive synchronization scheme to simulate neural network synchronization. Finally, the digital circuit implementation and functional verification of these memristor-based multiscroll HNNs are completed using a field-programmable gate array (FPGA). Based on this, an image encryption circuit is designed so that the FPGA can directly encrypt images and transmit them to the IO device.

FPGA Implementation of SPI Protocol

Field Programmable Gate Array (FPGA) are versatile devices that can be programmed to implement various digital circuits, including communication protocols like Serial Peripheral Interface (SPI). The Serial peripheral interface protocol is a synchronous serial communication interface that allows for full duplex communication between a master device and a multiple slave MOSI, MISO, SCLK, and SS. MOSI and MISO are data lines, while SCLK is the clock signal generated by the master to synchronize transfers. SS is used by the master to select individual slave devices. By implementing the SPI protocol in FPGA, to gain flexibility and customization, as FPGAs can be reprogrammed for different applications without the need for dedicated hardware changes. The FPGA implementation of the Serial Peripheral Interface (SPI) protocol involves a structured methodology. With the help of pipeline buffer and DAM technique power dissipation is performed effectively. Finally, integrate the FPGA SPI module into the larger system, ensuring seamless communication with other components or microcontrollers. This systematic approach ensures a reliable and tailored FPGA based SPI implementation.

Review on FPGA Implementation of CORDIC Algorithm

The Coordinate Rotation Digital Computer (CORDIC) algorithm has emerged as a pivotal method for executing trigonometric and various mathematical operations within digital systems. Field-Programmable Gate Arrays (FPGAs) have witnessed a remarkable surge in adoption for implementing the CORDIC algorithm owing to their inherent flexibility and exceptional performance capabilities. This paper endeavours to provide a comprehensive overview of FPGA implementations of the CORDIC algorithm, elucidating both the advantages and challenges associated with this methodology. It thoroughly examines various FPGA architectures customized for CORDIC implementation, meticulously analyzing their respective trade-offs regarding resource utilization, performance metrics, and accuracy levels. Moreover, the paper explores numerous applications where the FPGA-based CORDIC algorithm shines, illustrating its adaptability across diverse domains like digital signal processing and control systems. These applications underscore the algorithm's efficacy in addressing real-world challenges and its potential to significantly augment system performance and efficiency.By furnishing profound insights into FPGA-based CORDIC implementations, this paper serves as an invaluable resource for engineers and researchers keen on harnessing the capabilities of FPGAs for high-performance mathematical computations in digital systems.

MBIST Implementation and Evaluation in FPGA Based on Low-Complexity March Algorithms

March algorithms are widely used in Memory Built-In Self-Test (MBIST) on-chip memory testing, providing linear test complexities that reduce the test time and cost. However, studies show that March algorithms with complexities lower than 18N have poor coverages of faults that have emerged with the advent of the nanometer process technologies and are more relevant to nowadays memories. New March AZ1 and March AZ2 algorithms, with 13N and 14N complexities, respectively, were introduced to provide optimum coverage of those faults and to produce a shorter test than an 18N-complexity test algorithm with a lesser area overhead, thus reducing chip manufacturing costs. This paper presents the implementation and validation of MBIST controllers that applied the March AZ1 and March AZ2 algorithms in a Field-Programmable Gate Array (FPGA) device. They were implemented in the Intel Max 10 DE10-Lite FPGA Development Board. A test generator was built in FPGA, as an alternative to the external tester, to provide test vectors required in initiating the test on the memory model using the implemented MBIST. The FPGA experimental tests demonstrated that they function correctly as the expected test sequences were observed. In addition, their fault detection abilities were also validated through tests on a fault-injected memory model, which shows that the implemented March AZ1 and March AZ2 provide 80.6% and 83.3% coverage of the intended faults, respectively, which outperform any other existing 14N-complexity March algorithms.

FPGA implementation in mobile robot applications: State of the art review

Field-programmable gate arrays (FPGAs) have emerged as a valuable technology in mobile robotics due to their unique ability to be reconfigured to perform specific tasks efficiently. This article presents a comprehensive state-of-the-art review of the implementations of FPGAs in mobile robots. The article explores the various applications where FPGAs have been successfully integrated and discuss their advantages and limitations. The review covers vital areas such as perception, control, navigation, and communication, highlighting each domain's innovative approaches and advancements. Additionally, the study examines FPGAs' impact on mobile robot performance, including improvements in real-time processing, energy efficiency, and adaptability to changing environments. Furthermore, challenges and current efforts in leveraging FPGAs for mobile robotics are discussed, paving the way for exciting developments and possibilities in this rapidly evolving field. This review is a valuable resource for researchers, engineers, and enthusiasts interested in understanding the state of the art and potential of FPGA implementations in mobile robots.

Memristor-induced hyperchaos, multiscroll and extreme multistability in fractional-order HNN: Image encryption and FPGA implementation

Fractional-order differentiation (FOD) can record information from the past, present, and future. Compared with integer-order systems, FOD systems have higher complexity and more accurate ability to describe the real world. In this paper, two types of fractional-order memristors are proposed and one type is proved to have extreme multistability, local activity, and non-volatility. By using memristors to simulate the autapse of a neuron and to describe the phenomenon of electromagnetic induction caused by electromagnetic radiation, we establish a new 5D FOD memristive HNN (FOMHNN). Through dynamic simulation, rich dynamic behaviors are found, such as hyperchaos, multiscroll, extreme multistability, and “overclocking” behavior caused by order reduction. To the best of our knowledge, this is the first time that such rich dynamic behaviors are found in FOMHNN simultaneously. Based on this FOMHNN, a very efficient and secure image encryption scheme is designed. Security analysis shows that the encrypted Lena image has extremely low adjacent pixel correlation and high randomness, with information entropy of 7.9995. Despite discarding diffusion and scrambling, it has excellent plaintext sensitivity, with NCPR = 99.6095% and UACI = 33.4671%. Finally, this paper implements the proposed FOMHNN and image encryption on field programmable gate array (FPGA). To our knowledge, the related work of fully hardware implementation of fractional-order neural networks and image encryption schemes based on this is rare.

GPU versus FPGA implementation of a digital predistortion linearizer for wideband radiofrequency power amplifiers

This paper presents and compares the implementation of a digital predistortion (DPD) linearizer for radiofrequency power amplifiers (PAs) considering two different hardware acceleration platforms. Both graphics processing unit (GPU)-based and field programmable gate arrays (FPGA)-based implementations of the DPD are capable to meet the high throughput requirements for linearizing the PA with current 5G new radio (NR) wideband signals. A comparison in terms of hardware resources usage, precision, throughput and linearization performance is provided for both GPU and FPGA implementations of a DPD based on the generalized memory polynomial (GMP) behavioral model.

CNN inference acceleration on limited resources FPGA platforms_epilepsy detection case study

<span lang="EN-US">The use of a convolutional neural network (CNN) to analyze and classify electroencephalogram (EEG) signals has recently attracted the interest of researchers to identify epileptic seizures. This success has come with an enormous increase in the computational complexity and memory requirements of CNNs. For the sake of boosting the performance of CNN inference, several hardware accelerators have been proposed. The high performance and flexibility of the field programmable gate array (FPGA) make it an efficient accelerator for CNNs. Nevertheless, for resource-limited platforms, the deployment of CNN models poses significant challenges. For an ease of CNN implementation on such platforms, several tools and frameworks have been made available by the research community along with different optimization techniques. In this paper, we proposed an FPGA implementation for an automatic seizure detection approach using two CNN models, namely VGG-16 and ResNet-50. To reduce the model size and computation cost, we exploited two optimization approaches: pruning and quantization. Furthermore, we presented the results and discussed the advantages and limitations of two implementation alternatives for the inference acceleration of quantized CNNs on Zynq-7000: an advanced RISC machine (ARM) software implementation-based ARM, NN, software development kit (SDK) and a software/hardware implementation-based deep learning processor unit (DPU) accelerator and DNNDK toolkit.</span>

Design and FPGA Implementation of Compensator for Sharpening CIC Filter

This paper presents a novel compensator design for sharpened CIC (cascade-integrator-comb) proposed in the literature. Sharpened CIC provides higher aliasing attenuation than the CIC filter. However, its passband droop is higher than the corresponding CIC filter and must be compensated. Our motivation was to design a decimator with better compensation than the one proposed in the literature. The proposed decimation filter has two coefficients and six adders. The coefficients are determined using particle swarm optimization (PSO) in MATLAB. Two designs are presented. The first one has two multipliers and six adders. The second is a multiplierless design obtained by presenting optimal coefficients in the signed power-of-two (SPT) form. The proposed design is compared with the design from the literature. The designed compensator is implemented in a field-programmable gate array (FPGA). Details of the implementation are described in the paper.

A status pre-matching method for the real-time simulation of power electronic converters

The inherent iterative problem limits the applicability of the resistance switch model in real-time simulation (RTS) for power electronic converters (PECs). This paper presents a status pre-matching method (SPM) that eliminates the iterative calculations for resistance switch model. The switch status can be easily and accurately determined by using gating signals and matching the switch resistances to the sign of the switch voltages. SPM can simulate all operation modes of PECs through a more convenient approach. Furthermore, a field programmable gate array (FPGA) implementation scheme is proposed to fully utilize the multiplier units of FPGA. Finally, a three-phase back-to-back converter (3-ph BTBC) with 25 ns simulation time-step, 10 kHz switching frequency, as well as an LLC resonant converter with 17.2 ns simulation time-step, 100 kHz switching frequency, are implemented on FPGA. The results demonstrate the effectiveness and ability to reduce hardware resource consumption for SPM-based models.

LabPET II scanner performances improvement: Thermal stability control based on FPGA

The LabPET II detection module serves as the fundamental component within Positron Emission Tomography (PET) scanners designed for achieving ultra-high-resolution imaging of small to medium-sized animals as well as the human brain. To ensure peak performance, it is imperative that this module operates consistently at a stable temperature. In this paper, we present an automatic and real-time method to improve the thermal control of the scanner LabPET II by evacuating the heat to reduce the overall temperature and maintain the thermal stability of the system. Based on the Thermo-Electric Cooler (TEC) process, our method applies two numerical techniques, Computational Fluid Dynamics (CFD) and Heat Transfer Analysis (HTA). The Dirichlet Boundary Conditions (DBC) method is applied for the Application-Specific Integrated Circuit (ASIC) at 25∘ C. The real measurements confirm and validate the simulation results with the Finite Element Method (FEM) based on the software COMSOL Multiphysics™. Field-Programmable Gate Array (FPGA) implementation on the Development and Education (DE1) board is performed with comparative results study. The proposed method is both simple and practical, and ensures thermal stability at 35∘C for the duration of operation of the scanner, which has a complex structure.

A compact and efficient AES-32GF for encryption in small IoT devices

The phenomenal growth of resource constrained devices in IoT set ups has motivated the researchers to develop solutions for securing information flow. In this paper, we present a compact and efficient field programmable gate array (FPGA) implementation of AES with 32-bit data-path named, AES-32GF. The implementation is carried out on different Xilinx FPGAs. In FPGAs, utilization of slices and look up tables (LUTs) reflect on the compactness of the design. Numerical results show that lesser resources are required with smaller data path in comparison with the original standard. With the help of data path compression and Galois field implementation of the s-box resource consumption is minimized. S-box is the most resource consuming component in the AES structure. In our implementation, Artix-7 series FPGA for the same. It results in significant resource savings. In comparison to unrolled AES-128 architecture, it achieves 87 % resource savings. With 595 slices and 2.004 Gbps throughput, AES-32GF cipher achieves an efficiency of 3.37 Mbps/slice. It outperforms other designs in terms of efficiency.•A compact and efficient FPGA implementation of AES with 32-bit data-path has been proposed.•The proposed design utilizes data path compression and Galois field implementation of the s-box to minimize resource consumption.•With 595 slices and 2.004 Gbps throughput, AES-32GF cipher achieves an efficiency of 3.37 Mbps/slice.

Place-and-Route Analysis of FPGA Implementation of Nested Hardware Self-Organizing Map Architecture

Self-organizing map (SOM) is a type of artificial neural network that provides a nonlinear mapping from a given high-dimensional input space to a low-dimensional map of neurons for clustering. The clustering of high-dimensional vectors is too slow for SOM when implemented in software. In such cases, an application-specific hardware SOM accelerator is highly desirable. Field-programmable gate array (FPGA) implementation is a popular platform to implement hardware SOM. In our previous work, a nested hardware SOM architecture, which has a homogeneous modular structure to enhance expandability, was proposed. This paper investigates the impact of the nested hardware SOM on FPGA implementation tools that perform logic synthesis, place, and route (PAR). Experiments revealed that the nested architecture provided better results in resource usage and performance. FPGA resource usage of the nested architecture was 97.2% of that of the flat design on average. Importantly, the nested architecture operated at 10% higher clock frequencies compared to flat SOM designs. In addition, the pipeline computation was improved by increasing the pipeline stages so that it operates with a higher clock frequency. The operable clock frequency was 81 MHz, which was 21 MHz higher than its predecessor.

FPGA Implementation of a Phase Optimizer-Assisted PTS Scheme for PAPR Reduction in OFDM Systems

This article proposes a phase optimizer-assisted partial transmit sequence (PO-PTS) for minimizing PAPR values in OFDM systems. The novel PO-PTS scheme after validation, based on simulation results, is implemented using a Xilinx system generator on a field programmable gate array (FPGA). The phase optimizer (PO) module is employed to select optimal phase weighting factors to perform scaling with the data sequence in the PTS scheme. The computational complexity and the redundancy involved in producing the candidate signals are significantly reduced by the PO-PTS compared with the conventional PTS method. The proposed method reduces PAPR for a QPSK-OFDM signal by 56.16% compared to the original OFDM signal without compromising on the bit error rate (BER) performance. In addition, the performance of PO-PTS in terms of PAPR reduction for 32-QAM and 64-QAM modulated OFDM systems is also presented to justify the robustness of the proposed scheme. Moreover, when PO-PTS is implemented using FPGA, it uses only 1% of the hardware available in Virtex.