Field Programmable Gate Array Implementation Research Articles

Implementation of an FPGA-Based System to Process Images and Match Keypoints on High-Resolution Pictures

Processing scenery and finding points of interest is crucial for applications in robotics and aerospace missions. Those areas require efficient and reliable visual input processing. Here, field programmable gate arrays (FPGAs) offer essential advantages, like low power consumption compared to CPUs, performing a large number of calculations simultaneously, and having compact hardware. This paper presents an FPGA system that processes incoming camera data, finds points of interest, and matches them across different images on high-resolution images (2048 × 1088). It is a novel approach to implement the complete image processing pipeline on high-resolution images within the FPGA fabric without additional hardware. For keypoint detection and matching, our work uses a modified SIFT algorithm optimized for FPGA implementation processing and a nearest neighbor-based matching method. It was implemented on a Xilinx Kintex-7 FPGA and partially on a NanoXplore NG-Ultra to evaluate a radiation-hardened FPGA for space applications. On the Kintex-7, the keypoint detection achieves a speed of 33 ms per image, and its features are matched on up to 5 images per second. Judging by the resource utilization of one image processing module on the NG-Ultra, porting the entire system on a radiation-hardened FPGA appears feasible.

Complex Periodic Motions and Bifurcations of a Forced Duffing Oscillator with Its Field-Programmable Gate Arrays Implementation

The dynamical behavior of a Duffing oscillator under periodic excitation is investigated using semi-analytical methods. Bifurcation trees with varying periodic excitation are constructed. The stability, saddle-node bifurcation and period-doubling bifurcation are revealed by assessing the eigenvalue of the model. From the bifurcation trees, we observed that saddle-node and period-doubling bifurcations occur when the excitation frequency and excitation amplitude vary to an appropriate value. The generation of periodic-doubling bifurcation leads to a change in the periodicity of periodic motion. The relationships among periodic-m motions are interconnected yet independent of each other. To satisfy the need of parameter selection for FPGA circuits, a dual-parameter map is calculated to study the periodic characteristics. Then, an FPGA circuit model is designed and implemented. The results show that the phase trajectory and waveform of the FPGA hardware circuit match the numerical model.

Design and FPGA Implementation of a Hyper-Chaotic System for Real-time Secure Image Transmission

Recently, chaos theory has been widely used in multimedia and digital communications due to its unique properties that can enhance security, data compression, and signal processing. It plays a significant role in securing digital images and protecting sensitive visual information from unauthorized access, tampering, and interception. In this regard, chaotic signals are used in image encryption to empower the security; that's because chaotic systems are characterized by their sensitivity to initial conditions, and their unpredictable and seemingly random behavior. In particular, hyper-chaotic systems involve multiple chaotic systems interacting with each other. These systems can introduce more randomness and complexity, leading to stronger encryption techniques. In this paper, Hyper-chaotic Lorenz system is considered to design robust image encryption/ decryption system based on master-slave synchronization. Firstly, the rich dynamic characteristics of this system is studied using analytical and numerical nonlinear analysis tools. Next, the image secure system has been implemented through Field-Programmable Gate Arrays (FPGAs) Zedboard Zynq xc7z020-1clg484 to verify the image encryption/decryption directly on programmable hardware Kit. Numerical simulations, hardware implementation, and cryptanalysis tools are conducted to validate the effectiveness and robustness of the proposed system.

FPGA Realization of an Image Encryption System Using a 16-CPSK Modulation Technique

Nowadays, M-Quadrature Amplitude Modulation (M-QAM) techniques are widely used to modulate information by bit packets due to their ability to increase transfer rates. These techniques require more power when increasing the modulation index M to avoid interference between symbols. This article proposes a technique that does not suffer from interference between symbols, but instead uses memory elements to store the modulation symbols. In addition, the aim of this paper is to implement a four-dimensional reconfigurable chaotic oscillator that generates 16-Chaotic Phase Shift Keying (16-CPSK) modulation–demodulation carriers. An encryption and modulation transmitter module, a reception module, and a master–slave Hamiltonian synchronization module make up the system. A 16-CPSK modulation scheme implemented in Field Programmable Gate Array (FPGA) and applied to a red-green-blue (RGB) and grayscale image encryption system are the main contributions of this work. Matlab and Vivado were used to verify the modulation–demodulation scheme and synchronization. This proposal achieved excellent correlation coefficients according to various investigations, the lowest being −15.9×10−6 and 0.13×10−3 for RGB and grayscale format images, respectively. The FPGA implementation of the 16-CPSK modulation–demodulation system was carried out using a manufacturer’s card, Xilinx’s Artix-7 AC701 (XC7A200TFBG676-2).

Machine learning and FPGA implementation for predicting luminance decay and temperature distribution in micro-LED displays

AbstractA machine learning-based method predicts the luminance decay of micro light emitting diode (micro-LED) displays, utilizing temperature distribution and degradation experiments alongside implementation on field-programmable gate array (FPGA). Micro-LEDs, used in outdoor and indoor billboards, experience degradation due to harsh environmental conditions. To model temperature distribution in indoor advertising displays using minimal data, a temperature model is constructed based on sensor from the panel and thermal images captured by a camera, in relation to the display pattern. The input data is processed using an FPGA, which transmits the sensed temperatures and display patterns to the micro-LED panel. Multilayer Perceptron (MLP), a type of neural network, predicts the temperature distribution over the panel surface, achieving an error of less than 1.1 °C. Separate degradation models forecast luminance decay, factoring in enclosure temperature, input current, and usage time, with distinct models for red, green, and blue LEDs. Exponential curve-fitting and interpolation, following TM-21 standards, ensure long-term accuracy. The luminance decay predictions have an average error below 1.05% (approximately 9 nits). The FPGA implementation minimizes resource consumption while maintaining prediction accuracy, making it suitable for real-time applications. The degradation model accurately predicts performance over tens or even hundreds of thousands of hours, aligning with the exponential decay trends defined by TM-21.

Dynamic Analysis and FPGA Implementation of Fractional-Order Hopfield Networks with Memristive Synapse

Memristors have become important components in artificial synapses due to their ability to emulate the information transmission and memory functions of biological synapses. Unlike their biological counterparts, which adjust synaptic weights, memristor-based artificial synapses operate by altering conductance or resistance, making them useful for enhancing the processing capacity and storage capabilities of neural networks. When integrated into systems like Hopfield neural networks, memristors enable the study of complex dynamic behaviors, such as chaos and multistability. Moreover, fractional calculus is significant for their ability to model memory effects, enabling more accurate simulations of complex systems. Fractional-order Hopfield networks, in particular, exhibit chaotic and multistable behaviors not found in integer-order models. By combining memristors with fractional-order Hopfield neural networks, these systems offer the possibility of investigating different dynamic phenomena in artificial neural networks. This study investigates the dynamical behavior of a fractional-order Hopfield neural network (HNN) incorporating a memristor with a piecewise segment function in one of its synapses, highlighting the impact of fractional-order derivatives and memristive synapses on the stability, robustness, and dynamic complexity of the system. Using a network of four neurons as a case study, it is demonstrated that the memristive fractional-order HNN exhibits multistability, coexisting chaotic attractors, and coexisting limit cycles. Through spectral entropy analysis, the regions in the initial condition space that display varying degrees of complexity are mapped, highlighting those areas where the chaotic series approach a pseudo-random sequence of numbers. Finally, the proposed fractional-order memristive HNN is implemented on a Field-Programmable Gate Array (FPGA), demonstrating the feasibility of real-time hardware realization.

Ponte: Represent Totally Binary Neural Network Toward Efficiency

In the quest for computational efficiency, binary neural networks (BNNs) have emerged as a promising paradigm, offering significant reductions in memory footprint and computational latency. In traditional BNN implementation, the first and last layers are typically full-precision, which causes higher logic usage in field-programmable gate array (FPGA) implementation. To solve these issues, we introduce a novel approach named Ponte (Represent Totally Binary Neural Network Toward Efficiency) that extends the binarization process to the first and last layers of BNNs. We challenge the convention by proposing a fully binary layer replacement that mitigates the computational overhead without compromising accuracy. Our method leverages a unique encoding technique, Ponte::encoding, and a channel duplication strategy, Ponte::dispatch, and Ponte::sharing, to address the non-linearity and capacity constraints posed by binary layers. Surprisingly, all of them are back-propagation-supported, which allows our work to be implemented in the last layer through extensive experimentation on benchmark datasets, including CIFAR-10 and ImageNet. We demonstrate that Ponte not only preserves the integrity of input data but also enhances the representational capacity of BNNs. The proposed architecture achieves comparable, if not superior, performance metrics while significantly reducing the computational demands, thereby marking a step forward in the practical deployment of BNNs in resource-constrained environments.

A novel adaptive parameter zeroing neural network for the synchronization of complex chaotic systems and its field programmable gate array implementation

This article proposes a novel adaptive-parameter zeroing neural network (NAP-ZNN) to control the synchronization of complex chaotic systems. Different from previous zeroing neural networks (ZNNs), the NAP-ZNN model incorporates adaptive-parameter, a unique blend of time-varying convergence factor and fuzzy control parameter, which is adjusted continuously according to the real-time synchronizing error, offering greater flexibility. The NAP-ZNN model aims to address the time-varying problem in complex-valued domain, which is scarcely explored, it rapidly impels two complex chaotic systems to synchronize within predetermined time and effectively mitigates noise interference. Moreover, the upper bound of the convergence time is theoretically calculated in noiseless environments, and the disturbance-resistant property is demonstrated under various noisy disturbances. The control performance of NAP-ZNN model has been separately compared to other general ZNNs (NAP-ZNN synchronizes at 0.097 s while three general ZNNs spend 0.43 s, 0.78 s and 0.84 s, and only NAP-ZNN complete synchronization within 0.1 s under noisy interferences while general ZNNs fail) and the traditional adaptive control method through two synchronization simulation (RMSE of NAP-ZNN under sinusoidal noise is 3.165 × 10-3 while traditional is 3.383 at t = 1 s). The numerical outcomes clearly illustrate the superior performance of the NAP-ZNN model in comparison to other synchronization strategies. The hardware implementation of the NAP-ZNN model has been successfully realized through the Field Programmable Gate Array (FPGA), and the chaos synchronization process has been vividly captured via an oscilloscope, further reinforcing the practicality and effectiveness of the NAP-ZNN model.

All-to-all reconfigurability with sparse and higher-order Ising machines

Domain-specific hardware to solve computationally hard optimization problems has generated tremendous excitement. Here, we evaluate probabilistic bit (p-bit) based Ising Machines (IM) on the 3-Regular 3-Exclusive OR Satisfiability (3R3X), as a representative hard optimization problem. We first introduce a multiplexed architecture that emulates all-to-all network functionality while maintaining highly parallelized chromatic Gibbs sampling. We implement this architecture in a single Field-Programmable Gate Array (FPGA) and show that running the adaptive parallel tempering algorithm demonstrates competitive algorithmic and prefactor advantages over alternative IMs by D-Wave, Toshiba, and Fujitsu. We also implement higher-order interactions that lead to better prefactors without changing algorithmic scaling for the XORSAT problem. Even though FPGA implementations of p-bits are still not quite as fast as the best possible greedy algorithms accelerated on Graphics Processing Units (GPU), scaled magnetic versions of p-bit IMs could lead to orders of magnitude improvements over the state of the art for generic optimization.

BIDS: An efficient Intrusion Detection System for in-vehicle networks using a two-stage Binarised Neural Network on low-cost FPGA

Automotive networks are crucial for ensuring safety as the number of Electronic Control Units (ECUs) grows to support vehicle intelligence. The Controller Area Network (CAN) is commonly used for efficient in-vehicle communication among ECUs. However, its broadcast nature and lack of a dedicated security layer make it vulnerable to attacks. This paper proposes a novel CAN bus Intrusion Detection System (IDS), named BNN-based IDS (BIDS), which efficiently provides both unknown attack detection and known attack classification using a hierarchical two-stage Binarised Neural Network (BNN) and Generative Adversarial Network (GAN). BIDS was validated on three datasets, and its implementation achieves an average inference time of less than 0.170 ms with minimal resource utilisation on a low-cost Field Programmable Gate Array (FPGA). This rapid inference speed enables real-time inference on individual CAN messages using a sliding window technique, eliminating the need to wait for multiple accumulated CAN messages required for data preprocessing. Evaluation metrics demonstrate that our IDS achieves high accuracy in both identifying unseen attacks and categorising known attacks. Furthermore, our FPGA implementation consumes merely 2.09 W, which is a 57% reduction compared to a cutting-edge FPGA-based IDS that is capable of detecting unknown attacks using the same dataset.

DEAC-IoT: Design of lightweight authenticated key agreement protocol for Intra and Inter-IoT device communication using ECC with FPGA implementation

The growing reliance on wireless communication in Internet-of-Things (IoT) devices highlights the critical need for secure and efficient communication protocols, especially in environments vulnerable to cyber threats. Existing IoT protocols often lack sufficient security, creating a need for robust authentication and key exchange mechanisms that can resist attacks while maintaining low computational overhead. In this paper, we propose a fog-enabled network architecture integrated with IoT devices (Intra and Inter IoT device) and develop the DEAC-IoT scheme using Elliptic Curve Cryptography (ECC) for secure authentication and key agreement. Our protocol is designed to protect device-to-device communication from security threats in resource-constrained IoT environments. We validate DEAC-IoT’s security through both informal analysis and formal verification using the Real-Or-Random (RoR) model, demonstrating its resistance to major attacks. Simulation via the Scyther tool confirms that private parameters remain secure throughout the protocol’s execution. For practical feasibility, we implement DEAC-IoT on a Field Programmable Gate Array (FPGA) and conduct performance evaluations. The results show that our protocol surpasses existing protocols in both computational and communication efficiency, making it highly suitable for real-world IoT applications.

Robust fuzzy controller design with FPGA implementation for matrix converter based induction motor drive

This paper aims to design a controller for a matrix converter fed induction motor drive providing less torque ripples and eliminating peak overshoots with good transient and steady state responses utilizing fuzzy and direct torque control. The proposed controller utilizes Direct Torque Control (DTC) strategy with space vector modulation for regulating stator flux and electromagnetic torque. Due to the superior control capabilities of the matrix converter such as bidirectional power flow, sinusoidal input/output waveforms, high power density and lesser volume, it has attracted significant research interest in the field of adjustable speed drive. Hence the proposed matrix converter based controller is developed in MATLAB/Simulink and tested in different input/output conditions. To validate simulation results, a laboratory prototype is built around the Altium Nano Board 3000 equipped with a Xilinx Spartan using Field Programmable Gate Array (FPGA) is employed. The proposed control scheme, validated through simulation and hardware testing, ensures stable, robust drive system with significant reductions in input side harmonics and enhances induction motor drive's performance.

Dynamics analysis and FPGA implementation of discrete memristive cellular neural network with heterogeneous activation functions

The activation function, as an important component of artificial neural networks, endows neural networks with rich dynamical phenomena by virtue of its nonlinear properties. However, especially for cellular neural networks (CNNs), the exploration of neural networks consisting of heterogeneous activation functions has not been sufficient. In this article, we introduce heterogeneous activation functions in discrete cellular neural network (DCNN) for the first time. In order to enhance the dynamics of the original DCNN, we propose our discrete memristive cellular neural network (DMCNN) based on a memristor with a sinusoidal function. Using various methods of dynamical characterization, such as Lyapunov exponential analysis, bifurcation diagrams and spectral entropy, the rich dynamical behaviour of the proposed model is comprehensively investigated, including hyperchaos, transient chaos, high spectral entropy and multiple types of coexisting attractors in the proposed model. Last but not least, the hardware platform of the proposed model is implemented by field programmable gate array (FPGA), and the dynamics of the proposed model is verified by a combination of software simulation and hardware experiments. The new exploration of DMCNN with heterogeneous activation functions in this article lays the foundation for further research into neural networks with complex dynamical behaviour.

Methodology of deployment of dependable FPGA based artificial intelligence as a service

The subject of study in this article is the models, methods, and principles of organization of entire lifecycle of Artificial Intelligence (AI) as a Service implemented with the use of Field Programmable Gate Array (FPGA). The purpose of this work is the improvement of the methodology of the deployment of dependable FPGA-based Artificial Intelligence as a Service by creating a complex of mutually agreed concept, principles, models, and methods considering the specifics of the use of heterogeneous computations of Artificial Intelligence and the possibility of realizing the unified protection of FPGA implementations. Tasks: to clarify the taxonomy of the dependability term within the proposed methodology; to propose the concept of deployment of dependable FPGA-based heterogeneous computations of Artificial Intelligence as a Service; to formulate the principle of tracing changes in FPGA projects and integrated environments during the entire lifecycle; to formulate the principle of unification of protection of FPGA implementations of heterogeneous computing of Artificial Intelligence as a Service; to formulate the principle of the product-service assessment of the availability of FPGA as a Service; and to discuss the promising directions of heterogeneous computations of AI. According to the tasks, the following results were obtained. The existing concepts of dependable systems deployment are discussed. The concept of the deployment of computations of Artificial Intelligence as a Service, which is obtained based on the improvement of paradigms of the creation and deployment of dependable systems and services, is proposed. The principle of tracing of changes, which assumes the updating of requirements during the lifecycle of FPGA projects, is proposed. The principle of the unification of protection, which combines and joins the consideration of various unique features of the FPGA instance to protect the implementation and the set of cyberthreats for the service as a whole, is proposed. The principle of the product-service assessment, which considers parameters and indicators of availability, is proposed. The perspective of the progress of non-electronic mediums for heterogeneous computations with the use of a photonic implementations of Artificial Intelligence computations to ensure improved performance and reduced energy consumption is discussed. Conclusions. One of the main contributions of this research is that in the proposed methodology, the set of principles, models, and methods of deployment of Artificial Intelligence as a Service under conditions of changing requirements and integrated environments, and the need for mechanism of licensing protection of each instance of the system are developed, which allows to reduce model uncertainty by considering various stages of the lifecycle of dependable FPGA implementation using heterogeneous computations.

FPGA implementation of power-lite Volterra-inspired neural network equalizer in 180-Gb/s net bitrate IMDD short-reach optical system.

A white-box power-lite Volterra-inspired neural network (VINN) equalizer is proposed to solve the problem of complexity discontinuity in a Volterra nonlinear equalizer (VNLE). By adjusting the granularity of the solution space, it conserves computational resources while maintaining nonlinear compensation capability. The performance of VINN is verified on a field-programmable gate array (FPGA) in a short-reach intensity modulation and direct detection (IMDD) system, and a 240-Gb/s real-time signal processing rate is achieved. Under the 25% overhead soft-decision forward error correction (SD-FEC) bit error rate (BER) threshold, we realize a record net rate of up to 180 Gb/s based on the FPGA.

A triangular-trapezoidal dual-channel shaping algorithm for resistive anode readout systems and its FPGA implementation.

This paper introduces a novel digital triangular-trapezoidal double-channel shaping algorithm to enhance the counting rate of resistive anode detectors. The algorithm is based on the trapezoidal shaping algorithm and improves it. At the extreme counting rate, the trapezoidal shaping algorithm cannot alleviate the pulse pileup, so the counting rate cannot meet the requirements of a high performance detector. The triangular-trapezoidal double-channel shaping algorithm is introduced in the resistance anode detector, which can replace the trapezoidal shaping filtering algorithm to process the output signal of the resistance anode detector and obtain the single photon position information. This improvement improves the counting rate of the resistor anode detector and reduces the resolution degradation caused by pulse pileup. The algorithm is simulated by System Generator software and implemented on FPGA (field programmable gate array). The triangular-trapezoidal double-channel shaping algorithm presented in this paper plays an important role in reducing electronic noise and pulse pileup. The algorithm is subjected to simulation testing, and it can recognize signals with a minimum pulse interval of 1 µs and counting rate up to 1000 kcps.

Field-programmable gate array implementation of efficient deep neural network architecture

Deep neural network (DNN) comprises multiple stages of data processing sub-systems with one of the primary sub-systems is a fully connected neural network (FCNN) model. This fully connected neural network model has multiple layers of neurons that need to be implemented using arithmetic units with suitable number representation to optimize area, power, and speed. In this work, the network parameters are analyzed, and redundancy in weights is eliminated. A pipelined and parallel structure is designed for the fully connected network information. The proposed FCNN structure has 16 inputs, 3 hidden layers, and an output layer. Each hidden layer consists of 4 neurons and describes how the inputs are connected to hidden layer neurons to process the raw data. A hardware description language (HDL) model is developed for the proposed structure and the verified model is implemented on Xilinx field-programmable gate array (FPGA). The modified structure comprises registers, demultiplexers, weight registers, multipliers, adders, and read-only memory lookup table (ROM/LUT). The modified architecture implemented on FPGA is estimated to reduce area by 87.5% and improve timing by 3x compared with direct implementation methods.

FPGA implementation of automatic seizure detection in EEG signals using machine learning algorithm

This work presents a novel approach that harnesses the capabilities of field programmable gate arrays (FPGA) to enable instantaneous monitoring of electroencephalography (EEG) signals for the detection and prediction of seizure patterns. The integration of FPGA technology with the perceptron learning algorithm holds promises for enhancing real-time healthcare monitoring systems and contributing to improved patient care and safety. The proposed work addresses the challenges presented at predicting seizures from EEG data. The first challenge is to handle massive EEG data that poses memory issues. To tackle this, the research employs cellular automata (Rule 90 and Rule 150) to reduce data size by 85.71%, making it more manageable. The second is to implement a linearly classified perceptron algorithm using FPGA to predict and detect seizures from real-time EEG data. The third is clock synchronization between stored data and real EEG data for comparison purposes. The proposed system is continuously compared to real-time EEG signals using a single perceptron neural network, and alert signals are generated based on preactivation values, with a continuous alert issued when the value reaches 3/4th sample match. These early alerts empower individuals to take preventive actions. The model is implemented using an FPGA Zynq-7000 series, which consumes 270mW of power. The design utilizes 118 Lookup Tables (LUTs).

A novel fractional-order memristive Hopfield neural network for traveling salesman problem and its FPGA implementation

This paper proposes a novel fractional-order memristive Hopfield neural network (HNN) to address traveling salesman problem (TSP). Fractional-order memristive HNN can efficiently converge to a globally optimal solution, while conventional HNN tends to become stuck at a local minimum in solving TSP. Incorporating fractional-order calculus and memristors gives the system long-term memory properties and complex chaotic characteristics, resulting in faster convergence speeds and shorter average distances in solving TSP. Moreover, a novel chaotic optimization algorithm based on fractional-order memristive HNN is designed for the calculation process to deal with mutual constraint between convergence accuracy and convergence speed, which circumvents random search and diminishes the rate of invalid solutions. Numerical simulations demonstrate the effectiveness and merits of the proposed algorithm. Furthermore, Field Programmable Gate Array (FPGA) technology is utilized to implement the proposed neural network.

FPGA implementation and measurement of cusp-flattop hybrid filter shaping method for nuclear instruments

In the field of nuclear technology applications, digital multi-channel pulse amplitude analysis technology plays an indispensable role in information acquisition due to its high precision and sensitivity. However, the challenge of pulse pileup can compromise the accuracy of measurement results in this technology. While conventional filter shaping and pulse pileup processing methods can extract nuclear pulse feature information under mild pileup conditions, severe pileup can notably degrade spectral counting rate and resolution. This paper introduces a designed two-channel pulse pileup rejection method, termed the cusp-flattop hybrid filter forming algorithm, leveraging the unique features of cusp, such as high forming speed and minimal interference from pulse pileup. The two channels simultaneously process the collected signals and utilize their differences for data filtering and rejection. This approach enhances information content, improves data processing quality, and boosts the signal-to-noise ratio. Compared to three methods—three trapezoidal filter shaping algorithms, the triangle trapezoidal pulse shaping algorithm, and the pulse width discrimination algorithm—our proposed method refines the shaping threshold of pulse pileup rejection. It accurately distinguishes and extracts effective pulse amplitudes even under severe pileup conditions, generating energy spectrum results while accounting for counting rate and resolution. Building on this, we construct a digital multichannel pulse amplitude analysis system based on FPGA (Field Programmable Gate Array) and use a national standard alloy sample, YSBS41346, for testing. The system can generate energy spectrum correctly, consistent with the actual sample content. We evaluate the system's performance by comparing the peak counting rate and resolution of the energy spectrum generated by the cusp-flattop hybrid filter forming algorithm and the trapezoidal forming algorithm. A high peak counting rate represents the maximum nuclear pulse data captured by the system, while low resolution indicates more valid data after pileup rejection. Through testing, the peak counting rate reaches 12843cps, with a resolution of 6.68%, marking a significant improvement over the trapezoidal pulse forming algorithm. The system demonstrates satisfactory performance and operational effectiveness, aligning with the design objectives and presenting innovative and practical applications.