FPGA implementation of joint synchronization algorithm based on short training sequence

Abstract

Synchronization processing is a vital component of the Orthogonal Frequency Division Multiplexing (OFDM) receiver, playing a decisive role in determining the performance of the OFDM receiver. Based on the repetitive structure of the Short Training Sequence (STS) in the IEEE 802.11 physical layer protocol data unit, this paper proposes and implements a joint synchronization algorithm to address issues related to data packet detection and coarse frequency offset correction during the synchronization process. Through software simulation and Field-Programmable Gate Array (FPGA) board-level validation, it is concluded that the algorithm ensures performance while, to some extent, conserving FPGA resources.