Field Programmable Gate Array Development Research Articles

Timing and triggering of the Thomson scattering diagnostics on the COMPASS tokamak

The Thomson scattering diagnostics (TS) at the COMPASS tokamak (operated in the Institute of Plasma Physics ASCR, Prague, Czech Republic) is based on two high-power Nd:YAG lasers, which have a pulse energy of 1.5J and repetition rate of 30Hz each.A new timing and synchronization unit (TSU) based on a Field Programmable Gate Array (FPGA) was designed and constructed in order to assure reliable and synchronized control of flash lamps and Q-switches of both lasers. Correct delay between laser pulses is necessary to obtain the highest possible laser energy and to prevent the active medium, the Nd:YAG rod, from thermal damage.An FPGA development kit was chosen as core hardware for the TSU and dedicated input and output circuits were manufactured to adapt the kit interfaces for COMPASS TS needs. In addition, the FPGA firmware, the control software, and the graphical user interface were developed to control the TSU hardware.This paper describes the TS regimes that are addressed by the new TSU. Further, the TSU design, the operation flow, and the firmware and software development are presented. Finally, the results of commissioning are shown.

Comparison of High Level FPGA Hardware Design for Solving Tri-diagonal Linear Systems

Reconfigurable computing devices can increase the performance of compute intensive algorithms by implementing application specific co-processor architectures. The power cost for this performance gain is often an order of magnitude less than that of modern CPUs and GPUs. Exploiting the potential of reconfigurable devices such as Field-Programmable Gate Arrays (FPGAs) is typically a complex and tedious hardware engineering task. Recently the major FPGA vendors (Altera, and Xilinx) have released their own high-level design tools, which have great potential for rapid development of FPGA based custom accelerators. In this paper, we will evaluate Altera's OpenCL Software Development Kit, and Xilinx's Vivado High Level Sythesis tool. These tools will be compared for their performance, logic utilisation, and ease of development for the test case of a tri-diagonal linear system solver.

Real‐time optical character recognition on field programmable gate array for automatic number plate recognition system

The last main stage in an automatic number plate recognition system (ANPRs) is optical character recognition (OCR), where the number plate characters on the number plate image are converted into encoded texts. In this study, an artificial neural network-based OCR algorithm for ANPR application and its efficient architecture are presented. The proposed architecture has been successfully implemented and tested using the Mentor Graphics RC240 field programmable gate arrays (FPGA) development board equipped with a 4M Gates Xilinx Virtex-4 LX40. A database of 3570 UK binary character images have been used for testing the performance of the proposed architecture. Results achieved have shown that the proposed architecture can meet the real-time requirement of an ANPR system and can process a character image in 0.7 ms with 97.3% successful character recognition rate and consumes only 23% of the available area in the used FPGA.

Low cost FPGA based data acquisition system for a gamma imaging probe

We present the development of a low cost field programmable gatearrays (FPGA) based data acquisitionsystem for a gamma imaging probe proposed for sentinel lymph node (SLN) mapping.Radioguided surgery using a gamma probe is an established practice and has beenwidely introduced in SLN biopsies. For such applications, imaging systemsrequirecompact readout electronics and flexibility. Embedded systems implemented in theFPGA technology offer new possibilities indata acquisition for nuclear medicine imagers. FPGAs are inexpensive compared toapplication specific integrated circuits (ASICs), usually used for the readoutelectronics of dedicated gamma cameras and their size is rather small.In this study, cost effective analog to digital converters (ADCs) were used andsignalprocessing algorithms were implemented in the FPGA to extract the energy andposition information. The analog front-end electronics were carefully designedtakinginto account the low sampling rate of the ADCs. The reference gamma probe has asmall fieldof view (2.5 cm × 2.5 cm) and is based on the R8900U-00-C12 positionsensitive photomultiplier tube (PSPMT) coupled to a pixellated CsI(Na)scintillator with 1 mm × 1 mm × 5 mm crystal element size. Measurementswere carried out using a general purpose collimatorand 99mTc sources emitted at 140 keV. Performance parameters for theimaging gamma probe werecompared with those obtained when data were acquired using the standard NIM(NuclearInstrumentation Modules) electronics and found to be in very good agreement,which demonstrates the efficiency of the proposed implementation.

Designing a Four-by-Four Keypad Arbitrary-Key-Entry Detector

This paper presents a field programmable gate array (FPGA) prototype of a four-by-four keypad arbitrary-key-entry detector design for entering any arbitrary set of the 4x4 keypad keys. The number of the valid keys was defined by a multiple-bit mask input. The character code of the prohibited key would not be generated after a key stroke. A valid-key stroke caused the detector circuit to generate a 4-bit hexadecimal character code and a sampling tick for the next-stage device to capture the pressed key information. The detector design and the testing circuitry were implemented on an Atlys Spartan-6 FPGA Development Board. The design itself can be incorporated into a wide variety of key-entry tools on electronic instruments, mechanical devices, medical apparatus, and more, to improve the key-stroke filtering and ease the interface connection.

Development of FPGA based NURBS interpolator and motion controller with multiprocessor technique

The high-speed computational performance is gained at the cost of huge hardware resource, which restricts the application of high-accuracy algorithms because of the limited hardware cost in practical use. To solve the problem, a novel method for designing the field programmable gate array(FPGA)-based non-uniform rational B-spline(NURBS) interpolator and motion controller, which adopts the embedded multiprocessor technique, is proposed in this study. The hardware and software design for the multiprocessor, one of which is for NURBS interpolation and the other for position servo control, is presented. Performance analysis and experiments on an X-Y table are carried out, hardware cost as well as consuming time for interpolation and motion control is compared with the existing methods. The experimental and comparing results indicate that, compared with the existing methods, the proposed method can reduce the hardware cost by 97.5% using higher-accuracy interpolation algorithm within the period of 0.5 ms. A method which ensures the real-time performance and interpolation accuracy, and reduces the hardware cost significantly is proposed, and it’s practical in the use of industrial application.

CAD Tools for Hardware Implementation of Embedded Fuzzy Systems on FPGAs

This paper describes two computer-aided design (CAD) tools for automatic synthesis of fuzzy logic-based inference systems. The tools share a common architecture for efficient hardware implementation of fuzzy modules, but are based on two different design strategies. One of them is focused on the generation of standard VHDL code, which can be later implemented on a reconfigurable device [field-programmable gate array (FPGA)] or as an application-specific integrated circuit (ASIC). The other one uses the Matlab/Simulink environment and tools for development of digital signal processing (DSP) systems on Xilinx's FPGAs. Both tools are included in the last version of Xfuzzy, which is a specific environment for designing complex fuzzy systems, and they provide interfaces to commercial VHDL synthesis and verification tools, as well as to conventional FPGA development environments. As demonstrated by the included design example, the proposed development strategies speed up the stages of description, synthesis, and functional verification of embedded fuzzy inference systems.

Design and FPGA implementation of a wireless hyperchaotic communication system for secure real-time image transmission

Abstract In this paper, we propose and demonstrate experimentally a new wireless digital encryption hyperchaotic communication system based on radio frequency (RF) communication protocols for secure real-time data or image transmission. A reconfigurable hardware architecture is developed to ensure the interconnection between two field programmable gate array development platforms through XBee RF modules. To ensure the synchronization and encryption of data between the transmitter and the receiver, a feedback masking hyperchaotic synchronization technique based on a dynamic feedback modulation has been implemented to digitally synchronize the encrypter hyperchaotic systems. The obtained experimental results show the relevance of the idea of combining XBee (Zigbee or Wireless Fidelity) protocol, known for its high noise immunity, to secure hyperchaotic communications. In fact, we have recovered the information data or image correctly after real-time encrypted data or image transmission tests at a maximum distance (indoor range) of more than 30 m and with maximum digital modulation rate of 625,000 baud allowing a wireless encrypted video transmission rate of 25 images per second with a spatial resolution of 128 × 128 pixels. The obtained performance of the communication system is suitable for secure data or image transmissions in wireless sensor networks.

Improved number plate localisation algorithm and its efficient field programmable gate arrays implementation

Number plate localisation is a very important stage in an automatic number plate recognition (ANPR) system and is computationally intensive. This study presents a low complexity with high-detection rate number plate localisation algorithm based on morphological operations together with an efficient multiplier-less architecture based on that algorithm. The proposed architecture has been successfully implemented and tested using a Mentor Graphics RC240 FPGA (field programmable gate arrays) development board equipped with a 4M-gate Xilinx Virtex-4 LX40. Two database sets sourced from the UK and Greece and including 1000 and 307 images, respectively, both with a resolution of 640 × 480, have been used for testing. Results achieved have shown that the proposed system can process an image in 4.7 ms, while achieving a 97.8% detection rate and consuming only 33% of the available area of the FPGA.

Design, Implementation and Testing of 16 bit RISC Processor

Nowadays Embedded Systems have became a part of human life. The most important part of an embedded system is the embedded processor. The performance of embedded processor determines the performance of embedded system. An embedded processor is a Reduced Instruction Set Computer (RISC). In this paper the procedure for designing, implementing and testing a 16 bit RISC processor is presented. This processor was implemented in XC3S400 Field Programmable Gate Array (FPGA) and tested on XC3S400 FPGA development board. This processor is useful for demonstrating hazards in pipeline and the techniques used to solve them.

A novel low‐spur DDFS utilizing the twice second‐order high‐pass error feedback architecture

AbstractIn this paper, the twice second‐order high‐pass error feedback (EF) (twice second‐order high‐pass EF (HPEF)) utilizing re‐feedback process and phase‐bit splitting technique in the second‐order HPEF to design a simplified low‐spur direct digital frequency synthesizer is proposed. The proposed method performs phase‐bit splitting technique and re‐feedback process in order to make the phase change tremendously and scramble the periodicity of the phase sequences violently in the original feedback path. In addition, the noise spectrum power is spread more uniformly in order to effectively suppress the spurs due to phase‐truncated error effect. Thus, the twice second‐order HPEF is implemented on a field programmable gate array development board, the Altera Stratix II EP2S60. The simulation and experimental results show that the proposed method can effectively achieve better spectrum performance, such as spurious‐free dynamic range, as compared to basic phase truncation, first‐order HPEF and second‐order HPEF architectures. Copyright © 2012 John Wiley & Sons, Ltd.

Continuous real-time correction and averaging for frequency comb interferometry

Interferograms from a dual-comb spectrometer are continuously corrected and averaged in real-time. The algorithm is implemented on a field-programmable gate array (FPGA) development board. The chosen approach and the algorithm are described. Measurements with high signal-to-noise ratio, resolution and bandwidth are shown to demonstrate the accuracy of the optical referencing and the processing algorithm with 24 hours of averaging time, reaching a signal to noise ratio of 10,750,000 (>21 bits) in the interferogram and 316,000 in the spectrum at 100 MHz resolution. An interferogram where signal dominates the noise over the full delay range imposed by the 100 MHz repetition rate is reported for the first time.

Note: A 4 ns hardware photon correlator based on a general-purpose field-programmable gate array development board implemented in a compact setup for fluorescence correlation spectroscopy

We present a fast hardware photon correlator implemented in a field-programmable gate array (FPGA) combined with a compact confocal fluorescence setup. The correlator has two independent units with a time resolution of 4 ns while utilizing less than 15% of a low-end FPGA. The device directly accepts transistor-transistor logic (TTL) signals from two photon counting detectors and calculates two auto- or cross-correlation curves in real time. Test measurements demonstrate that the performance of our correlator is comparable with the current generation of commercial devices. The sensitivity of the optical setup is identical or even superior to current commercial devices. The FPGA design and the optical setup both allow for a straightforward extension to multi-color applications. This inexpensive and compact solution with a very good performance can serve as a versatile platform for uses in education, applied sciences, and basic research.

Improved number plate character segmentation algorithm and its efficient FPGA implementation

Character segmentation is an important stage in Automatic Number Plate Recognition systems as good character separation leads to a high recognition rate. This paper presents an improved character segmentation algorithm based on pixel projection and morphological operations. An efficient architecture based on the proposed algorithm is also presented. The architecture has been successfully implemented and verified using the Mentor Graphics RC240 FPGA (Field Programmable Gate Arrays) development board equipped with a 4M-Gate Xilinx Virtex-4 LX40. A database of 1,000 UK binary NPs with varying resolution has been used for testing the performance of the proposed architecture. Results achieved have shown that the proposed architecture can process a number plate image in 0.2---1.4 ms with 97.7 % successful segmentation rate and consumes only 11 % of the available area in the used FPGA.

An Ultra Low Cost Wireless Communications Laboratory for Education and Research

This paper presents an ultra-low-cost wireless communications laboratory that is based on a commercial off-the-shelf field programmable gate array (FPGA) development board that is both inexpensive and available worldwide. The total cost of the laboratory is under USD $200, but it includes complete transmission, channel emulation, reception (coherent and noncoherent), and probing capabilities. Over 15 different modulation types are currently supported. The laboratory, aimed primarily to serve as a teaching aid for a professor teaching senior undergraduate courses and projects, allows students to have visual real-time demonstrations in wireless communications systems. The laboratory is also powerful enough to allow experienced researchers to carry out wireless communications research projects. In this context, the laboratory is particularly useful for universities in developing countries, where budgets are extremely limited. Numerical and written survey results are presented that were collected from two classes of students taught by the author in a university in Colombia, South America, and which show the effectiveness of the laboratory in teaching wireless communications.

Interactive Demonstration of a Remote Reconfigurable Logic Laboratory for Basic Digital Design

In this interactive demonstration we show the usage of a remote reconfigurable logic laboratory for digital design students, presented in a full paper submitted to the conference. A very simple web based approach is used to enable the remote access to a FPGA (Field Programmable Gate Array) development and educational board. The board switches and keys are virtualised with an online web form, and a webcam is used to provide feedback to the user.

A Redundant FPGA Based Controller for Subsea Blowout Preventer Stack

A redundant Field Programmable Gate Array (FPGA) based controller for subsea Blowout Preventer (BOP) is presented. Triple modular redundancy technique is used for architecture design, since high reliability is a necessary requirement for subsea BOP control system. A multiprocessor system is developed to enhance reliability of the processors and performance of the system. In addition, the shared memory method is applied to interchange information between the processors. One processor is responsible for communication, while the others run application programs. The proposed system has been implemented using three FPGA development boards, which are connected to each other through RS-232 serial ports. Besides, the voting algorithms for discrete input, analog input and discrete output are proposed. Functional simulation of the output voting is performed by using the Quartus II Simulator software. The results demonstrate that the proposed controller is able to tolerate faults, which means it has extremely high reliability.

An analytical model for multilevel performance prediction of Multi-FPGA systems

Power limitations in semiconductors have made explicitly parallel device architectures such as Field-Programmable Gate Arrays (FPGAs) increasingly attractive for use in scalable systems. However, mitigating the significant cost of FPGA development requires efficient design-space exploration to plan and evaluate a range of potential algorithm and platform choices prior to implementation. The authors propose the RC Amenability Test for Scalable Systems (RATSS), an analytical model which enables straightforward, fast, and reasonably accurate performance prediction prior to implementation by extending current modeling concepts to multi-FPGA designs. RATSS provides a comprehensive strategic model to evaluate applications based on the computation and communication requirements of the algorithm and capabilities of the FPGA platform. The RATSS model targets data-parallel applications on current scalable FPGA systems. Three case studies with RATSS demonstrate nearly 90% prediction accuracy as compared to corresponding implementations.

Fast Hardware Design of 1/f Fractional Brownian Noise Generator

This paper proposes the design of a fast and accurate 1/f fractional Brownian motion (fBm) noise generator. The solution is based on the successive random addition algorithm using the midpoint displacement (SRMD) technique. The implementation was performed on a high-speed field-programmable gate array (FPGA) Development Kit. It enabled the generation of 150 million of 16-bit noise samples per second. The 1/f noise generator achieved 7.4% of the logic elements, 52% of the RAM memory and 1.6% of the ROM memory. The accuracy of the 1/f noise samples was evaluated for different sequence size and confidence intervals. The noise samples pattern was examined by the probability density (PDF) and the heavy-tail distribution (HTD) functions. The results also include the auto-correlation function (ACF) to show the low-frequency statistics of the 1/f noise samples. For the investigation it was used the real 1/f speech-babble acoustic noise parameters. The results showed that the proposed 1/f noise generator design can be promising to the performance evaluation of communications channels with low bit error rate (BER) values. It can also be interesting for signal processing applications and other areas concerned with noisy conditions.

Multidimensional DFT IP Generator for FPGA Platforms

Multidimensional (MD) discrete Fourier transform (DFT) is a key kernel algorithm in many signal processing applications. In this paper we describe an MD-DFT intellectual property (IP) generator and a bandwidth-efficient MD DFT IP for high performance implementations of 2-D and 3-D DFT on field-programmable gate array (FPGA) platforms. The proposed architecture is generated automatically and is based on a decomposition algorithm that takes into account FPGA resources and the characteristics of off-chip memory access, namely, the burst access pattern of the synchronous dynamic RAM (SDRAM). The IP generator has been integrated into an in-house FPGA development platform, AlgoFLEX, for easy verification and fast integration. The corresponding 2-D and 3-D DFT architectures have been ported onto the BEE3 board and their performance measured and analyzed. The results shows that the architecture can maintain the maximum memory bandwidth throughout the whole procedure while avoiding matrix transpose operations used in most other MD DFT implementations. To further enhance the performance, the proposed architecture is being ported onto the newly released Xilinx ML605 board. The simulation results show that 2 K × 2 K images with complex 64-bit precision can be processed in less than 27 ms.