Field Programmable Gate Array Development Research Articles

Performance Modeling for CNN Inference Accelerators on FPGA

The recently reported successes of convolutional neural networks (CNNs) in many areas have generated wide interest in the development of field-programmable gate array (FPGA)-based accelerators. To achieve high performance and energy efficiency, an FPGA-based accelerator must fully utilize the limited computation resources and minimize the data communication and memory access, both of which are impacted and constrained by a variety of design parameters, e.g., the degree and dimension of parallelism, the size of on-chip buffers, the bandwidth of the external memory, and many more. The large design space of the accelerator makes it impractical to search for the optimal design in the implementation phase. To address this problem, a performance model is described to estimate the performance and resource utilization of an FPGA implementation. By this means, the performance bottleneck and design bound can be identified and the optimal design option can be explored early in the design phase. The proposed performance model is validated using a variety of CNN algorithms comparing the results with on-board test results on two different FPGAs.

Desarrollo de un sistema mecatrónico para robot humanoide que permita emular el movimiento del cuello de los seres humanos

En el presente trabajo se muestra el diseño de un sistema mecatrónico, el cual emula los movimientos del cuello humano, ya que sostendrá la cabeza de un robot humanoide (Arthur) desarrollado por la empresa Hanson Robotics. El diseño mecánico se basa en un robot esférico de 3 grados de libertad (3-GDL), se desarrolla el modelo dinámico a través de las ecuaciones de movimiento de Euler-Lagrange. La etapa de control es una tarjeta de desarrollo FPGA (arreglos de compuertas programables en campo) de la familia Cyclone IV, la etapa de potencia se basa en transistores BJT, se implementa el controlador Tangente hiperbólico y una interfaz de comunicación WiFi para configurar el robot desde una PC con ayuda del software Labview. Como resultado se muestra la integración del sistema mecatrónico, la interfaz desarrollada junto con la comunicación FPGA-PC y control de posición. El trabajo futuro será la implementación del sistema en el robot humanoide.

OpenCL Implementation of FPGA-Based Signal Generation and Measurement

Signal generation and measurement have been widely used in many engineering applications, such as for creating test signals in radar, communication, and software-defined radio. In field programmable gate array (FPGA) design, to generate and measure an analog signal, compatible software and hardware interfaces are required. Traditionally, hardware description language (HDL) is required to program an FPGA. HDL programming provides an efficient logic resource with low latency. However, it is time-consuming for designs that are more complex. Currently, OpenCL is implemented for FPGA programming. OpenCL reduces the FPGA development time because it increases the abstraction level of the code. OpenCL is an open and royalty-free framework for accelerating the algorithm executed on a heterogeneous system, such as a GPU, CPU, DSP, or FPGA. OpenCL implementation on FPGAs yields high-performance results for the computation process. However, compared to HDL design, OpenCL does not provide a particular function to access the FPGA hardware directly. In this paper, we have demonstrated the implementation of OpenCL programming on an FPGA for signal generation and measurement. We have developed OpenCL components that can interact with the FPGA hardware directly. An OpenCL I/O channel extension is employed in the kernel to read data from and write data to the OpenCL components. The experimental results indicate that OpenCL can be used for signal measurement and generation using FPGAs.

A highly scalable parallel spike-based digital neuromorphic architecture for high-order fir filters using LMS adaptive algorithm

This brief presents a highly scalable parallel neuromorphic architecture to efficiently compute high-order adaptive FIR filters using a least mean square (LMS) algorithm. This has been achieved by eliminating critical paths because they critically affect the scalability of advanced parallel architectures. Here, the scalability is defined in terms of number of taps and bit-length. On the computation of high-order adaptive FIR filters, the multiplication is the most demanding operation. Therefore, we have made intensive efforts to create a compact new neural multiplier by improving the design and hardware implementation of an existing neural multiplier. The resulting multiplier requires 50 % fewer synapses, 40 % fewer neurons, 30 % fewer area resources and 26 % fewer clock cycles compared with the existing neural multiplier, respectively. The efficient implementation of the proposed multiplier has allowed us to eliminate critical paths significantly and thus the bit-length can be easily increased to guarantee the convergence performance when high-order adaptive filters are processed. To demonstrate its effectiveness, the proposed multiplier was included in the neuromorphic architecture to support high-order adaptive FIR filters. In addition, we employ the time multiplexing technique to maximize the utilization of the proposed neural multiplier by performing filter processing and the adaptive process because multiplication is involved in both. We mainly use this strategy to eliminate critical paths and reduce the area consumption by implementing a large number of taps. The proposed neuromorphic architecture was implemented on the Kintex-7 Field Programmable Gate Array (FPGA) development kit to validate its performance. Our results demonstrate that the neuromorphic architecture is capable of processing higher adaptive FIR filters compared with previously reported solutions. This potentially allow its practical use in many advanced digital signal processing applications such as acoustic echo cancellers, active noise control, channel equalization and system identification.

Online adaptive master maximum power point tracking algorithm and sensorless weather estimation

This paper presents analysis aspects for photovoltaic (PV) cells. Starting from reducing the number of needed I–V points to extract the parameters of the double diode PV model based on two different stochastic algorithms. Then, the identified model is analyzed to find informative and detailed sensitivities of the main outputs of the PV cell to cell temperature and solar irradiance. These formulations can work as a master algorithm to check, update and accelerate the maximum power point tracking (MPPT) algorithms. Besides that, model uncertainties and variations in the parameters are considered to represent a new accurate MPPT algorithm in one straightforward step. An improved online adaptation to the fractional open circuit voltage and fractional short circuit current MPPT algorithms are presented as examples of the proposed one-step online MPPT algorithm. As a result, different sensorless estimators of the temperature and the irradiance are presented to replace the actual weather sensors with high accuracy. The proposed work is done for four PV cells to show the importance of this comprehensive analysis. Experimental work is carried out using a 100W (PS-M36s) solar panel and Altera DE2-115 field programmable gate array development board in the-loop verification environment to illustrate the effectiveness of the proposed procedure.

Cloud Based Remote FPGA Lab Platform: An Application of Internet of Things

IoT (Internet of Things) is the next generation of the Internet. The main goal of IoT is to connect each and every physical object to the Internet Cloud. This concept is introduced by bringing IoT technology to the laboratories, making expensive laboratory equipment available on-cloud for real-time experimentation. In this paper, an on CLP (Cloud Laboratory Platform) is presented by employing the concept of IoT to the academic experimentation environment. The CLP allows a rapid deployment of an online laboratory system enabling students and researchers to perform actual experiments on the on-Cloud laboratory equipment using a web interface. A web interface for end users to access front end of the system. This interface was developed for login purposes so that any user can perform experiments from anywhere. The interface also provides options for comments and feedback. Moreover, this research contribution also facilitate users to test their designs and record observations in real-time on the equipment. For demonstration purposes, a remote lab has been developed for high-tech Xilinx FPGA (Field Programmable Gate Array) development boards, namely Spartan-II and Spartan-III. This project aims to provide students a new tool to enhance their learning experience and encourage them to test their theoretical knowledge in practical applications.

Design and development of a synchronized operation control system for Thomson scattering diagnostic on J-TEXT

A Thomson scattering diagnostic system is under construction at the Joint Texas Experimental Tokamak (J-TEXT). A 1064 nm Nd:YAG laser with 50 Hz repetition rate is used as the laser source. We have used a software for careful and precise control of the laser through serial communication. A time sequence operating system has been developed to synchronize the laser control and data acquisition system with the central control system (CSS). The system operates commands from the CSS of J-TEXT and generates triggers for the laser and data acquisition system in the proper sequence. It also measures an asynchronous time value that is needed for accurate time stamping. All functions are served by a field-programmable gate array development platform that is suitable for high-speed data and signal processing applications. Several embedded peripherals, including Ethernet and USB 2.0, provide communication with the CSS and the server.

Design of Pocket Development Board Based on FPGA

With the development of programmable technology, the application of FPGA (field programmable gate array) technology is also more and more widely. In order to facilitate the students in the school to learn more about the FPGA development process and improve the practical ability of the students, a FPGA chip based on practicality is designed and suitable Experimental teaching pocket development board, can be convenient for students to carry, and low cost; this small development board to achieve some simple experiments, as a tool for students to learn hardware, rapid development of students’ good experimental ability.

On the improvement of the teaching quality and learning effectiveness in the computer organization course through FPGA and modular centered microcomputer design

AbstractThis manuscript focuses on the results of a project study on the field programmable gate array (FPGA) and modular based microcomputer architecture design for improving the teaching and learning effectiveness in computer organization course and similar courses. The design mentioned in this manuscript is a unique system allowing to students to directly write their program and/or include their own designs. The main objective of this study is to improve the teaching effectiveness in the computer organization course at graduate level via hands‐on learning. The goal of the project is to encourage students to create their unique microcomputer designs since this design has modular structure and the fundamental elements which a simple computer has. Also it is to make appropriate modifications using students’ concerns and the results of project study for computer architecture and organization course for next semesters. To evaluate the improvement of the teaching and learning effectiveness, the students enrolled in the computer organization course in computer engineering department are divided into two groups. A student survey is conducted to provide students with an opportunity to have their views about this methodology at computer organization course. The results of the survey acquired with the probability density distribution function reveal the effectiveness of this methodology with FPGA development environment.

Design and Testing of the Address in Real-Time Data Driver Card for the Micromegas Detector of the ATLAS New Small Wheel Upgrade

The address in real-time data driver card (ADDC) is designed to transmit the trigger data in the micromesh gaseous structure (Micromegas, MM) detector of the ATLAS new small wheel (NSW) upgrade. The address in real-time (ART) signals are generated by the front-end application-specific integrated circuit (ASIC), named VMM chip, to indicate the address of the first above-threshold event. A custom ASIC (ART ASIC) is designed to receive the ART signals from the VMM chip and implement the hit selection. The processed data from the ART ASIC will be transmitted out of the NSW through the gigabit transceiver (GBTx) serializer, the unidirectional versatile twin transmitter (VTTx), and fiber-optic links. The ART signal is critical for the ATLAS experiment trigger selection; thus, the performance and stability of the ADDC is very important. To ensure extensive testing of the ADDC, a field-programmable gate array (FPGA) mezzanine card (FMC)-based testing platform and a specially designed firmware/software are developed. This test platform works with the commercial Xilinx VC707 FPGA development kit; independent of the other electronics in the NSW, it can test all the functions of the ADDC and it has long-term stability. This article will introduce the design, testing procedure, and results of the ADDC and the FMC testing platform.

Design and Implementation of Multicore System for Wireless Intelligent Control

This paper presents the design and implementation of multicore system based on Nios II processor in field programmable gate array (FPGA) for wireless intelligent control. The system includes FPGA as a central controller to control the devices connected to it. We monitor the devices wirelessly by using the Bluetooth. We are using the android mobile for Bluetooth connectivity. The central implementation was conceded out by a Cyclone-II FPGA Development Board to evaluate the proposed concept of the system.

The performance and limitations of FPGA-based digital servos for atomic, molecular, and optical physics experiments.

In this work, we address the advantages, limitations, and technical subtleties of employing field programmable gate array (FPGA)-based digital servos for high-bandwidth feedback control of lasers in atomic, molecular, and optical physics experiments. Specifically, we provide the results of benchmark performance tests in experimental setups including noise, bandwidth, and dynamic range for two digital servos built with low and mid-range priced FPGA development platforms. The digital servo results are compared to results obtained from a commercially available state-of-the-art analog servo using the same plant for control (intensity stabilization). The digital servos have feedback bandwidths of 2.5 MHz, limited by the total signal latency, and we demonstrate improvements beyond the transfer function offered by the analog servo including a three-pole filter and a two-pole filter with phase compensation to suppress resonances. We also discuss limitations of our FPGA-servo implementation and general considerations when designing and using digital servos.

Facial Expression Emotion Detection for Real-Time Embedded Systems

Recently, real-time facial expression recognition has attracted more and more research. In this study, an automatic facial expression real-time system was built and tested. Firstly, the system and model were designed and tested on a MATLAB environment followed by a MATLAB Simulink environment that is capable of recognizing continuous facial expressions in real-time with a rate of 1 frame per second and that is implemented on a desktop PC. They have been evaluated in a public dataset, and the experimental results were promising. The dataset and labels used in this study were made from videos, which were recorded twice from five participants while watching a video. Secondly, in order to implement in real-time at a faster frame rate, the facial expression recognition system was built on the field-programmable gate array (FPGA). The camera sensor used in this work was a Digilent VmodCAM — stereo camera module. The model was built on the Atlys™ Spartan-6 FPGA development board. It can continuously perform emotional state recognition in real-time at a frame rate of 30. A graphical user interface was designed to display the participant’s video in real-time and two-dimensional predict labels of the emotion at the same time.

Design of Digital PID Controllers Relying on FPGA-based Techniques

A major challenge of higher education institutions is to prepare professionals capable of learning by building effective solutions that are able to integrate different disciplines and knowledge areas. With this in mind, academics and researchers from ESPOL university in Ecuador, have designed laboratory experiments for a digital control class that introduces students to a modular design of embedded feedback controllers using Field Programmable Gate Array (FPGA) technologies. The proposed experiment includes the design of direct discrete time PID controllers, for an existing speed control system with three different sampling times, to test and compare their performance. The obtained controllers are implemented using a prototyping strategy that relies on FPGA development boards. The prototype controller is tested using the experimental plant, and the system performance is contrasted with results from simulations under realistic conditions.

An Improved High-Resolution DPWM Control Circuit Based on FPGA

Digital pulse width modulation (DPWM) has advantages of strong anti-interference ability, high efficiency and good flexibility, therefore it has been widely used in switching power supply, communications, power control and transform and other fields. This paper proposed a high resolution DPWM control circuit based on field programmable gate array (FPGA), which solved the problem of low resolution and instability of the traditional DPWM control circuit. The principle of the proposed circuit is presented in this paper, and the circuit has been successfully implemented on the Xilinx Artix-7 FPGA development board. The experiment shows that, when the frequency of the circuit is 50 MHz, the resolution of DPWM can reach 78ps, and the proposed DPWM control circuit has wide application prospects.

Power Systems Control Implementation Based on Two Dedicated FPGA Development Boards Using a Hard/soft Communication Interface

This paper presents an unusual Field Programmable Gate Array (FPGA) development platform for power systems control. This platform is made up of two FPGA boards with a hardware and software communication interface. The one initially realized for direct torque Motor control is now dedicated for analog and digital signals input/output and the other card of much important density is specialized in data processing. A fully digital modules have been developed inside FPGAs from synthesis tools Quartus 2 and Maxplus 2, and a physical link have been realized to manage the communication between the cards. The control strategy takes advantage of the parallelism of the FPGA technology to share in real-time the controller’s information with its environment. Simulations and experimental results validate the feasibility of a simple handshaking communication protocol between both cards. On the other hand, with the proposed implementation solution it was shown a safe operation in a power grid switching station, a successful instantaneous frequency measurements used for grid synchronization and Active Power Filter control, followed by a production of Pulse Width Modulation (PWM) gating signals used for inverter in motor control and power quality applications.

No latency feedback controller coupled to real-time physical models using programmable hardware

Over the last years, advances in technology and methodology made it possible to simulate and synthesize highly realistic finite difference (FD) models in real-time or close to real-time. Still, most conventional processing platforms introduce latency to the signal processing chain due to sequential processing and/or communication protocol timing and throughput restrictions. This can act as a severe penalty when developing expressive controller interfaces for large geometry physical models. Using field programmable gate array (FPGA) hardware enables highly customized interface and FD model designs that are able to meet hard real-time requirements even for large physical models. In this work, a modified five-string banjo coupled to a real-time physical modeling synthesis application running on an FPGA development board is presented. The proposed methodology is an extension of an existing PCIe enabled interface which was primarily developed for research applications. The new interface is aimed at facilitating expressive interaction for musical purposes. The bi-directional excitation and feedback is realized using standard electro-mechanical sensors and actuators, making it possible to connect the string vibration of the modified banjo to arbitrary geometries as well as capturing the response of the modeled structure and feeding it back to the acoustic instrument. FD-models of different shapes and materials are implemented resulting in physically impossible instrument configurations yielding unique tone production capabilities.

Spike-based compact digital neuromorphic architecture for efficient implementation of high order FIR filters

Finite impulse response (FIR) filters have been widely used in many digital signal processing applications because of their interesting properties such as phase linearity, bounded-input-bounded-output (BIBO) stability and easy implementation. However, the implementation of high order filters requires many multipliers. Several authors have proposed new methods such as multiple constant multiplication (MCM), distributed arithmetic (DA) and signed-powers-of-two (SPT) to avoid the use of multipliers by using the minimum number of registers. Nevertheless, the implementation of these strategies generates critical paths that limit their performance. In this work, we propose a compact hardware architecture to compute FIR filters at high processing speeds using new parallel neural multipliers. The scalability of the system enables the construction of many neural multiplier units for higher order FIR filters. To validate the proposal, the hardware architecture was implemented on the Kintex-7 field programmable gate array (FPGA) development kit. The results demonstrate that this new approach can be interfaced with the conventional binary systems to improve advanced signal processing applications such as high quality media contents, wireless communication and biomedical systems.

Development of a wireless capsule endoscope system based on field programmable gate array

A new modular and programmable wireless capsule endoscope is presented in this paper. The capsule system consumes low power and has small physical size. A new image compression algorithm is presented in this paper to reduce power consumption and silicon area. The compression algorithm includes color space transform, uniform quantization, sub-sampling, differential pulse code modulation (DPCM) and Golomb-Rice code. The algorithm is tested in a field programmable gate array (FPGA) development board, and the final result achieves 80% compression rate at 40 dB peak signal to noise ratio (PSNR). The algorithm has high image compression efficiency and low power consumption, compared to other existing works. The system is composed of the following three parts: image capsule endoscope, portable wireless receiver and host computer software. The software and hardware design of the three parts are disscussed in details.

Realization of OFDM modulation and demodulation for visible light communication based on FPGA

In order to ensure stable, correct and real-time high-speed transmission of indoor visible light communication (VLC), the key modulation and demodulation technologies of orthogonal frequency division multiplexing (OFDM) are studied in this paper. The time-domain synchronization, frequency synchronization and channel equalization of receiver are analyzed and optimized by utilizing short and long training preamble. Moreover, field programmable gate array (FPGA) development board (Xilinx Kintex-7) and Verilog hardware description language are used to realize the design of proposed OFDM-VLC system. Simulation and experiment both verify the feasibility of the hardware designs of this system. The proposed OFDM-based VLC system can process signal in real-time, which can be used in actual VLC application systems.