Field Programmable Gate Array Design Research Articles

Remote field-programmable gate array laboratory for signal acquisition and design verification

A remote laboratory utilizing field-programmable gate array (FPGA) technologies enhances students’ learning experience anywhere and anytime in embedded system design. Existing remote laboratories prioritize hardware access and visual feedback for observing board behavior after programming, neglecting comprehensive debugging tools to resolve errors that require internal signal acquisition. This paper proposes a novel remote embedded-system design approach targeting FPGA technologies that are fully interactive via a web-based platform. Our solution provides FPGA board access and debugging capabilities beyond the visual feedback provided by existing remote laboratories. We implemented a lab module that allows users to seamlessly incorporate into their FPGA design. The module minimizes hardware resource utilization while enabling the acquisition of a large number of data samples from the signal during the experiments by adaptively compressing the signal prior to data transmission. The results demonstrate an average compression ratio of 2.90 across three benchmark signals, indicating efficient signal acquisition and effective debugging and analysis. This method allows users to acquire more data samples than conventional methods. The proposed lab allows students to remotely test and debug their designs, bridging the gap between theory and practice in embedded system design.

FPGA: The super chip in the age of artificial intelligence

In modern society, artificial intelligence (AI) is developing more rapidly. And the Field Programmable Gate Array (FPGA) has always been the focus of research as a driving platform. This paper studies in detail the theoretical basis, applications, defects, and future development directions of FPGAs. It is concluded that FPGA has three characteristics: gate array, programmable, and scene, and the detailed positioning of FPGA, the structure, principle, tools, process, and description language of FPGA design. And the unique advantages of FPGA in the field of artificial intelligence: flexible and configurable, special optimizations for convolutional neural networks, and deterministic low latency. Several typical applications of FPGA in the field of artificial intelligence, deficiencies and solutions, and two future development directions. This article will make a great contribution to the development of FPGA in the field of artificial intelligence in the future.

Introduction and application analysis of FIFO-related methods

In this paper, an improved method of using binary pointers is proposed based on the analysis of the basic principles and structure of FIFO. The paper also presents a high-speed data acquisition system based on STM32 with an asynchronous FIFO designed to solve the insufficient data acquisition speed and high-power consumption problems of fiber-optic grating sensors in the electrical industry. The use of binary pointers significantly improves the processing speed and reduces the power consumption of the FIFO, thus improving the overall efficiency.In addition, the paper introduces the use of a field-programmable gate array (FPGA) design as the control core of a color sorter system. This overcomes the drawbacks of processor-based multi-channel color sorters, including low delay accuracy, poor consistency, and persistent signal loss. The FPGA offers superior performance due to its parallel computing capabilities and flexibility in algorithm implementation, making it ideal for high-performance applications such as color sorting systems.The color sorter system designed using FPGA technology is capable of sorting different materials based on color, shape, and size. The system's superior performance is due to the use of an asynchronous FIFO buffer that enables real-time color recognition and processing. By incorporating the FIFO buffer, the system can achieve high processing speeds, consistent color recognition, and minimal signal loss, providing a valuable solution for applications requiring high-precision color sorting.

Dynamical analysis and synchronization control of flux-controlled memristive chaotic circuits and its FPGA-Based implementation

This paper focuses on addressing the synchronization control problem of memristive chaos through the investigation of a single feedback controller strategy. Our objective is to deploy this strategy on field-programmable gate arrays (FPGA) with the aim of bolstering the security and reliability of memristive chaotic synchronization control. Concurrently, we seek to enhance system performance and fulfill the diverse requirements of various applications. Initially, the study utilizes chaos synchronization theory and the Routh–Hurwitz stability criterion to devise a feedback controller with a single input. This controller plays a crucial role in establishing a synchronization system specifically designed for memristive chaos. Subsequently, the FPGA design approach utilizing DSP Builder is employed to create models for both the single-input feedback controller and the memristive chaotic synchronization control system. This approach facilitates the efficient translation of these theoretical concepts into practical digital circuit implementations. Finally, the paper concludes with an experimental analysis that verifies the feasibility and practical applicability of the FPGA circuit design for memristive chaotic synchronization control.

A Framework for Automated Exploration of Trojan Attack Space in FPGA Netlists

Field Programmable Gate Arrays (FPGAs) provide a flexible compute platform for quick prototyping or hardware acceleration in diverse application domains. However, similar to the global semiconductor life-cycle in the modern supply chain, FPGA-based product development includes processes and interactions with potentially untrusted parties outside the traditional scrutiny of a completely in-house development cycle. An untrusted party or software can maliciously alter a hardware intellectual property (IP) block mapped to an FPGA device during various stages of the FPGA life-cycle. Such malicious alterations, also known as hardware Trojan attacks, have garnered significant research into their detection and prevention in the context of application-specific integrated circuit (ASIC) design flow. However, Trojan attacks in FPGAs have not enjoyed this same attention. Designers often rely on mapping ASIC-specific solutions and evaluation benchmarks to the FPGA domain, which leaves much of the FPGA-specific Trojan space uncovered. We note that the distinctive business model as well as the architectural configurations of FPGAs present unique opportunities for Trojan attacks to an adversary. To this end, we introduce a framework to automatically explore the hardware Trojan attack space in FPGA netlists. It is capable of inserting different types of FPGA-specific Trojans in a netlist enabling rapid exploration of potential Trojan attacks in an FPGA design: soft-template, monolithic, and distributed dark silicon. Soft template Trojans use behavioral templates with random synthesis constraints to increase Trojan structural diversity. Monolithic and distributed dark silicon Trojans use the under-utilized input space (FPGA dark silicon) in FPGA primitives to realize Trojans with effectively zero area and power footprint. Further optimizations are also presented to remove any potential delay impact. We then generate over 1300 Trojan-inserted benchmarks using each of the introduced FPGA Trojan classes, and compare their impact on utilization, delay, and power. Finally, we evaluate our Trojans against a machine learning-based Trojan detection to highlight their evasiveness.

Integrating Machine-Learning Probes in FPGA CAD: Why and How?

This article discusses the performance challenge that modern designs pose for current Field Programmable Gate Array (FPGA) design tools. It then explores how machine-learning probes can be used within the traditional FPGA design flow to improve performance. As proof of concept, the authors implement nine probes and integrate them into the placement step of the Verilog-to-Routing (VTR) tool. Each probe provides fast, accurate estimates of routing-resource utilization, which can be used to guide the placer towards more “routing-friendly” placement solutions or avoid futile routing attempts.

Resource-Efficient Low-Latency Modified Pietra-Ricci Index Detector for Spectrum Sensing in Cognitive Radio Networks

In this article, the modified Pietra-Ricci index detector (mPRIDe) is devised, and its field programmable gate array (FPGA) and application-specific integrated circuit (ASIC) designs are reported. The mPRIDe attains lower implementation complexity with respect to its predecessor, without performance penalty. Moreover, the mPRIDe is blind, robust against time-varying noise and received signal powers, and exhibits the constant false alarm rate property. Two versions of the mPRIDe, namely mPRIDe v1 and mPRIDe v2, have been designed. The former privileges lower hardware complexity, whereas the latter aims lower latency, with both versions having a linear scalability with the number of sensors in cooperation. In comparison with the smallest area consumed by a state-of-the-art sensor, mPRIDe v1 and mPRIDe v2 consume 56.6% and 47.3% lower areas, respectively. The sensing times of the proposed sensors are 1.6 and 2.9 times better than the fastest sensing time of contemporary sensors. Moreover, the proposed designs deliver the lowest area-time-product and power-delay-product among state-of-the-art implementations. These metrics make both mPRIDe v1 and mPRIDe v2 the most hardware-efficient and power-efficient sensors reported in the literature.

FPGA Design of Transposed Convolutions for Deep Learning Using High-Level Synthesis

Deep Learning (DL) is pervasive across a wide variety of domains. Convolutional Neural Networks (CNNs) are often used for image processing DL applications. Modern CNN models are growing to meet the needs of more sophisticated tasks, e.g. using Transposed Convolutions (TCONVs) for image decompression and image generation. Such state-of-the-art DL models often target GPU-based high-performance architectures, due to the high computational and hardware resource needs of TCONV layers. To avoid prohibitive GPU energy costs, CNNs are increasingly deployed to decentralized embedded autonomous devices, such as Field Programmable Gate Arrays (FPGAs). However, this poses challenges for designing efficient hardware implementations of TCONV layers. This paper presents a parameterized design and implementation of a new TCONV module, which is synthesizable onto FPGAs. It is implemented using the High-Level Synthesis (HLS), through a C++ template to parameterize its functional and non-functional properties. These parameters allow kernel sizes, image sizes, quantization and parallelism to be varied by users. With a systematic exploration in this design space, we find an optimal instance of this TCONV module that achieves 6.25 Giga Outputs per Second (Gout/s) using just 1.53 W of power. We then use our TCONV layer in two neural networks for image decompression and image generation. Image decompression achieves a speed throughput of more than 30K frames-per-second (fps) using only the 16% of resources on average, image generation achieves an energy efficiency of 324 fps/W and outperforms comparable state-of-the-art models by at least 7.3×.

A Hardware-Friendly Real-Time Implementation of the Auditory Attention Based on a Novel Spiking Winner-Take-All Network

In recent decades, the modeling and designing of neuromorphic systems have received considerable attention, leading to the development of electrophysiological devices that can mimic the dynamic behavior of cortical networks. Some features such as parallel processing, real-time performance, reconfigurability, low production cost, and good accuracy, make field programmable gate arrays (FPGAs) an ideal hardware platform for implementing spiking neural networks (SNN), which has become very popular in the field of neural computing. In this work, we investigated a high-performance FPGA design of the auditory attention to simulate the on-chip ‘cocktail party’ effect similar to what happens in the brain. In the first step, we introduce a novel spiking winner-take-all (SWTA) network consisting of a hardware-friendly Izhikevich neuron model and explore its biological characteristics and stability. We then use this network as a receptive field in the primary auditory cortex, which is tuned by attention signals. The desired sound frequency will be selected as the target and transmitted to the higher layers of the auditory cortex for further processing, while other frequencies are severely suppressed. Experimental results show that the proposed network accurately follows the dynamic behavior defined in the auditory attention theory, and emphasizes the resource consumption after post place and routes on a fully efficient hardware implementation, where less than 4% of the resources were used to implement a network with 1856 neurons.

A Scalable and Area-Efficient Configuration Circuitry for Semi-Custom FPGA Design

Configuration circuitry is an essential component of a field-programmable gate array (FPGA) fabric, which enables the configuration of each programmable logic and takes over 40% of the FPGA chip area. Following the recent trends of automated custom FPGA design, it is essential to study the impact on the area and power of the configuration circuitry. This study compares the performance of different configuration circuitries using a strictly automated and complete standard cell-based semi-custom design methodology. We leverage an open-source framework, OpenFPGA, and extended it to support two configuration protocols: shift-register-based configuration (SRC) and memory-bank-based configuration (MBC) circuitries and their variants. We proposed area optimization strategies to improve the physical implementation of each configuration circuitry. Our results show that compared with naive SRC implementation, the proposed optimization strategies minimize the area overhead by more than 30% and power dissipation during programming by 20%. Whereas compared with MBC implementation, the optimized SRC implementation requires approximately a similar area. However, considering the more practical implementation of MBC with the write-verify functionality with optimized SRC implementation, the MBC implementation requires an 11% higher area and 30% higher routing wirelength, but results in a 62% reduction in the power dissipation during programming.

FPGA-Based Machine Learning: Platforms, Applications, Design Considerations, Challenges, and Future Directions

Field-Programmable Gate Arrays (FPGAs) have emerged as a promising platform for accelerating machine learning tasks due to their high parallelism, low latency, and hardware customization ability. In this paper, the authors provide an overview of popular FPGA platforms for machine learning and compare the tradeoffs among FPGAs, GPUs, and CPUs for machine learning. The authors also present specific applications of machine learning based on FPGAs, including those in autonomous driving and healthcare. Additionally, the paper explores FPGA design considerations, such as architecture, resource utilization, and power consumption. Nonetheless, obstacles persist in the realm of FPGA-based machine learning that require attention. Identifying the ideal balance between adaptability and performance, considering factors such as space, energy usage, and latency, is still challenging. As the capabilities of FPGAs expand, there is a significant need for devices that have a smaller footprint, reduced power consumption, and minimized delays. The paper emphasizes the necessity of ongoing research in the field of FPGA-based machine learning to address these issues and continue enhancing the performance and effectiveness of machine learning systems.

Design and Implementation of a Multiplier free FPGA based OFDM Transmitter

Orthogonal Frequency Division Multiplexing (OFDM) is an efficient multi-carrier technique.The core operation in the OFDM systems is the FFT/IFFT unit that requires a large amount of hardware resources and processing delay. The developments in implementation techniques likes Field Programmable Gate Array (FPGA) technologies have made OFDM a feasible option. The goal of this paper is to design and implement an OFDM transmitter based on Altera FPGA using Quartus software. The proposed transmitter is carried out to simplify the Fourier transform calculation by using decoder instead of multipliers. After programming ALTERA DE2 FPGA kit with implemented project, several practical tests have been done starting from monitoring all the results of the implemented blocks (VHDL code) and compare them with corresponding results from simulation system implemented in matlab 2010a. The results of these practical tests show that the suggested approach gives a significant improvement in reducing complexity and processing delays (45 nsec) in comparison with the conventional implementations of OFDM transmitter.

Accurate Multi-Channel QCM Sensor Measurement Enabled by FPGA-Based Embedded System Using GPS

This paper presents a design and implementation proposal for a real-time frequency measurement system for high-precision, multi-channel quartz crystal microbalance (QCM) sensors using a field programmable gate array (FPGA). The key contribution of this work lies in the integration of a frequency measurement and mass resolution computation based on Global Positioning System (GPS) signals within a single FPGA chip, utilizing Input/Output Blocks to incorporate logic QCM oscillator circuits. The FPGA design enables parallel processing, ensuring accurate measurements, faster calculations, and reduced hardware complexity by minimizing the need for external components. As a result, a cost-effective and accurate multi-channel sensor system is developed, serving as a reconfigurable standalone measurement platform with communication capabilities. The system is implemented and tested using the FPGA Xilinx Virtex-6, along with multiple QCM sensors. The implementation on a Xilinx XC6VLX240T FPGA achieves a maximum frequency of 324 MHz and consumes a dynamic power of 120 mW. Notably, the design utilizes a modest number of resources, requiring only 188 slices, 733 flip-flops, and 13 IOBs to perform a double-channel sensor microbalance. The proposed system meets the precision measurement requirements for QCM sensor applications, exhibiting low measurement error when monitoring QCM frequencies ranging from 1 to 50 MHz, with an accuracy of 0.2 ppm and less than 0.1 Hz.

Optimized Deep Learning-Based Fully Resolution Convolution Neural Network for Breast Tumour Segmentation on Field Programmable Gate Array

ABSTRACT Deep learning (DL) approaches have been highly interesting in segmentation and classification in recent years. During breast cancer detection, a convolutional neural network (CNN) requires several up-sampling operations to recover the original image from the feature map. This research introduces an optimised fully resolution-CNN (FR-CNN) based breast tumour segmentation in the field programmable gate array (FPGA) platform. The FPGA implementation of FR-CNN considers both fixed and floating point operations to find the best trade-off between accuracy and hardware complexity. The FR-CNN network model usually requires several adder and multiplier units that consume more power and area. Hence, an optimised Vedic multiplier based on a carry select adder with Simplified Sum-Carry Generation Logic (VCSA-SSCGL) is introduced. In addition, the particle swarm optimisation algorithm (PSO) is introduced for tuning the parameters in the network model. In the experimental scenario, the proposed model achieved an accuracy of 96.89%, precision of 95.84%, F-score of 96.08%, specificity of 96.73%, mean absolute error (MAE) of 0.87, dice similarity coefficient (DSC) of 0.93, and Jaccard coefficient (JC) of 0.9. Also, the FPGA design of a proposed model consumed only 0.6124W power and a LUT of 12,167. The experimental results prove the efficiency of a proposed method.

Open-Source Ethernet MAC IP Cores for FPGAs: Overview and Evaluation

Field-Programmable Gate Arrays (FPGAs) can be found in an increasing number of application domains, such as the telecom industry, the automotive electronics sector, or automation technology as well as in the area of reconfigurable computing. In recent years, it can be observed that the open-source idea which is known from the software domain for a long time also became popular in the world of hardware and FPGA design. In the era of the Internet of Things, many of today’s electronic devices implement some kind of network interface with Ethernet being known as one of the most widely used network standards. Thus, there is consequently a high demand on available Ethernet implementations for FPGA platforms. The goal of this work is to survey available open-source Ethernet MAC IP cores, evaluate existing designs in terms of performance, resource utilization, code quality, or maturity, and to present and summarize the evaluation results herein. Furthermore, advantages of commercial solutions and related publication work are discussed. To the authors’ best knowledge, this is the first publication that evaluates and compares existing open-source Ethernet MAC IP cores on a large scale. This work should help designers to select an appropriate open-source Ethernet MAC for an FPGA design and shows possible pitfalls and things to pay attention when using an open-source IP core in general. Finally, the authors would like to show that the open-source community can be also very helpful in the world of hardware in terms of design reuse or time to market.

Quantization-Aware NN Layers with High-throughput FPGA Implementation for Edge AI

Over the past few years, several applications have been extensively exploiting the advantages of deep learning, in particular when using convolutional neural networks (CNNs). The intrinsic flexibility of such models makes them widely adopted in a variety of practical applications, from medical to industrial. In this latter scenario, however, using consumer Personal Computer (PC) hardware is not always suitable for the potential harsh conditions of the working environment and the strict timing that industrial applications typically have. Therefore, the design of custom FPGA (Field Programmable Gate Array) solutions for network inference is gaining massive attention from researchers and companies as well. In this paper, we propose a family of network architectures composed of three kinds of custom layers working with integer arithmetic with a customizable precision (down to just two bits). Such layers are designed to be effectively trained on classical GPUs (Graphics Processing Units) and then synthesized to FPGA hardware for real-time inference. The idea is to provide a trainable quantization layer, called Requantizer, acting both as a non-linear activation for neurons and a value rescaler to match the desired bit precision. This way, the training is not only quantization-aware, but also capable of estimating the optimal scaling coefficients to accommodate both the non-linear nature of the activations and the constraints imposed by the limited precision. In the experimental section, we test the performance of this kind of model while working both on classical PC hardware and a case-study implementation of a signal peak detection device running on a real FPGA. We employ TensorFlow Lite for training and comparison, and use Xilinx FPGAs and Vivado for synthesis and implementation. The results show an accuracy of the quantized networks close to the floating point version, without the need for representative data for calibration as in other approaches, and performance that is better than dedicated peak detection algorithms. The FPGA implementation is able to run in real time at a rate of four gigapixels per second with moderate hardware resources, while achieving a sustained efficiency of 0.5 TOPS/W (tera operations per second per watt), in line with custom integrated hardware accelerators.

A New Recursive Trigonometric Technique for FPGA-Design Implementation

This paper presents a new recursive trigonometric (RT) technique for Field-Programmable Gate Array (FPGA) design implementation. The traditional implementation of trigonometric functions on FPGAs requires a significant amount of data storage space to store numerous reference values in the lookup tables. Although the coordinate rotation digital computer (CORDIC) can reduce the required FPGA storage space, their implementation process can be very complex and time-consuming. The proposed RT technique aims to provide a new approach for generating trigonometric functions to improve communication accuracy and reduce response time in the FPGA. This new RT technique is based on the trigonometric transformation; the output is calculated directly from the input values, so its accuracy depends only on the accuracy of the inputs. The RT technique can prevent complex iterative calculations and reduce the computational errors caused by the scale factor K in the CORDIC. Its effectiveness in generating highly accurate cosine waveform is verified by simulation tests undertaken on an FPGA.

A Domain-Specific Accelerator for Ultralow Latency Market Data Distribution System

Ultralow latency parsing of financial data is gaining significance in the high-frequency trading of the security exchange market. Hardware-aided systems exhibit superior improvement of latency over traditional software solutions, but flexibility may suffer when processing the financial protocol. This article presents a domain-specific accelerator for the market data distribution system, which integrates a financial information exchange adapted for streaming (FAST) decoder, a 10-Gbps network interface, and a high-speed PCIe host interface into a single field programmable gate array (FPGA) acceleration card. The proposed FAST decoder adopts the finite state machines-coordinated sequence mapping table to achieve run-time reconfigurability over fine-grained FPGA programming, and 16 fields can be decoded simultaneously in a pipelined manner, resulting in a decoding latency of only 33 ns. Evaluated on the Xilinx Alveo U200 acceleration card, this work improves the latency of decoding a FAST message by 26%–72% than state-of-the-art FPGA designs, and outperforms the software baseline by <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$&gt;27\times$</tex-math></inline-formula> in terms of latency covering both decoding and communication.

FCRoute: A Fast FPGA Connection Router Using Soft Routing-Space Pruning Algorithm

Routing is one of the most time-consuming stages in the field-programmable gate array (FPGA) design flow. Even if various attempts have been made to reduce route time, the existing work rarely focuses on improving the underlying A*-based FPGA connection router. In this article, we present a fast FPGA connection router called FCRoute based on a novel soft routing-space pruning algorithm. Within FCRoute, a routing resource priority mechanism is applied to classify the routing resource nodes into high-priority nodes and low-priority ones. On the whole, FCRoute is composed of fast maze search and backtracking process. During the fast maze search, we explore only the high-priority nodes in the routing space. In this way, a great deal of unnecessary work can be avoided. When the fast maze search fails to find the target sink, it allows the backtracking process to explore the low-priority nodes promising to be on the best path, after which a new fast maze search is called. By avoiding the exploration of the majority of low-priority nodes, FCRoute maintains runtime efficiency while ensuring global search ability. In addition, we further accelerate FCRoute with an engineering enhancement which simplifies the cost computations of nodes. Runtime and quality of results are compared with the state-of-the-art connection router in VPR 8. Experimental results show that on average FCRoute explores less than half the number of routing resource nodes, and therefore reduces runtime by 38% while enabling the quality of results. When combined with the enhancement, FCRoute achieves an average 45% reduction on runtime without sacrificing the quality of results.

Hardware Design and Implementation of FPGA Controlled Seven-Level Reduced Switch MLI

The paper proposes the design of a seven-level reduced switch multi-level inverter (7LRS-MLI) topology. The design produces a seven-level staircase output waveform with fewer components (seven power switches), thus reducing the cost and area and improving the performance of the design, i.e. increasing efficiency and reducing switching loss effectively. Both symmetric and asymmetric configurations have been implemented and the results are discussed in the paper. A comparison of the proposed structure with other recent seven-level structures has been illustrated. The simulation (using MATLAB/SIMULINK software) and experimental validation of 7LRS-MLI also have been performed for R, RL load, change in load and change in a modulation index (MI). Field programmable gate arrays (FPGA) have been used for digital implementation of the switching waveforms which reduces design time and improves flexibility. For switching devices, the alternative phase opposite disposition pulse width modulation (APOD-PWM) technique is used at 500 Hz and 5 kHz. The voltage and current total harmonic distortion (THD) profiles are also computed during the simulation and experimental validation.