Field Programmable Gate Array Clock Research Articles

A Mixed Approach for Clock Synchronization in Distributed Data Acquisition Systems.

Proper timing synchronization is important when data from sensors are acquired by different devices. This paper proposes a simple but effective solution for System on Chip (SoC) architectures that integrates a general-purpose Field Programmable Gate Array (FPGA) with a CPU. The proposed approach relies on a network synchronization protocol implemented in software, such as Network Time Protocol (NTP) or Precision Time Protocol (PTP), and uses the FPGA to generate a clock reference that is maintained in step with the synchronized system clock. The clock generated by the FPGA is obtained from the FPGA oscillator via appropriate fractional clock division. Clock drift is avoided via a software program that periodically compares the FPGA and the system counters, respectively, and adjusts the fractional clock divider in order to slightly adjust the FPGA clock frequency using a Proportional Integral controller. A specific implementation is presented on the RedPitaya platform, generating a 1 MHz clock in step with the NTP synchronized system clock. The presented system has been used in a distributed data acquisition system for fast transient recording in the neutral beam test facility for the ITER nuclear fusion experiment.

High‐speed, high‐resolution methodology for portable universal radar target‐echo simulator

AbstractIn this paper, digital parallelization and fractional delay‐based novel methods are proposed for the realization of high bandwidth, high‐resolution Ku‐band radar target simulator with 2.5 GHz intermediate frequency. High bandwidth waveform from radar is sampled by high‐speed Analog to Digital Converter, and samples are parallelized in Field Programmable Gate Array (FPGA) to work at the nominal clock frequency. In Digital RF Memory‐based target simulator, for finer range resolution, the FPGA clock frequency needs to be increased, which leads to increased system design complexity. The finer range resolution is accomplished without altering the system clock frequency using variable fractional delay filters and the digital parallelization methodology is proposed in this paper. The maximum target range that can be simulated is 20 km. As a result, memory requirements, computational complexity, and power dissipation are reduced. Finally, simulation and implementation results are presented.

High quality hypergraph partitioning for logic emulation

Dividing a large-scale design into parts for hardware prototyping and emulation is very important for integrated circuit design flow. In this paper, we present a suite of algorithms to solve the partitioning problem in general field programmable gate arrays (FPGAs) prototyping and hardware emulation. Our k-way hypergraph partitioner is based on a multi-level framework and its performance is similar to the well-known partitioners hMetis (Karypis et al., 1999) and KaHyPar (Akhremtsev et al., 2017). Based on this framework, we take up some algorithms which solve partitioning problems with varying objectives and constraints extracted from logic emulation scenarios. These objectives and constraints take FPGA resources, interconnection resources, flip-flops, and clock domains into account, which are all important factors in FPGA prototyping and hardware emulation. We test our algorithms using ISPD98 benchmarks and several industry cases. The experimental results show that our algorithms are efficient and effective in solving different partitioning problems.

GaN based micro-light-emitting diode size effect and array display

Single micro-light emitting diodes(LEDs) with different sizes and array micro-LED are designed and prepared, where the sizes of the single micro-LEDs are in a range of 40−100 μm, their electrodes are all co-N electrodes, P electrode is drawn out alone; the number of array pixels is <inline-formula><tex-math id="Z-20200831090558-1">\begin{document}$ 8\times8 $\end{document}</tex-math><alternatives><graphic xmlns:xlink="http://www.w3.org/1999/xlink" xlink:href="17-20200305_Z-20200831090558-1.jpg"/><graphic xmlns:xlink="http://www.w3.org/1999/xlink" xlink:href="17-20200305_Z-20200831090558-1.png"/></alternatives></inline-formula>, which is a passively driving structure with a pixel size of 60 μm. In the process of device preparation, N electrode and P electrode are fabricated by the sputtering & stripping method. The electrode thickness is 2.4 μm. Thick photoresist 5120 is used as a mask, and N GaN is etched to the substrate by using the ICP dry etching to form an isolation trench. The PECVD technique is used to deposit an SiO<sub>2</sub> insulating layer with a thickness of 10000 Å. By optimizing the electrode structure and thickness, the reliability of the P electrode at the slope of the isolation trench is improved, and the SiO<sub>2</sub> insulating layer has good encapsulation; field programmable gate array (FPGA) is used to drive and display the micro-LED passive array. The single micro-LEDs of different sizes are tested and analyzed in the aspects of electrics, photics and thermotics and the results of which show that the current density corresponding to the peak radiation flux of 80 μm micro-LED is 1869.2 A/cm<sup>2</sup>, which is 57.1% higher than that of 100 μm micro-LED, indicating that the current density corresponding to the peak radiation flux of micro-LED increases as the size decreases; compared with the ordinary blue LED, the micro-LED has a large <i>k</i> factor, and with the size decreases, the value of the <i>k</i> factor increases, indicating that the micro-LED series resistance is larger, and the thermal stability is not so good as the traditional blue LED. Finally, the field programmable gate array (FPGA) can achieve a good drive for the micro-LED passive array. The driving principle is passive scanning driving, which is carried out in a row-by-row lighting mode. The FPGA clock is 50 MHz, and 320 ns is required for the circuit to scan all rows.

A scalable arbitrary waveform generator for atomic physics experiments based on field-programmable gate array technology.

We present a field-programmable gate array (FPGA) based control system that has been implemented to control a strontium optical lattice clock at the National Physical Laboratory, UK. Bespoke printed circuit boards have been designed and manufactured, including an 8-channel, 16-bit digital to analog converter board with a 2 μs update rate and a 4-channel direct-digital synthesis board clocked at 1 GHz. Each board includes its own FPGA with 28 digital output lines available alongside the specialized analog or radio frequency outputs. The system is scalable to a large number of control lines by stacking the individual boards in a master-slave arrangement. The timing of the digital and analog outputs is based on the FPGA clock and is thus very predictable and exhibits low jitter. A particular advantage of our hardware is its large data buffers that, when combined with a pseudoclock structure, allow complex waveforms to be created. A high reliability of the system has been demonstrated during extended atomic clock frequency comparisons.

Toward FPGA Security in IoT: A New Detection Technique for Hardware Trojans

Nowadays, field programmable gate array (FPGA) has been widely used in Internet of Things (IoT) since it can provide flexible and scalable solutions to various IoT requirements. Meanwhile, hardware Trojan (HT), which may lead to undesired chip function or leak sensitive information, has become a great challenge for FPGA security. Therefore, distinguishing the Trojan-infected FPGAs is quite crucial for reinforcing the security of IoT. To achieve this goal, we propose a clock-tree-concerned technique to detect the HTs on FPGA. First, we present an experimental framework which helps us to collect the electromagnetic (EM) radiation emitted by FPGA clock tree. Then, we propose a Trojan identifying approach which extracts the mathematical feature of obtained EM traces, i.e., 2-D principal component analysis (2DPCA) in this paper, and automatically isolates the Trojan-infected FPGAs from the Trojan-free ones by using a BP neural network. Finally, we perform extensive experiments to evaluate the effectiveness of our method. The results reveal that our approach is valid in detecting HTs on FPGA. Specifically, for the trust-hub benchmarks, we can find out the FPGA with always on Trojans (100% detection rate) while identifying the triggered Trojans with high probability (by up to 92%). In addition, we give a thorough discussion on how the experimental setup, such as probe step size, scanning area, and chip ambient temperature, affects the Trojan detection rate.

Design and Characterization of a Low-Cost FPGA-Based TDC

We present a field-programmable gate array (FPGA) implementation of a time-to-digital converter (TDC) based on a low-cost, low-area Spartan 6 device. The converter is based on a tapped delay line model. Several implementation details are discussed with a particular focus on critical blocks such as the input stage and thermometer-to-binary decoding techniques. We implemented a tap filtering technique to improve the differential nonlinearity (DNL) of the single delay line while keeping a good LSB value of 25.57 ps with a single-shot precision (SSP) between 0.69 - 1.46 LSB. Measured DNL and integral nonlinearity (INL) lie in the range between -0.90 + 1.23 and -0.43 ÷ 2.96 LSB, respectively. Measured DNL and INL lie in the range between -0.90 ÷ 1.23 and -0.43 ÷ 2.96 LSB, respectively. We then implemented an interpolating TDC to overcome the limitations of a single delay line in terms of linearity and measurement range. The interpolating TDC uses the sliding scale technique, where the time interval to be measured is asynchronous with respect to the FPGA clock, achieving DNL and INL in the range -0.072 ÷ 0.070 and -0.755 ÷ 0.872 LSB. SSP is in the 1.096 ÷ 2.815 range. Moreover, we present a novel comparison between the DNLs obtained with two different methods: statistical code density test and using a finely controlled delay source. Finally, we present the results of a Monte Carlo simulation used to investigate the effects of nonlinear propagation of the signal through the delay line.

Prototyping of Nonlinear Time-Stepped Finite Element Simulation for Linear Induction Machines on Parallel Reconfigurable Hardware

The finite element method (FEM) is widely used for accurate design and analysis of electric machines; however, it suffers from long execution time. In this paper, for the first time hardware acceleration of two-dimensional FEM for a single-sided linear induction motor on the field programmable gate array (FPGA) is proposed. The nonlinearity of the iron core as well as the movement are taken into consideration. A new sparse solver is proposed based on left-looking Gilbert–Peierls algorithm for the system of linear equations of FEM that need to be solved in different iterations and time steps. Implementation of the model is performed in a massively paralleled and deeply pipelined hardware architecture using VHDL coding with single precision floating-point number representation. The proposed emulation was performed at various time steps resulting in significant average speedup of 9.73 times in comparison with JMAG-Designer as a commercial finite element software, and the overall hardware latency of each time step for the emulation was 49.2 ms in average with minimum achievable FPGA clock of 5.59 ns.

Optimization of Low-Density Parity Check decoder performance for OpenCL designs synthesized to FPGAs

Open Computing Language (OpenCL) is a high-level language that allows developers to produce portable software for heterogeneous parallel computing platforms. OpenCL is available for a variety of hardware platforms, with compiler support being recently expanded to include Field-Programmable Gate Arrays (FPGAs). This article investigates flexible OpenCL designs for the iterative min-sum decoding algorithm for (3,6)-regular Low-Density Parity Check (LDPC) codes over a range of codeword lengths. The target FPGA hardware is the Altera Stratix V GX A7 based Nallatech 385n board. The computationally demanding LDPC decoding algorithm offers several forms of parallelism that could be exploited by the Altera Offline Compiler (AOC version 15.1) for OpenCL. Our best decoder design produced a corrected codeword throughput of 68.22 Mbps at the compiler-selected FPGA clock frequency of 163.88 MHz for a length-2048 (3,6)-regular LDPC code. For a length-1024 (3,6)-regular LDPC code, our best design produced a throughput of 54.8 Mbps (32 decoding iterations) which significantly improves on the throughput of around 7 Mbps (30 decoding iterations) produced by an OpenCL based decoder design reported by Falcao et al. for the same size of LDPC code.

Real-Time FPGA-Based Analytical Space Harmonic Model of Permanent Magnet Machines for Hardware-in-the-Loop Simulation

This paper presents a real-time analytical space harmonic model of permanent magnet synchronous machines with shaped poles. The goal of this configuration is to produce an air-gap flux density distribution as close to sinusoidal as possible to enhance the machine performance. The analytical model is derived to predict the magnetic fields and the machine behavior by solving Maxwell's equations and applying the superposition theorem. The digital hardware realization of the model is developed on the field-programmable gate arrays (FPGAs) in a paralleled and pipelined paradigm for an efficient hardware design. Such real-time emulation on FPGA can be used in the design procedure and the assessment of newly prototyped controllers and drive systems in the hardware-in-the-loop platform. In this paper, the analytical model of the machine is simulated in real time on 7.5 ns input FPGA clock cycles, and the achieved executive time is 1.8 ${\mu }\text{s}$ . The captured real-time analytical results demonstrate the good accuracy of the emulator in comparison with the offline 2-D time-stepping transient finite-element solution obtained by JMAG software.

Feature detection for image analytics via FPGA acceleration

With the growth of multimedia data generation and consumption, image-based data analytics plays an increasingly important role in big data analytics systems. For image analytics, feature detection algorithms provide a foundation for a variety of image-based applications. These algorithms are typically computationally intensive and thus are good candidates for acceleration with field programmable gate arrays (FPGAs). In this paper, we investigate a Harris-Laplace variant of scale-invariant feature detection, a widely used image analytics algorithm, to demonstrate the capability of acceleration. Based on stream computing, we construct a fully pipelined implementation that can process one pixel per FPGA clock cycle. Our implementation significantly outperforms the existing published work. The proposed implementation adopts a single-precision floating-point representation and can detect the features of 640 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="TeX">$\times$</tex-math></inline-formula> 480-pixel images at 540 frames per second. This throughput is sufficient for multistream real-time video interpretation.

Graph-Based Approaches to Placement of Processing Element Networks on FPGAs for Physical Model Simulation

Physical models utilize mathematical equations to characterize physical systems like airway mechanics, neuron networks, or chemical reactions. Previous work has shown that field programmable gate arrays (FPGAs) execute physical models efficiently. To improve the implementation of physical models on FPGAs, this article leverages graph theoretic techniques to synthesize physical models onto FPGAs. The first phase maps physical model equations onto a structured virtual processing element (PE) graph using graph theoretic folding techniques. The second phase maps the structured virtual PE graph onto physical PE regions on an FPGA using graph embedding theory. A simulated annealing algorithm is introduced that can map any physical model onto an FPGA regardless of the model's underlying topology. We further extend the simulated annealing approach by leveraging existing graph drawing algorithms to generate the initial placement. Compared to previous work on physical model implementation on FPGAs, embedding increases clock frequency by 25% on average (for applicable topologies), whereas simulated annealing increases frequency by 13% on average. The embedding approach typically produces a circuit whose frequency is limited by the FPGA clock instead of routing. Additionally, complex models that could not previously be routed due to complexity were made routable when using placement constraints.

Design of PXI Digital Storage Oscilloscope Module Based on FPGA

A digital storage oscilloscope module in automatic test equipment was designed based on PIX bus. The field programmable gate array (FPGA) is used as the logic control unit. The circuit of high speed ADC and FPGA interface, clock management, and high speed data access were designed based on hardware modules. The digital storage oscilloscope module was successfully applied to the practical test system, whose performance was good, stable, and achieved the desired design goals.

An 8-Bit 1.72-Gsample/s Two Channel TimeInterleaved Analog-to-Digital Converter Based on PCB Circuit Board

This paper reports an 8-bit 1.72-Gsample/s TimeInterleaved analog-to-digital converter (TIADC) based on PCB with Field Programmable Gate Array (FPGA) technique. The system integrates two independent designed 8-bit 0.9-Gsample/s ADC chips in parallel, commercial FPGA and multi phase clock distributor circuit. In order to increase the systems performance, online calibration method is proposed to calibrate the mismatching errors in TIADC. The utilization of the FPGA is proven to be effective in removing the offset &amp; gain mismatch; the clock distributor circuit is used as the time delay for each Sub-ADC chip to eliminate the sampling-time error. The hardware design features are also described in details. The ADC chip is fabricated in 0.35 um SiGe BiCMOS. Finally, experimental results reveal that the proposed system is capable to be operated up to 1.72GSps.Under this sampling frequency (1.72GHz), the system can achieve spurious free dynamic range (SFDR) which is larger than 40dBc. The effective code (ENOB) is lager than 5.5 bit from DC to Nyquist frequency and the power dissipation is 2.28 W.

Field-programmable gate array based arbitrary signal generator and oscilloscope for use in slow light and storage of light experiments

We present a field-programmable gate array (FPGA) based device that simultaneously generates two arbitrary analog voltage signals with the maximum sample rate of 1.25 MHz and acquires two analog voltage signals with the maximum sample rate of 2.5 MHz. All signals are synchronized with internal FPGA clock. The personal computer application developed for controlling and communicating with FPGA chip provides the shaping of the output signals by mathematical expressions and real-time monitoring of the input signals. The main advantages of FPGA based digital-to-analog and analog-to-digital cards are high speed, rapid reconfigurability, friendly user interface, and low cost. We use this module in slow light and storage of light experiments performed in Rb buffer gas cell.

Monte Carlo simulation of the Ising model on FPGA

Two-dimensional Ising lattices are simulated on a field programmable gate array (FPGA) based system. Multiple spins are updated at each FPGA clock, leading to a linear increase of simulation time with the lattice size. A hybrid random number generator is designed and shown to have a better statistical quality than the tested pseudorandom generators. For a 1024×1024 Ising lattice, speedups of 1518× over single CPU, 11.8× over single GPU, and 1.5× over previously reported FPGA based simulation systems are achieved. Simulations of 1024×1024 Ising models with sampling periods up to 4.2 million Monte Carlo sweeps (MCS) and total spin updates of 17.2 billion MCS are carried out to study autocorrelation effects at the transition temperature. The mean magnetization is shown to converge to a stable value when the sampling period is reaching 105 MCS, and the standard deviation of the mean is shown to be described better with an equation from Kikuchi and Ito.

Ball grid array (BGA) solder joint intermittency real-time detection

This paper presents test results and specifications for SJ BIST (solder joint built-in-self-test), an innovative sensing method for detecting faults in solder-joint networks that belong to the I/O ports of field programmable gate arrays (FPGAs), especially in ball grid array packages. It is well known that fractured solder joints typically maintain sufficient electrical contact to operate correctly for long periods of time. Subsequently, the damaged joint begins to exhibit intermittent failures: the faces of a fracture separate during periods of stress, causing incorrect FPGA signals. SJ BIST detects faults at least as low as 100 Ω with zero false alarms: minimum detectable fault period is one-half the period of the FPGA clock – guaranteed detection is two clock periods. SJ BIST correctly detects and reports instances of high-resistance with no false alarms: test results are shown in this paper. Being able to detect solder-joint faults in FPGAs increases fault coverage and health management capabilities, and provides support for condition-based and reliability-centered maintenance.

Optimisation of the stress distribution in ceramic hip joint balls by implementation of biological growth

This paper presents test results and specifications for SJ BIST (solder joint built-in-self-test), an innovative sensing method for detecting faults in solder-joint networks that belong to the I/O ports of field programmable gate arrays (FPGAs), especially in ball grid array packages. It is well known that fractured solder joints typically maintain sufficient electrical contact to operate correctly for long periods of time. Subsequently, the damaged joint begins to exhibit intermittent failures: the faces of a fracture separate during periods of stress, causing incorrect FPGA signals. SJ BIST detects faults at least as low as 100 Ω with zero false alarms: minimum detectable fault period is one-half the period of the FPGA clock – guaranteed detection is two clock periods. SJ BIST correctly detects and reports instances of high-resistance with no false alarms: test results are shown in this paper. Being able to detect solder-joint faults in FPGAs increases fault coverage and health management capabilities, and provides support for condition-based and reliability-centered maintenance.