Field Programmable Gate Array Board Research Articles

Hardware and software co-design for detecting hypertension from photoplethysmogram

Hypertension is one of the leading causes of cardiovascular disease morbidity in the world. If remains untreated, it may cause severe damage like heart attack or even death. Early detection is required to prevent the development of other cardiac abnormalities. Photoplethysmogram (PPG) is a bio signal that can be obtained optically by a sensor. It is studied to monitor the change of volume of blood and detect heart conditions. Previous studies have already applied PPG to detect hypertension at the software level. In this article, along with software-based detection, we have implemented a digital hardware-based system for detecting hypertension from signals recorded using PPG sensor. Xilinx ZedBoard Zynq-7000 field programmable gate array (FPGA) board is utilized for designing the embedded system. The hypertension detection accuracy is 98.02% at the software level while for the digital system, it is 96.05% consuming 0.374 W power. The study can be analyzed for other cardiac disease detection and medical equipment development.

Rapid Prototyping and Hardware-In-the-Loop Verification of Enhanced Sliding Mode Control of an Asynchronous Machine Using a Xilinx System Generator and an FPGA-Zynq Board

This article describes rapid prototyping using the Xilinx system generator (XSG) of a direct field oriented control (DFOC) strategy based on improved super twisting sliding mode controllers (ISTSMCs) of an asynchronous machine to succeed a hardware implementation on a field programmable gate array (FPGA) board. The main goal is to enhance regulation loops governing rotor speed, rotor flux, and stator current components within the classical DFOC structure. These ISTSMCs replace integral proportional controllers, resulting in improved system dynamics, faster speed and torque responses, and heightened robustness against load and rotor resistance variations, surpassing other control methods. Additionally, the article aims to implement this DFOC-ISTSMC method on an FPGA board to reduce control system sampling time and loop delays, leveraging the FPGA’s parallel processing capabilities. The hardware architecture is designed using XSG in the MATLAB/Simulink environment, enabling effective simulation, testing, discrete algorithm creation, and VHDL code generation for FPGA implementation via the hardware-in-the-loop (HIL) process. Assessment involves digital simulation studies and HIL processes using XSG with a Xilinx FPGA Zynq 7000 under MATLAB/Simulink, demonstrating improved system performance, reduced time delays, and efficient FPGA utilization. This approach validates the effectiveness of the proposed DFOC-ISTSMC algorithm in enhancing control strategy for asynchronous machines.

Adaptive neuro fuzzy technology to enhance PID performances within VCA for grid-connected wind system under nonlinear behaviors: FPGA hardware implementation

Wind Energy Conversion Systems (WECSs) exhibit nonlinear behavior due to internal and external disturbances, which can significantly impact the control performance. Firstly, this paper proposes a Vector Control Approach (VCA) based on Adaptive Neuro Fuzzy (ANF) of Proportional Integral Derivative (PID) controllers for a variable speed Permanent Magnet Synchronous Generator (PMSG)-based WECS connected to the grid to address these issues. The proposed ANF-PID controller combines the robustness of the fuzzy logic with the neural network's performance to ensure high accuracy, excellent tracking, and robustness against the WECS's nonlinear behavior. The neural network automates the placement of fuzzy logic membership functions. Secondly, this paper suggests a real-time hardware implementation of the VCA based on ANF-PID using a Field Programmable Gate Array (FPGA) to reduce the processing time and the WECS's sampling period. The effectiveness of the VCA based on ANF-PID controllers is validated by conducting a numerical simulation within the Matlab-Simulink using the Xilinx System Generator tool, alongside an experimental in-the-loop hardware implementation using FPGA board. Different scenarios are conducted to validate the robustness and stability of the proposed VCA based on ANF-PID control schemes, which is compared to Conventional Fuzzy PID (C-FPID) and PID controllers. The results exhibit that the VCA based on ANF-PID controllers outperforms VCA-C-FPID and VCA-PID controllers in terms of precision, tracking accuracy, and robustness against the WECS's nonlinear behavior and the PMSG parameter variations. The performances of the proposed controllers are tested under some criteria. In fact, the proposed ANF-PID controller provides a Mean Absolute Error (MAE), a Mean Squared Error (MSE) and a Root Mean Squared Error (RMSE) of 8.1911 × 10−04, 8.4181 × 10−05 and 0.0092, respectively. Compared to the C-FPID controller, the proposed controller offers an improvement gain of 98.96 %, 99.61 %, and 93.79 % of MAE, MSE, and RMSE, respectively. When compared to the PID controller, its improvement is even more significant, with a reduction of 99.9919 %, 99.9999 %, and 99.9288 % of MAE, MSE, and RMSE, respectively. In addition, the ANF-PID-based VCA utilizes hardware resources on the FPGA efficiently, requiring only 65.60 % slices LUT, 0.28 % LUTRAM, and 22.99 % FF. This makes it a more cost-effective option compared to the VCA-C-FPID controller for diverse control systems.

FPGA-Based Implementation of a Digital Insulin-Glucose Regulator for Type 2 Diabetic Patients

This paper reports on the hardware implementation of a digital insulin-glucose regulator for type 2 diabetic patients by using a Field Programmable Gate Array board. For a real time-control of the patient insulin concentration, the insulin-regulator needs to measure only his blood glucose concentration. With respect to other reported solutions using general-purpose programmable hardware’s, the proposed insulin-glucose regulator allows to design a software-free, fully-hardware architecture of the system here described in detail. A prototype has been developed so to validate its functionality in the following two operating modes: (i) in the open loop condition for which only the insulin-glucose regulator is operating; (ii) in the closed loop condition for which the insulin-glucose regulator acting as an artificial pancreas is connected to a population of one hundred virtual patients individuated by employing a comprehensive theoretical model recognized by the U.S. Food and Drug Administration for the pre-clinical validation of glucose control strategies. These virtual patients present the same trend of the variation of the glucose concentration achieving different maximum and minimum values of glucose concentrations when eating a meal. The paper presents and discusses the experimental results by comparing them with those ones obtained by implementing the theoretical model through numerical simulations performed in SIMULINK. Relative errors lower than ±1% have been achieved by performing this comparison so demonstrating a very high accuracy of the proposed insulin-glucose regulator digital system. The implemented hardware solution of the digital controller can process the input data related to the glucose concentration of each virtual patient in about 1.1 μs with an estimated power consumption of about 36 mW. These achievements open the way for further investigations on digital architectures for glucose regulators to be integrated in VLSI as System-on-Chips and/or Lab-on-Chips for portable, wearable, and implantable solutions in real biomedical applications.

Investigation on Vision System: Digital FPGA Implementation in Case of Retina Rod Cells.

The development of prostheses and treatments for illnesses and recovery has recently been centered on hardware modeling for various delicate biological components, including the nervous system, brain, eyes, and heart. The retina, being the thinnest and deepest layer of the eye, is of particular interest. In this study, we employ the Nyquist-Based Approximation of Retina Rod Cell (NBAoRRC) approach, which has been adapted to utilize Look-Up Tables (LUTs) rather than original functions, to implement rod cells in the retina using cost-effective hardware. In modern mathematical models, numerous nonlinear functions are used to represent the activity of these cells. However, these nonlinear functions would require a substantial amount of hardware for direct implementation and may not meet the required speed constraints. The proposed method eliminates the need for multiplication functions and utilizes a fast, cost-effective rod cell device. Simulation results demonstrate the extent to which the proposed model aligns with the behavior of the primary rod cell model, particularly in terms of dynamic behavior. Based on the results of hardware implementation using the Field-Programmable Gate Arrays (FPGA) board Virtex-5, the proposed model is shown to be reliable, consume 30 percent less power than the primary model, and have reduced hardware resource requirements. Based on the results of hardware implementation using the reconfigurable FPGA board Virtex-5, the proposed model is reliable, uses 30% less power consumption than the primary model in the worth state of the set of approximation method, and has a reduced hardware resource requirement. In fact, using the proposed model, this reduction in the power consumption can be achieved. Finally, in this article, by using the LUT which is systematically sampled (Nyquist rate), we were able to remove all costly operators in terms of hardware (digital) realization and achieve very good results in the field of digital implementation in two scales of network and single neuron.

Remote field-programmable gate array laboratory for signal acquisition and design verification

A remote laboratory utilizing field-programmable gate array (FPGA) technologies enhances students’ learning experience anywhere and anytime in embedded system design. Existing remote laboratories prioritize hardware access and visual feedback for observing board behavior after programming, neglecting comprehensive debugging tools to resolve errors that require internal signal acquisition. This paper proposes a novel remote embedded-system design approach targeting FPGA technologies that are fully interactive via a web-based platform. Our solution provides FPGA board access and debugging capabilities beyond the visual feedback provided by existing remote laboratories. We implemented a lab module that allows users to seamlessly incorporate into their FPGA design. The module minimizes hardware resource utilization while enabling the acquisition of a large number of data samples from the signal during the experiments by adaptively compressing the signal prior to data transmission. The results demonstrate an average compression ratio of 2.90 across three benchmark signals, indicating efficient signal acquisition and effective debugging and analysis. This method allows users to acquire more data samples than conventional methods. The proposed lab allows students to remotely test and debug their designs, bridging the gap between theory and practice in embedded system design.

Accelerating autonomous vehicles: Harnessing FPGA power for deep learning advancements

In the rapidly developing field of autonomous vehicles (AV), the integration of deep learning algorithms has become the cornerstone for improving vehicle perception and decision-making ability. This study investigates the potential of field-programmable gate arrays (FPGAs) as hardware accelerators for deep-learning tasks in self-driving cars. This study used a Zynq UltraScale+ MPSoC FPGA board from Xilinx, known for its performance and adaptability, and combined it with a high-resolution camera to simulate real-world visual data encountered by AVs. The approach involved implementing a convolutional neural network (CNN) to perform tasks such as object detection, lane detection, and traffic sign classification. The model was quantized and converted to VHDL code using Xilinx Vivado HLS to optimize the deep learning algorithm for FPGA.The results show that the FPGA-based model significantly outperforms the traditional CPU-based model in terms of processing speed and energy efficiency without sacrificing accuracy. This study highlights the critical role of FPGAs in supporting deep learning tasks in self-driving cars and paves the way for safer and more efficient transportation solutions in the future.

Operation of a Ramsey-CPT microcell atomic clock with driving current-based power modulation of a VCSEL

We report on the operation of a coherent population trapping (CPT) microcell atomic clock using a pulsed Ramsey-like interrogation. The Ramsey-CPT sequence, defined by two-step optical pulses separated by a free-evolution dark time, is produced by switching on and off the output power of a low-power vertical-cavity surface-emitting laser, through direct modulation of its driving current. High-contrast and narrow Ramsey-CPT fringes are detected without the use of any external optical modulator stage. We demonstrate closed-loop operation of the clock based on high-speed digital signal processing implemented in a field programmable gate array board. The clock's short-term fractional frequency stability is 1.3 × 10−10τ−1/2 until 2000 s. A power light-shift coefficient of 8 × 10−11/μW, in relative value, is obtained for a dark time of 150 μs. This value is about ten times lower than in the continuous regime. These results show the feasibility of fully integrated atomic clocks based on Ramsey spectroscopy, which could provide enhanced long-term stability.

Finite control set model predictive control of three-port converter for interfacing a PV–battery energy storage system to a three-phase stand-alone AC system

Abstract This paper proposes a multiport bidirectional non-isolated converter topology that provides advantages in terms of simultaneous multiple operations, single-stage conversion, high power density and reduced power losses due to the lower number of switches. The proposed multiport converter uses a centralized non-linear controller known as a finite control set model predictive controller to manage the flow of power between different ports. It deals with the parallel operation of photovoltaic and battery energy storage systems for stand-alone alternating current (AC) systems. The converter connects the lower voltage battery to the photovoltaic port using a bidirectional buck/boost converter and the photovoltaic port is linked to the stand-alone AC load through a three-phase full-bridge inverter. Each leg of the three-phase converter will act as a bidirectional direct current (DC)/DC converter as well as an inverter simultaneously. Only six switches manage the power transfer between all the connected ports of photovoltaic–battery energy storage system linked to the stand-alone AC load. The proposed multiport converter is mathematically modelled and controlled by a finite control set model predictive controller. The system is validated in simulation (1-kW rating) and experimental environment (200-W rating). The hardware prototype is developed in the laboratory and the controller is implemented on the field-programmable gate array board. Two independent case studies are carried out to validate the efficacy of the system. The first scenario is for a change in solar irradiance, while the second scenario is for a change in the output load.

A Semi-Implicit Parallel Leapfrog Solver With Half-Step Sampling Technique for FPGA-Based Real-Time HIL Simulation of Power Converters

Field Programmable Gate Array (FPGA) based Hardware-in-the-loop (HIL) simulation is an effective tool to verify the performance of physical controllers and shorten the development cycle of power converters. In HIL simulations, sampling accuracy is of concern and is desired to be improved by reducing the step size. However, due to the cost of computational time, the step size is hard to reduce indefinitely to meet the requirements for high switching frequency applications. To improve the sampling accuracy and simulation performance of HIL simulation, this paper proposes a semi-implicit parallel leapfrog (SPL) solver with half-step sampling technique. In this solver, the switches and the rest part of the system are implemented to be computed parallel when the switch leg model operates in continuous current mode. Besides, the solver is formulated in leapfrog format to reduce computational costs and to compute at half-step as a minimum step-size. With this format, the half-step sampling technique can be employed to increase the sampling rate by onefold, even in cases where it is challenging to reduce the simulation step size further. A dual active bridge converter case is implemented on the FPGA board with a 12.5-ns sampling step-size, retaining the simulation accuracy while switched at 400 kHz. To further verify the advantages, the results are compared with other HIL method and experimental results.

Real-time field-programmable gate array-based closed-loop deep brain stimulation platform targeting cerebellar circuitry rescues motor deficits in a mouse model of cerebellar ataxia.

The open-loop nature of conventional deep brain stimulation (DBS) produces continuous and excessive stimulation to patients which contributes largely to increased prevalence of adverse side effects. Cerebellar ataxia is characterized by abnormal Purkinje cells (PCs) dendritic arborization, loss of PCs and motor coordination, and muscle weakness with no effective treatment. We aim to develop a real-time field-programmable gate array (FPGA) prototype targeting the deep cerebellar nuclei (DCN) to close the loop for ataxia using conditional double knockout mice with deletion of PC-specific LIM homeobox (Lhx)1 and Lhx5, resulting in abnormal dendritic arborization and motor deficits. We implanted multielectrode array in the DCN and muscles of ataxia mice. The beneficial effect of open-loop DCN-DBS or closed-loop DCN-DBS was compared by motor behavioral assessments, electromyography (EMG), and neural activities (neurospike and electroencephalogram) in freely moving mice. FPGA board, which performed complex real-time computation, was used for closed-loop DCN-DBS system. Closed-loop DCN-DBS was triggered only when symptomatic muscle EMG was detected in a real-time manner, which restored motor activities, electroencephalogram activities and neurospike properties completely in ataxia mice. Closed-loop DCN-DBS was more effective than an open-loop paradigm as it reduced the frequency of DBS. Our real-time FPGA-based DCN-DBS system could be a potential clinical strategy for alleviating cerebellar ataxia and other movement disorders.

Python Red Pitaya Lockbox (PyRPL): An open source software package for digital feedback control in quantum optics experiments.

We present the Python Red Pitaya Lockbox (PyRPL), an open source software package that allows the implementation of automatic digital feedback controllers for quantum optics experiments on commercially available, affordable Field-Programmable Gate Array (FPGA) boards. Our software implements the digital generation of various types of error signals, from an analog input through the application of loop filters of high complexity and real-time gain adjustment for multiple analog output signals, including different algorithms for resonance search, lock acquisition sequences, and in-loop gain optimization. Furthermore, all necessary diagnostic instruments, such as an oscilloscope, a network analyzer, and a spectrum analyzer, are integrated into our software. Apart from providing a quickly scalable, automatic feedback controller, the lock performance that can be achieved by using PyRPL with imperfect equipment, such as piezoelectric transducers and noisy amplifiers, is better than the one achievable with standard analog controllers due to the higher complexity of implementable filters and possibilities of nonlinear operations in the FPGA. This drastically reduces the cost of added complexity when introducing additional feedback loops to an experiment. The open-source character also distinguishes PyRPL from commercial solutions, as it allows users to customize functionalities at various levels, ranging from the easy integration of PyRPL-based feedback controllers into existing setups to the modification of the FPGA functionality. A community of developers provides fast and efficient implementation and testing of software modifications.

Developing a Portable Fluorescence Imaging Device for Fish Freshness Detection.

Rapid detection of fish freshness is of vital importance to ensuring the safety of aquatic product consumption. Currently, the widely used optical detecting methods of fish freshness are faced with multiple challenges, including low detecting efficiency, high cost, large size and low integration of detecting equipment. This research aims to address these issues by developing a low-cost portable fluorescence imaging device for rapid fish freshness detection. The developed device employs ultraviolet-light-emitting diode (UV-LED) lamp beads (365 nm, 10 W) as excitation light sources, and a low-cost field programmable gate array (FPGA) board (model: ZYNQ XC7Z020) as the master control unit. The fluorescence images captured by a complementary metal oxide semiconductor (CMOS) camera are processed by the YOLOv4-Tiny model embedded in FPGA to obtain the ultimate results of fish freshness. The circuit for the YOLOv4-Tiny model is optimized to make full use of FPGA resources and to increase computing efficiency. The performance of the device is evaluated by using grass carp fillets as the research object. The average accuracy of freshness detection reaches up to 97.10%. Moreover, the detection time of below 1 s per sample and the overall power consumption of 47.1 W (including 42.4 W light source power consumption) indicate that the device has good real-time performance and low power consumption. The research provides a potential tool for fish freshness evaluation in a low-cost and rapid manner.

Implementation of a non-linear SVM classification for seizure EEG signal analysis on FPGA

An automatic detection method for disease diagnosis plays an important role in the medical field. A computer-aided diagnosis (CAD) system for seizure detection using electroencephalogram (EEG) data is significant in protecting patients' lives. This paper presents machine learning algorithm-based seizure detection approach implemented in both software and hardware using EEG recordings. The input EEG signal is subjected to pre-processing, decomposition using wavelet transform and classification by a support vector machine (SVM) classifier. The maximum and variance statistical values of the decomposed EEG sub-bands are computed to generate a feature vector, while classification accuracy and computational complexity are taken into account. Gaussian Radial Basis Function (RBF) kernel based Non-Linear SVM (NLSVM) is used in this proposed approach to solve both two-class and three-class classification problems. In three-class classification, the one-against-one (OAO) technique is used. The competency of the proposed technique is evaluated using two distinct datasets provided by Bonn University, Germany & Neurology and Sleep Centre, New Delhi. The adequate parameters of the NLSVM classifier model are determined by using MATLAB software in the training phase and the best performing NLSVM model is selected for implementation on the Field-Programmable Gate Array (FPGA). The proposed seizure detection method is implemented with Verilog code and examined on a Xilinx Zynq-7000 XC7Z020 FPGA board to evaluate its performance. The experimental results show that the proposed method with a minimal number of features achieved a good performance metric for seizure detection and is comparable with that of the state-of-the-art methods.

A Fast FPGA Hardware Accelerator for Remote Heart Rate Detection Based on RGB Vision.

A fast hardware accelerator is created by this work via field programmable gate array (FPGA) to estimate heart rate (HR) through the video recorded by a RGB camera based on the technology of remote photoplethysmography (rPPG). The method of rPPG acquires physiological signals of a human body by analyzing the subtle color changes on the surface of the human skin. The hardware implementation of rPPG to estimate HR is proposed herein to aim for a much faster calculation speed than software for a number of applications, like heart failure pre-warning of an in-action athlete and drowsiness detection of a driver. In this accelerator, ICA (Independent Component Analysis) is used to recover the blood volume pulse from the raw signals of remote PPG, and then obtain the heart rate value. The architecture of the hardware circuit is described in Verilog HDL and verified by Quartus II, and also implemented in an Altera DE10-Standard FPGA board, which consists of image capture, heart rate algorithm and image display. A TRDB-D5M camera is utilized for image capture. Two experiments were conducted with image collecting duration of 16 seconds and 8 seconds respectively, and the commercial device Omron HEM-6111 was used as the golden value. The proposed system achieves an accuracy in (ME±1.96SD) of -0.76±5.09 and -0.70±8.71 bpm in the short periods of 16-second and 8-second versions, respectively, which outperforms all the reported prior works in combined computation time and accuracy.

2D router chip design, analysis, and simulation for effective communication

<p class="Correspondencedetails"><span lang="EN-US">The router is a network device that is used to connect subnetwork and packet-switched networking by directing the data packets to the intended IP addresses. It succeeds the traffic between different systems and allows several devices to share the internet connection. The router is applicable for the effective commutation in system on chip (SoC) modules for network on chip (NoC) communication. The research paper emphasizes the design of the two dimensional (2D) router hardware chip in the Xilinx integrated system environment (ISE) 14.7 software and further logic verification using the data packets transmitted from all input/output ports. The design evaluation is done based on the pre-synthesis device utilization summary relating to different field programmable gate array (FPGA) boards such as Spartan-3E (XC3S500E), Spartan-6 (XC6SLX45), Virtex-4 (XC4VFX12), Virtex-5 (XC5VSX50T), and Virtex-7 (XC7VX550T). The 64-bit data logic is verified on the different ports of the router configuration in the Xilinx and Modelsim waveform simulator. The Virtex-7 has proven the fast-switching speed and optimal hardware parameters in comparison to other FPGAs.</span></p>

Experimental EMFI detection on a RISC-V core using the Trace Verifier solution

Physical attacks are powerful threats that can cause changes in the execution behavior of a program. Control-Flow Integrity (CFI) is used to check the program’s flow execution, ensuring that it remains unaltered by these attacks. The RISC-V Trace Encoder (TE) provides valuable information about the user program’s execution path, and is used as part of a CFI solution. An enhanced version of the TE specifications permits detecting intricate fault models such as the corruption of any discontinuity instruction, using an additional Trace Verifier (TV) hardware module. In this paper, we present a buffer overflow software attack simulation and experimental ElectroMagnetic Fault Injection (EMFI) attacks conducted on an Field Programmable Gate Array (FPGA) board that implements a RISC-V core linked to the enhanced TE and TV modules. Unlike existing CFI solutions, our proposed approach does not require modifications to the RISC-V compiler, user application code or the RISC-V core. The average overhead of our solution in terms of hardware area, memory and power consumption are equal to 13.6%, 3.5% and 9% respectively.

Fuzzy current analysis-based fault diagnostic of induction motor using hardware co-simulation with field programmable gate array

Introduction. Presently, signal analysis of stator current of induction motor has become a popular technique to assess the health state of asynchronous motor in order to avoid failures. The classical implementations of failure detection algorithms for rotating machines, based on microprogrammed sequential systems such as microprocessors and digital signal processing have shown their limitations in terms of speed and real time constraints, which requires the use of new technologies providing more efficient diagnostics such as application specific integrated circuit or field programmable gate array (FPGA). The purpose of this work is to study the contribution of the implementation of fuzzy logic on FPGA programmable logic circuits in the diagnosis of asynchronous machine failures for a phase unbalance and a missing phase faults cases. Methodology. In this work, we propose hardware architecture on FPGA of a failure detection algorithm for asynchronous machine based on fuzzy logic and motor current signal analysis by taking the RMS signal of stator current as a fault indicator signal. Results. The validation of the proposed architecture was carried out by a co-simulation hardware process between the ML402 boards equipped with a Virtex-4 FPGA circuit of the Xilinx type and Xilinx system generator under MATLAB/Simulink. Originality. The present work combined the performance of fuzzy logic techniques, the simplicity of stator current signal analysis algorithms and the execution power of ML402 FPGA board, for the fault diagnosis of induction machine achieving the best ratios speed/performance and simplicity/performance. Practical value. The emergence of this method has improved the performance of fault detection for asynchronous machine, especially in terms of hardware resource consumption, real-time online detection and speed of detection.

Generation of self-similarity in a chaotic system of attractors with many scrolls and their circuit’s implementation

The concept of self-similarity, widely employed in specialized fields of applied sciences, has been investigated through numerous works utilizing both analytical elements and experimental observations. As a significant component of both fractal and chaos theories, self-similarity can naturally manifest around us or be artificially simulated using mathematical arguments and algorithms. In this paper, we utilize analytical, numerical, and experimental circuit elements to study, analyze, and simulate a generalized chaotic system of attractors with multiple scrolls. This system presents various types of processes, including chaotic and hyperchaotic dynamics, as well as hidden attractors. We discuss the well-posedness of the system before examining its numerical solvability, error tolerance, and simulations for the model involving fractal and fractional operations. Simulations are conducted for various values of the model’s parameters, demonstrating that the system displays fractal features combined with chaotic behavior. The system is implemented using a Field Programmable Gate Array (FPGA) board, generating self-similar results akin to those obtained numerically.

Cuckoo Bloom Hybrid Filter: Algorithm and Hardware Architecture for High Performance Satellite Internet Protocol Route Lookup

The next-generation satellite Internet Protocol (IP) router is required to achieve tens of millions of route lookups per second, since satellite Internet services based on low Earth orbit (LEO) constellations have become a reality. Due to the limitation of hardware resources on satellites and the high reliability requirements for equipment, a new satellite IP route lookup architecture is proposed in this paper. The proposed architecture uses a Bloom and cuckoo filter-based structure called cuckoo Bloom hybrid filter (CBHF), which guarantees only one off-chip memory access per lookup, to accelerate the Prefix-Route Trie (PR-Trie) algorithm. The proposed architecture has been evaluated through both a behavioral simulation in C++ language and a hardware implementation in Verilog hardware description language (HDL). Our simulation and implementation results show that the proposed satellite IP route lookup architecture can achieve a single-port throughput beyond 13 Gbps on a field programmable gate array (FPGA) board with a single DDR3 memory chip when operating at 200 MHz. In addition, the resource utilization in the FPGA shows that the proposed architecture also supports triple modular redundancy (TMR) to enhance reliability.