Field Programmable Analog Array Research Articles

Implementation and Experimentation of an Embedded Data Acquisition/Preprocessing System Based on a Hybrid Reconfigurable Hardware Accelerator for Inertial Measurements

The use of microelectromechanical systems' sensors is growing steadily since it is the cheapest way to get information about the inertial state of a moving object. However, preprocessing inertial data using hybrid reconfigurability is challenging. This article is an analysis of the noise generated by a multisensory data acquisition and preprocessing system that has been implemented to interface inertial sensors (particularly accelerometers and gyroscopes). A multichannel reconfigurable voltage attenuator (MRVA) based on the field-programmable analog array, an alternative to classical voltage dividers, has been created to interface the sensors with the field-programmable gate array. This article describes a hardware accelerator implementation of two calibration/denoising processes based on the moving average filters in order to select the best choice for the preparation of inertial measurement units data, where a precision of 99.72% was reached. The MRVA is interfaced via Xilinx analog-to-digital converter, where an intellectual property has been designed for hardware acceleration using Xilinx system generator.

Survey on Field Programmable Analog Array Architectures Eliminating Routing Network

This work focuses on reviewing the field programmable analog array (FPAA) architectures that eliminate the use of switches in signal path. The conventional FPAA architecture is composed of configurable analog blocks (CABs) connected together through switches in routing networks.The architectures covered in this survey have replaced the use of routing network by direct connection between CABs, and use of programmable analog building blocks. The first architecture covered is presented by Becker et al. with a hexagonal topology using operational transconductance amplifier (OTA) as a building block. The second architecture is presented by Mahmoud and Soliman, which uses the second generation current conveyor (CCII+) as a building block for their CABs arranged in a hexagonal architecture as well. Lastly, a more recent FPAA with a rectangular architecture proposed by Diab and Mahmoud is discussed, it uses the OTA as a building block for their rectangular architecture. The three FPAAs targeted continuous-time analog signal processing, having two architectures targeting high frequency applications, while the last targeting low frequency applications. The architectures, CAB structures, and the applications of each FPAA is covered separately in each section.

Multi-Objective Path Planning for Autonomous Robots Using Reconfigurable Analog VLSI

This paper presents a Multi-Objective path planning approach using reconfigurable Analog-Very-Large-Scale-Integrated (AVLSI) circuits. It is significant because it is the first example of floating-gate based analog resistive grid circuits used for Multi-Objective path planning. The two path planning objectives are 1) minimizing path length and 2) minimizing path cost. Three hardware experimental results are presented that implement the approach using a Field Programmable Analog Array (FPAA) circuit. First, an example demonstrates a simple proof-of-concept. Second, an example shows how the FPAA solution compares to an entire solution set for a specific Start and Goal path planning problem. Third, an example shows how the FPAA solution compares to two edge-cases. The edge-cases are the two ideals: ideal lowest cost path, and ideal shortest distance path. Based on these foundational proof-of-concept hardware results, larger environment grids than are currently implementable on the FPAA hardware were simulated to predict performance if a custom FPAA application specific integrated circuit (ASIC) was built for this Multi-Objective path planning purpose. Finally, analysis is presented to address this method's computational complexity.

A Real-Time Vital-Sign Monitoring in the Physical Domain on a Mixed-Signal Reconfigurable Platform.

This work presents a mixed-signal physical-compu-tation-electronics for monitoring three vital signs; namely heart rate, blood pressure, and blood oxygen saturation; from electrocardiography, arterial blood pressure, and photoplethysmography signals in real-time. The computational circuits are implemented on a reconfigurable and programmable signal-processing platform, namely field-programmable analog array (FPAA). The design leverages the core enabling technology of FPAA, namely floating-gate CMOS devices, and an on-chip low-power microcontroller to achieve energy-efficiency while not compromising accuracy. The custom physical-computation-electronics operating in CMOS subthreshold region, performs low-level (i.e., physiologically-relevant feature extraction) and high-level (i.e., detecting arrhythmia) signal processing in an energy-efficient manner. The on-chip microcontroller is used (1) in the programming mode for controlling the charge storage at the analog-memory elements to introduce patient-dependency into the system and (2) in the run mode to quantify the vital signs. The system has been validated against digital computation results from MATLAB using datasets collected from three healthy subjects and datasets from the MIT/BIH open source database. Based on all recordings in the MIT/BIH database, ECG R-peak detection sensitivity is 94.2%. The processor detects arrhythmia in three MIT/BIH recordings with an average sensitivity of 96.2%. The cardiac processor achieves an average percentage mean error bounded by 3.75%, 6.27%, and 7.3% for R-R duration, systolic blood pressure, and oxygen saturation level calculations; respectively. The power consumption of the ECG, blood-pressure and photo-plethysmography processing circuitry are 126 nW, 251nW and 1.44μW respectively in a 350nm process. Overall, the cardiac processor consumes 1.82μW.

Development of a XYZ scanner for home-made atomic force microscope based on FPAA control

Abstract Atomic force microscopy (AFM) is one of the useful tools in the fields of nanoscale measurement and manipulation. High speed scanning is one of the crucial requirements for live cell imaging and soft matter characterization. The scanning speed is limited by the bandwidth of the AFM’s detection and actuation components. Generally, the bandwidth of a traditional scanner is too low to conduct the live cell imaging. This paper presents a simple and integrated compact home-made AFM for high speed imaging. To improve the bandwidth of the scanner, a parallel kinematics mechanism driven by piezoelectric actuators (PZTs) is proposed for the fast positioning in the X, Y and Z directions. The mechanical design optimization, modeling and analysis, and experimental testing have been conducted to validate the performance of the proposed scanner. A number of experimental results showed that the developed scanner has the capability for broad bandwidth with low coupling errors in the actuation directions. A hybrid control strategy including feedforward and feedback loops has been designed to significantly improve the dynamic tracking performance of the scanner and a field programmable analog array (FPAA) system is utilized to implement the control algorithm for excellent and stable tracking capability. Further, a number of high speed measurements have been conducted to verify the performance of the developed AFM.

Fast predictive control algorithm based on an FPAA analog neural network

A fast predictive control algorithm was developed for simpler, faster MPC optimization based on an FPAA analog neural network. An FPAA analog circuit provides the quadratic programming using a continuous neural network which avoids the convergence problem of discrete neural networks in a fast, simple and flexible algorithm that uses less computational resources than previous methods. The signal constraint of the FPAA analog circuit is solved by translation and scaling. The software and hardware design of the FPAA analog neural network predictive control is presented and verified in tests that show that the algorithm is effective. 摘要 针对模型预测控制 (model predictive control, MPC) 优化求解中占用资源较多、实时性较低且实现相对复杂的问题, 该文提出了一种基于现场可编程模拟阵列 (field programmable analog array, FPAA) 模拟神经网络的快速模型预测控制算法。通过FPAA模拟电路来实现基于连续神经网络的二次规划求解, 有效规避了离散神经网络的收敛性问题, 具有求解速度快、占用资源小、简单易实现的特点; 通过平移变换和尺度变换方法, 解决FPAA模拟电路的信号限制。最后该文给出了FPAA模拟神经网络预测控制软硬件设计方案并通过实验验证了该算法的有效性。

Design and Implementation of Autonomous and Non-Autonomous Time-Delay Chaotic System Based on Field Programmable Analog Array.

Time-delay chaotic systems can have hyperchaotic attractors with large numbers of positive Lyapunov exponents, and can generate highly stochastic and unpredictable time series with simple structures, which is very suitable as a secured chaotic source in chaotic secure communications. But time-delay chaotic systems are generally designed and implemented by using analog circuit design techniques. Analog implementations require a variety of electronic components and can be difficult and time consuming. At this stage, we can now solve this question by using FPAA (Field-Programmable Analog Array). FPAA is a programmable device for implementing multiple analog functions via dynamic reconfiguration. In this paper, we will introduce two FPAA-based design examples: An autonomous Ikeda system and a non-autonomous Duffing system, to show how a FPAA device is used to design programmable analog time-delay chaotic systems and analyze Shannon entropy and Lyapunov exponents of time series output by circuit and simulation systems.

The JET upgraded toroidal Alfvén Eigenmode Diagnostic System

The Alfvén Eigenmode Active Diagnostic system (AEAD) has undergone a major upgrade and redesign to provide a state-of-the-art excitation and real-time detection system for JET.The new system consists of individual 4 kW amplifiers allowing for increased current, separate excitation and real time control of relative phasing between antenna currents. The amplifiers have a frequency range of 10–1000 kHz, divided into various frequency bands by external matching filters. Due to the varying transmission line impedance throughout the frequency range, the amplifiers were designed with a very high resilience to reflected power.The existing amplifier control electronics have been replaced with a digital control system incorporating a National Instruments platform and Field Programmable Gate Array (FPGA) modules for frequency, gain and phase control with a frequency and phase resolution of less than 1 kHz and 1 degree respectively. Complementing the digital control system is the Protection and Control System, which utilizes Field Programmable Analog Arrays (FPAAs) and an array of electronic devices to monitor and control the AEAD.New capabilities such as independent antenna current/phase control, allow for improved excitation control, better definition of antenna spectrum combined with enhanced system reliability. This paper will review the new AEAD system, its unique capabilities and improvements over the previous diagnostic system.

FPAA Implementation of Chaotic Modulation Based on Nahrain Map

Due to characteristic of chaotic systems in terms of nonlinearity, sensitivity to initial values, and non-periodicity, they are used in many applications like security and multiuser transmission. Nahrain chaotic map is an example of such systems that are recently proposed with excellent features for the use in multimedia security applications. Although the implementation of chaotic systems is easy using low costanalogue ICs, this approach does not provide the flexibility that the reconfigurable analogue devices have in design possibilities such as reducing the complexity of design, real-time modification, software control and adjustment within the system. This paper presents a description of data modulation and demodulation based on Nahrain chaotic system and there hardware implementation using field programmable analogue array (FPAA) device. AN231E04 dpASP board is used as a target device for the implementation. The simulation results of system closely matched the programmable hardware testing results.

Enabling Energy-Efficient Physical Computing through Analog Abstraction and IP Reuse

This paper shows the first step in analog (and mixed signal) abstraction utilized in large-scale Field Programmable Analog Arrays (FPAA), encoded in the open-source SciLab/Xcos based toolset. Having any opportunity of a wide-scale utilization of ultra-low power technology both requires programmability/reconfigurability as well as abstractable tools. Abstraction is essential both make systems rapidly, as well as reduce the barrier for a number of users to use ultra-low power physical computing techniques. Analog devices, circuits, and systems are abstractable and retain their energy efficient opportunities compared with custom digital hardware. We will present the analog (and mixed signal) abstraction developed for the open-source toolkit used for the SoC FPAAs. Abstraction of Blocks in the FPAA block library makes the SoC FPAA ecosystem accessible to system-level designers while still enabling circuit designers the freedom to build at a low level. Multiple working test cases of various levels of complexity illustrate the analog abstraction capability. The FPAA block library provides a starting point for discussing the fundamental block concepts of analog computational approaches.

Low-Voltage Low-Power Integrable CMOS Circuit Implementation of Integer- and Fractional-Order FitzHugh-Nagumo Neuron Model.

The low-voltage low-power sinh-domain (SD) implementations of integer- and fractional-order FitzHugh-Nagumo (FHN) neuron model have been introduced in this paper. Besides, the effect of fractional-orders on the external excitation current and dynamics of the neuron has been examined in this paper. The proposed SD designs of FHN neuron model have the benefits of: 1) low-voltage operation; 2) integrability, due to resistor-less design and the employment of only grounded components; 3) electronic tunability of performance parameters; and 4) low-power implementation due to the inherent properties of SD technique. HSPICE simulator tool and Taiwan Semiconductor Manufacturing Company, Hsinchu, Taiwan 130-nm CMOS process was used to evaluate and verify the correct functioning of the model. In addition, to experimentally verify the operation of the proposed fractional-order FHN neuron model, field-programmable analog array (FPAA) implementation of the model has been presented, and the proper functioning of the model has been verified. To the best of the authors' knowledge, this is the first paper that describes the electronic realization of the fractional-order FHN neuron model. In addition, it is the first time that the FPAA implementation of any fractional-order neuron model has been presented.

A new current-mode computational analog block free from the body-effect

In this paper, a new computational/configurable analog block (CAB) is presented based on MOS translinear (MTL) for current-mode nonlinear computation. The proposed CAB architecture consists of three main structures: a new MTL cell, NMOS-PMOS arrays, and two local switch networks. As the new trait, it benefits from an effective compensation technique that extensively minimizes the error generated by body effect–the most important factor amongst the second-order effects. The second feature is that the MTL cell only with six transistors has enabled the CAB to implement more arithmetic functions. This block is capable of implementing such various nonlinear functions as squaring, inverse function, N-dimensional vector summation, full-wave rectifier, four-quadrant multiplier/divider, two-quadrant square-root, and exponential functions. The proposed CAB is simulated with CADENCE and HSPICE software in 0.18 μm TSMC CMOS technology at 1.8 V supply voltage. Most importantly, Post-layout plus Monte Carlo, corner case, and temperature variation simulations are performed to investigate its robust performance in the presence of PVT fabrication non-idealities. Functionality and flexibility of the proposed CAB make it suitable for the core block of Field-Programmable Analog Array (FPAA) ICs and signal processing applications.

Field-programmable photonic arrays

We propose a new programmable integrated photonic device, the Field Programmable Photonic Array, which follows a similar rationale as that of Field Programmable Gate Arrays and Field Programmable Analog Arrays in electronics. This high-level concept, basic photonic building blocks, design principles, and technology and physical implementation are discussed. Experimental evidence of its feasibility is also provided.

Hodgkin–Huxley Neuron and FPAA Dynamics

We present the experimental silicon results on the dynamics of a Hodgkin-Huxley neuron implemented on a reconfigurable platform. The circuit has been inspired by the similarity between biology and silicon, by modeling ion channels and their time constants. Another significant motivation behind this paper is to make the system available to circuit designers as well as users in the neuroscience community. The open-source tool infrastructure and a remote system ease the accessibility of our system to a number of users. We demonstrate the reproducibility of the results by replicating the dynamics across different boards along with responses from different inputs and with different parameters. The reconfigurability enables one to make use of a single primary design to obtain a variety of results. The measurements are taken from the system compiled on a field programmable analog array fabricated on a 350-nm process.

Hybrid Analog/Digital Control of Bilateral Teleoperation Systems

Hybrid analog/digital control of bilateral teleoperation systems can lead to superior performance (transparency) while maintaining stability compared to pure analog or digital control methods. Such hybrid control is preferable over pure analog control, which is inflexible and not ideal for realizing complex teleoperation control algorithms, and pure digital control, which restricts teleoperation performance due to a well-known stability-imposed upper bound on the product of the digital controller's proportional gain and the sampling period. In this paper, a hybrid controller combining a Field programmable analog array (FPAA) based analog controller and a personal computer-based digital controller is compared in terms of performance and stability to its analog and digital counterparts. A stability analysis indicates that the addition of analog derivative term widens the range of teleoperation controls gains that satisfy the stability conditions, paving the way for improving the teleoperation performance. We also show how the hybrid controller leads to better teleoperation performance. To this end, we study the human's performance of a switch flipping task and a stiffness discrimination task in the teleoperation mode. In both tasks, the hybrid analog/digital controller allows the human operators to achieve the highest task success rates.

Analog Programmable Circuit Implementation for Memristor

In this work, a new flux controlled memristor circuit is presented. It provides a tool to emulate the pinched hysteresis loop.When driven the memristor by a bipolar periodic signal, the memristor exhibits a “pinched hysteresis loop” in the voltage-current plane and starting from some critical frequency, the hysteresis lobe area decreases monotonically as the excitation frequency increases, the pinched hysteresis loop shrinks to a single-valued function when the frequency tends to infinity. The design model numerically simulated and the physical implementation is achieved by using a field programmable analog array (FPAA). The circuit can be modeled and implemented with a changeable nonlinear function blocks and fixed main system blocks. The simplicity of the specific design method makes this proposed model be a very engaging option for the design of the memristor.

MEMS Seismic Sensor with FPAA Based Interface Circuit for Frequency-Drift Compensation using ANN

<p>Electrochemical MEMS seismic sensor is limited by its non-ideality of frequency dependent characteristics hence interface circuits for compensation is necessary. The conventional compensation circuits are limited by high power consumption, bulky external hardware circuitry. In these methods digital circuits are also limited by inherent analog to digital conversion and vice versa which consumes significant power, acquires more size and limits speed. A Field programmable analog array (FPAA) overcomes these limitations and gives fast, simple and user friendly development platform with less development speed comparable to ASIC. Recently FPAA becoming popular for rapid prototyping. The proposed system presents FPAA (Anadigm AN231E04) based hardware implementation of ANN model. Using this FPAA based compensation circuit, the error in frequency drift have been minimized in the range of 3.68% to about 0.64% as compared to ANN simulated results in the range of 23.07% to 0.99 %. This single neuron consumes of power of 206.62 mW. and has minimum block wise resource utilization. The proposed hardware uses all analog blocks which remove the requirement of ADC and DAC reducing significant power and size of interface circuit. This work gives the SMART MEMS seismic sensor with reliable output and ANN based intelligent interface circuit implemented in FPAA hardware.<strong></strong></p>

Temperature Sensitivity and Compensation on a Reconfigurable Platform

This brief investigates temperature compensation techniques for circuits and systems on a reconfigurable platform. The work demonstrates use of large-scale reconfigurable system-on-chip for reducing the variability of circuits and systems compiled on a floating gate (FG)-based field-programmable analog array (FPAA). The work presents current and voltage reference which could help in reducing the variability caused due to changes in temperature. These references are standard blocks in the Scilab/Xcos environment, which could be easily compiled on the FPAA. An FG-based current reference is then used for biasing a second-order $G_{m}-C$ bandpass filter to demonstrate the compilation and usage of these voltage/current reference in a reconfigurable fabric. The large-scale FG FPAA presented here is fabricated in 350-nm CMOS process.

VMM + WTA Embedded Classifiers Learning Algorithm Implementable on SoC FPAA Devices

This paper presents a learning algorithm for a vector-matrix multiplier (VMM) + k-winner-take-all (WTA) classifier one-layer architecture on a large-scale field programmable analog array (FPAA). The technique enables opportunities for embedded, ultra-low power machine learning, techniques typically considered for large servers. To develop this training algorithm, this paper starts by understanding fundamental equivalent transformations for the VMM + WTA classifier networks. A VMM+ WTA structure can exactly compute a self-organizing map (SOM) or vector quantization (VQ) operation, in addition to other transformations. SOM, VQ, and Gaussian mixture models learning concepts are utilized for the training algorithm of this single one-layer network. An on-chip clustering step determines the initial weight set for ideal target and background values. Null symbols are important for the algorithm and are set from midpoints of the target values. The results are shown both as numerical simulation of the VMM+WTA learning network, illustrating some numerical differential equation simulation limitations for this problem, as well as experimental measurements implemented on an system on chip FPAA device.

SoC FPAA Hardware Implementation of a VMM+WTA Embedded Learning Classifier

This paper focuses on the circuit aspects required for an on-chip, on-line system on chip large-scale field-programmable analog array learning for vector-matrix multiplier (VMM) + winner-take-all (WTA) classifier structure. We start by describing the VMM+WTA classifier structure, and then show techniques required to handle device mismatch. The approach is initially explained using a VMM+WTA as a two-input XOR classifier structure. The approach requires considering the entire mixed-mode system, including the analog classifier data path, control circuitry for weight updates, and digital algorithm for computing digital weight updates and resulting floating-gate programming during the algorithm.