Field Plate Design Research Articles

4.4 kV β-Ga2O3 MESFETs with power figure of merit exceeding 100 MW cm−2

β-Ga2O3 metal–semiconductor field-effect transistors are realized with superior reverse breakdown voltages (V BR) and ON currents (I DMAX). A sandwiched SiN x dielectric field plate design is utilized that prevents etching-related damage in the active region and a deep mesa-etching was used to reduce reverse leakage. The device with L GD = 34.5 μm exhibits an I DMAX of 56 mA mm−1, a high I ON/I OFF ratio >108 and a very low reverse leakage until catastrophic breakdown at ∼4.4 kV. A power figure of merit (PFOM) of 132 MW cm−2 was calculated for a V BR of ∼4.4 kV. The reported results are the first >4 kV class Ga2O3 transistors to surpass the theoretical unipolar FOM of silicon.

Improved X-Band Performance and Reliability of a GaN HEMT With Sunken Source Connected Field Plate Design

The world class performance and reliability of a high-power density AlGaN/GaN high electron mobility transistor (HEMT) with an innovative sunken source connected field plate (SCFP) is reported. The optimized HEMT structure implements a novel sunken SCFP design that has significant advantages over the conventional field plated GaN HEMT. The new design reduced parasitic capacitances (C_gs and C_gd) whilst suppressing the peak electric fields in the drift region to improve breakdown voltage and reliability. This sunken SCFP demonstrates the improved RF performance and reliability with respect to leading GaN HEMT devices for x-band applications. The fabricated device produces 10 GHz performance with saturated output power >10 W/mm, linear gain >18 dB and PAE > 60% @ 50 V. The improved gain is a direct result of the reduction in Cgs and Cgd, by 15% and 60%, respectively. The increased power is achieved from lower trapping and increased drain voltage rating of 25%. Accelerated RF-driven reliability testing is shown to determine the expected lifetime of the device was >6E7 hours at 225°C junction temperature. This is a more than 2 orders of magnitude increase over the conventional field plate design.

Implications of Various Charge Sources in AlGaN/GaN Epi-Stack on the Drain & Gate Connected Field Plate Design in HEMTs

We have established that a design strategy for drain and gate connected field plates should be adopted while keeping in mind the interplay of various charge sources across AlGaN/GaN epi-stack, which governs the electric field distribution across HEMT. The investigations in this work are carried out for Schottky, MIS and p-GaN gate stacks while accounting for possible GaN buffer types (Fe-doped and C-doped). The role of gate and drain field plates was found to be different in the Fe-doped buffer compared to the C-doped buffer. More than suppression of avalanche generation, mitigation of gate injection by shifting the peak electric field position away from the gate edge was found to be the dominant cause of breakdown voltage improvement when field plates were adopted. In a few cases, however, the widening of the depletion region near the gate or dominance of the buffer field was the reason for breakdown voltage improvement with a gate field plate. On the other hand, the drain field plate was found to be effective only for lower polarization % and lower surface trap concentration. The role of buffer trap parameters, surface/passivation trap concentration, interface trap concentration at the gate, and passivation thickness in defining the optimum field plate strategy are discussed.

Multi-channel nanowire devices for efficient power conversion

Nanowire-based devices can potentially be of use in a variety of electronic applications, from ultrascaled digital circuits to 5G communication networks. However, the devices are typically restricted to low-power applications due to the relatively low electrical conductivity and limited voltage capability of the nanowires. Here, we show that wide-band-gap AlGaN/GaN nanowires containing multiple two-dimensional electron gas channels can be used to create high-electron-mobility tri-gate transistors for power-conversion applications. The multiple channels lead to improved conductivity in the nanowires, and a three-dimensional field-plate design is used to manage the high electric field. Power devices made with 15-nm-wide nanowires are shown to exhibit low specific on resistances of 0.46 mΩ cm−2, enhancement-mode operation, improved dynamic behaviour and breakdown voltages as high as 1,300 V.

3.4-kV AlGaN/GaN Schottky Barrier Diode on Silicon Substrate With Engineered Anode Structure

In this letter, we demonstrate high-performance lateral AlGaN/GaN Schottky barrier diodes (SBD) on Si substrate with a recessed-anode structure. The optimized rapid etch process provides results in improving etching quality with a ~ 0.3 nm roughness of the 5 × 5 μm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> anode recessed surface. Supported by the flat anode recess surface and optimized anode field plate design. When the anode-to-cathode spacing is 30 μm, the physical breakdown voltage (VBK) can reach 3.4 kV, with a specific on-resistance (R <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">on,sp</sub> ) of 3.7 mΩ·cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> , the power figure of merit (V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">BK</sub> <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> /R <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">on,sp</sub> ) can be as high as 3.1 GW/cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> , demonstrating its great potential for the application in power electronics.

2.7-kV AlGaN/GaN Schottky barrier diode on silicon substrate with recessed-anode structure

In this paper, we demonstrate high-performance lateral AlGaN/GaN Schottky barrier diodes (SBD) on Si substrate with a recessed-anode structure. The optimized rapid etch process provides results in improving etching quality with a 0.26-nm roughness of the anode recessed surface. By using the high work function metal Pt as the Schottky electrode, a low turn-on voltage of 0.71 V is obtained with a high uniformity of ±0.023 V for 40 devices. Supported by the flat anode recess surface and related field plate design, the SBD device with the anode–cathode spacing of 15 μm show the specific on-resistance (Ron,sp) of 1.53 mΩ·cm2 only, the physical breakdown voltage can reach 1678 V with a high power figure-of-merit (P-FOM) of 1840 MW/cm2. For the SBD device with the anode–cathode spacing of 30 μm, the physical breakdown voltage can be as high as 2705 V and the power FOM is 2217 MW/cm2.

Thermionic emission or tunneling? The universal transition electric field for ideal Schottky reverse leakage current: A case study in β -Ga2O3

The reverse leakage current through a Schottky barrier transitions from a thermionic emission-dominated regime to a barrier tunneling-dominated regime as the surface electric field increases. In this study, we evaluate such a transition electric field (ET) in β-Ga2O3 using a numerical reverse leakage model. ET is found to depend on temperature but has an extremely weak dependence on the doping concentration and the barrier height; as a result, a simple empirical expression can be derived to capture this near-universal dependence of ET on temperature. With the help of a field-plate design, we observed experimentally in lightly doped Ga2O3 Schottky barrier diodes near-ideal bulk reverse leakage characteristics, which match well with our numerical model and that confirm the presence of the transition region. Near the transition electric field, both thermionic emission and barrier tunneling should be considered. This study provides important guidance toward accurate design and modeling of Schottky barrier diodes, which can be readily extended to other semiconductors.

High-Performance Normally-OFF AlGaN/GaN Fin-MISHEMT on Silicon With Low Work Function Metal-Source Contact Ledge

We demonstrate a high-performance normally-OFF AlGaN/GaN fin metal–insulator–semiconductor high electron mobility transistor (fin-MISHEMT) on silicon with a low work function metal-source contact ledge (LWFM-SCL). In order to realize the normally-OFF operation, an optimized gate-recessed fin structure is used. The fin structure inherently containing a gate-connected field plate (FP) design improves the breakdown voltage ( ${V}_{\text {BD}}$ ). Moreover, the LWFM-SCL can improve the device overall ON-resistance ( ${R}_{ \mathrm{ON}}$ ) by lowering the gate–source access resistance ( ${R}_{\text {a}}$ ). The proposed device with a gate–drain length ( ${L}_{\text {GD}}$ ) of 7 $\mu \text{m}$ exhibits superior characteristics such as a threshold voltage ( $V_{\text {TH}}$ ) of +1.2 V, maximum drain current ( ${I}_{\text {D, max}}$ ) of 825 mA/mm, ON-state/OFF-state current ( ${I}_{ \mathrm{ON}}/{I}_{ \mathrm{OFF}}$ ) ratio of 109–1010, subthreshold swing (SS) of 76 mV/decade, ${V}_{\text {BD}}$ of 810 V, and specific ${R}_{ \mathrm{ON}}$ ( ${R}_{\text {on, sp}}$ ) of 0.63 $\text{m}\Omega \cdot $ cm2. It also possesses excellent ${V}_{\text {TH}}$ hysteresis, temperature stability, and dynamic ${R}_{ \mathrm{ON}}$ characteristics. These results suggest that the proposed device is very suitable for high power switching applications.

Design Guidelines and Performance Tradeoffs in Recessed AlGaN/GaN Schottky Barrier Diodes

Critical design parameters for AlGaN/GaN Schottky barrier diodes (SBDs) are analyzed in this work using TCAD computations and detailed experiments. A comprehensive TCAD-based computational modeling approach is developed for GaN-based SBD. Breakdown mechanisms in SBD for unintentionally doped (UID) buffer, Fe-doped buffer and C-doped buffer are studied. For the first time, we have reported impact of anode recess, on breakdown and leakage behavior of SBD, in correlation with interface defects. Using these insights an optimum recess design strategy has been presented and is validated experimentally. Furthermore, for the first time, we have revealed critical repercussions of the field plate termination on SBD's breakdown, leakage as well as transient behavior. Forward and reverse recovery measurements were carried out to study the diode's transient performance as a function of field plate design. Various performance matrices such as diode current collapse, reverse current overshoot and reverse recovery time were studied experimentally as a function of field plate design. Moreover, the field plate-dependent electro-thermal behavior of SBD was studied using TCAD computations and experiments. Using the systematic device design approach we have experimentally demonstrated large periphery SBD with 15 A forward current at 5.5 V.

Lowering the Pressure Drop and Cost of a Proton Exchange Membrane Fuel Cell by Flow Field Plate Design

The flow field plate is a crucial factor affecting the pressure drop and cost of a proton exchange membrane fuel cell (PEMFC). In order to lower the pressure drop and cost of the PEMFC, a novel des...

Optimal design of cathode flow channel for air-cooled PEMFC with open cathode

Air-cooled open-cathode low temperature proton exchange membrane fuel cell (AO-LTPEMFC) with low weight, small volume and compact system has become the new potential power source in the unmanned aerial vehicle (UAV). However, the desirable parameters of the cathode channel are a very important factor to influence the cell performance and the compact of the stack, which have the higher requirements put forward to the structural designs of the cathode channel of AO-LTPEMFC. Thus, some single AO-LTPEMFC fabricated with different width:0.9–1.5 mm, depth:1.1–1.5 mm, ratio (width/landing):1:0.7–1:1.3 and bending:0–10° of the cathode channel was investigated to optimize the cell performance and temperature distribution in the 2 mm plate and determine desirable design parameters. The results show that the different design parameters of the cathode channel affect the contact resistance, oxygen mass transfer of cathode and pressure drop in air flow. For AO-LTPEMFC, to keep the best performance, the cathode channel design parameters should be operated at appropriate width, as deep as possible, small ratio and bending. Through the comparison of various designs, combined with practice process, the optimum design size with width (1.1 mm) × depth (1.3 mm) × width/landing (1:0.7) × bending angel (θ) (5°) was obtained based on the 2 mm thickness of the bipolar plate, which could get the maximum performance and improve the compactness of system. Moreover, analysis in this study will provide a new guideline for the development of cathode flow field plate design in application.

Novel Drain-Connected Field Plate GaN HEMT Designs for Improved V BD–R ON Tradeoff and RF PA Performance

TCAD studies are performed to develop physical insights into the breakdown behavior of drain-connected field plate-based GaN HEMTs. Using the developed insights, to mitigate the performance bottleneck caused by the lateral drain-connected field plate design, we have proposed novel vertical-field-plate designs. The proposed designs alleviate the channel electric field by uniformly distributing it vertically into the GaN buffer region. As a result, the proposed vertical and dual-field-plate design offer ${2} \times $ and ${3} \times $ improvements in breakdown voltage, respectively, compared with the design without field plate. Similarly, compared with a design with a lateral field plate, a 50% improvement in the breakdown voltage was seen with dual-field-plate architecture. RF power amplifier (PA) performance extracted using load-pull simulations demonstrates an improved RF PA linearity at higher drain bias, improved output power, efficiency, and PA gain for HEMTs with dual- and vertical-field-plate designs.

A Low Impact Ionization Rate Poly-Si TFT with a Current and Electric Field Split Design

In this study, a novel low impact ionization rate (low-IIR) poly-Si thin film transistor featuring a current and electric field split (CES) structure with bottom field plate (BFP) and partial thicker channel raised source/drain (RSD) designs is proposed and demonstrated. The bottom field plate design can allure the electron and alter the electron current path to evade the high electric field area and therefore reduce the device IIR and suppress the kink effect. A two-dimensional device simulator was applied to describe and compare the current path, electric field magnitude distributions, and IIR of the proposed structure and conventional devices. In addition, the advantages of a partial thicker channel RSD design are present, and the leakage current of CES-thin-film transistor (TFT) can be reduced and the ON/OFF current ratio be improved, owing to a smaller drain electric field.

Silicon carbide bipolar junction transistor with novel emitter field plate design for high current gain and reliability

A silicon carbide bipolar junction transistor with novel emitter field plate (EFP-BJT) design is proposed in this paper. The fabricated EFP-BJT features a metal plate of the extending emitter electrode with a 50-nanometer-thick oxide layer overlapped on the extrinsic base surface. The contrast of experimental results show that a 56% increase of maximum current gain is obtained by the EFP-BJT compared with a conventional SiC BJT (C-BJT), with the EFP-BJT’s current gain of 43 measured at the collector current density (JC) of 716 A cm−2 corresponding to a specific on-state resistance (RSP_ON) of 5.4 mΩ · cm2 and open-base breakdown voltage (BVCEO) of 1.5 kV. The novel EFP-BJTs are entirely compatible with the process and design considerations of the conventional ones. The in-depth mechanism comparisons between the proposed EFP-BJT and C-BJT are studied by the simulation tool TCAD Silvaco. The surface recombination effect of EFP-BJT is greatly reduced by the modulation of the emitter field plate. Additionally, due to the surface recombination suppression of the novel structure, EFP-BJTs have effectively enhanced reliability. Compared with C-BJTs, there is no significant degradation of the collector current for the fabricated EFP-BJTs under the forward current stress test.

Reverse Breakdown in Large Area, Field-Plated, Vertical β-Ga2O3 Rectifiers

There is interest in developing large area Ga2O3 rectifiers for applications in hybrid power converters. Vertical geometry, Schottky rectifiers with area 1.2 × 1.2 mm2 fabricated on thick (8μm), undoped (n = 4.4 × 1015 cm−3) β-Ga2O3 epitaxial layers oN conducting bulk substrates exhibit both high forward current (1A in pulsed mode) and reverse breakdown voltage (VB = 760V). This breakdown voltage was ∼200V higher than rectifiers without the presence of a bilayer SiO2/ SiNx field plate. This edge termination is critical for obtaining high breakdown voltage by reducing electric field crowding around the metal contact periphery. Optimization of the field plate design is still needed, since devices are observed experimentally to breakdown at the contact periphery. When purposely driven to failure at high reverse bias, pits are observed in the high field regions at the edge of the contact. The specific on-resistance (Ron) for these large area rectifiers was 22 mΩ.cm−2, with a figure-of-merit VB2/Ron of 26 MW.cm−2. The potential of Ga2O3 for power electronics is clear when it is realized that these values are still an order of magnitude lower than theoretical values. The diode on-off ratio was in the range 2.7 × 107–2.2 × 109 when switching from +1.5V forward bias to 1–100V reverse bias.

Effect of flow field design and channel/header ratio on velocity distribution: An experimental approach

In this paper, an investigation was carried out to observe the effect of flow field design on flow distribution uniformity and its effect on a fuel cell performance. The research followed two methodologies; the first examined the effect of several flow field plate designs (Single Serpentine, parallel Z, 2Z, U, and 2U) on distribution uniformity of flow velocity. The second methodology involved studying the effect of header/channel area ratio on flow velocity distribution in “Parallel Z and U- type” flow fields in an attempt to obtain a more uniform distribution of flow velocity. Results acquired from first research methodology showed that using the serpentine flow field design resulted in a very small non-uniformity coefficient of flow velocity distribution of nearly 0.0271 which indicates uniform flow velocity distribution with highest pressure drop, while the U-type yielded the highest non-uniformity coefficient (0.246–0.249) which represents non-uniform distribution of flow velocity with lowest pressure drop. The results obtained from the second research methodology while using a fixed header area and variable channel area for both parallel Z and U-type channels; showed a decrease in non-uniformity coefficient with decreasing header/channel area ratio with increasing overall pressure drop in both types of flow channel design.

Field Plate Design for Low Leakage Current in Lateral GaN Power Schottky Diodes: Role of the Pinch-off Voltage

In this letter, we demonstrate a general model to reduce the reverse leakage current ( ${I}_{\text {R}}$ ) in high-voltage AlGaN/GaN Schottky diodes (SBDs) by engineering the pinchoff voltage ( ${V}_{\text {p}}$ ) of their field plates (FPs). The maximum voltage drop at the Schottky junction ( ${V}_{\text {SCH}}$ ) in the OFF state can be significantly decreased by reducing $\vert {V}_{p}\vert $ , which leads to a drastically diminished ${I}_{\text {R}}$ . We used a tri-gate architecture as means to control ${V}_{\text {p}}$ and, thus, ${I}_{\text {R}}$ , as it offers great flexibility to engineer ${V}_{\text {p}}$ compared with conventional schemes. $\vert {V}_{\text {p}}\vert $ of SBDs with tri-gate FPs was reduced by decreasing the width of the nanowires, which led to a very small ${I}_{\text {R}}$ , below 10 nA/mm under reverse biases up to 500 V, and an increase of over 800 V in soft breakdown voltage ( ${V}_{\text {BR}}$ ) at $1~\mu \text{A}$ /mm. These results reveal the importance of ${V}_{\text {p}}$ in reducing ${I}_{\text {R}}$ for SBDs, and unveil the potential of tri-gate structures as FPs for power devices.

Novel Asymmetric Slant Field Plate Technology for High-Speed Low-Dynamic Ron E/D-mode GaN HEMTs

In this letter, we discuss a novel asymmetric field plate structure utilizing a slanted field plate (FP) engineered to appropriately distribute the electric field on GaN high-electron mobility transistors (HEMTs) scaled for low-loss, high-speed power switch applications. A uniform electric field distribution achieved with the slant FP enables an optimum device design, where a low-dynamic ON-resistance ( $\text{R}_{\textsf {on,dyn}}$ ) and high breakdown voltage are obtained simultaneously by minimizing the gate-drain distance. The optimized FP design demonstrated a low $\text{R}_{\textsf {on,dyn}}$ of 2.3 (2.1) $\Omega $ -mm at a quiescent drain voltage of 50V in $\mathsf {E}$ -mode ( $\mathsf {D}$ -mode) HEMTs with a breakdown voltage of 138 V (146 V). The corresponding high-frequency performance of E-mode (D-mode) HEMTs of peak $\text{f}_{\textsf {T}}/\text{f}_{\textsf {max}}= 41$ /100 GHz (53/100 GHz) yielded a decent $\text{R}_{\textsf {on,dyn}} \times \text{Q}_{\textsf {g}}$ product in the range of 31.0–34.5 (28.0–33.3) $\text{m}\Omega \vphantom {^{\int }}$ -nC. This new slant FP technology combined with scaled epitaxial structure (for short $\textsf {L}_{\textsf {g}}$ ) and reduced access resistances, using n+ GaN ohmic contacts, greatly enhances performance and design flexibility of high-speed, low-loss, GaN power switch devices.

PureB multi-guard ring structures for detector applications

The breakdown voltage is an important parameter in designing X-ray detectors such as silicon drift detectors (SDDs). In SDDs the complete thickness of the wafer has to be depleted to enable the detection of different energies of X-rays. A high voltage is required to have a fully depleted region while keeping the leakage current low. Multi-guard ring structures are designed to meet both a low leakage current and a high breakdown voltage using deposited PureB layers. To obtain a low leakage current, PureB layers were used. In multi-guard ring structures, parameters such as gap width, number of the rings and overlap of the metal field plate with the oxide have been designed to obtain higher breakdown voltage. Parameters such as gap size, oxide charge, bulk doping concentration and field plate design have an influence on the potential distribution of the guard rings. The designed structure works up to the limit of the measurement systems (1100V) with very low leakage current in the range of 1.5–3nA/cm2 for the detector.

Novel Gate-All-Around High-Voltage Thin-Film Transistor With T-Shaped Metal Field Plate Design

A novel gate-all-around (GAA) high-voltage thin-film transistor (HVTFT) with the T-shaped metal field plate (MFP) design results in a high breakdown voltage ( $V_{\rm BD})_{_{_{}}}$ of 119.9 V and a low specific ON-resistance ( $R_{\rm SP})$ of 8.4 m $\Omega \cdot ~\mathrm{cm}^{2}$ . This T-shaped MFP GAA HVTFT solves the $V_{{\rm {BD}}}$ – $R_{\rm SP}$ tradeoff problems and exhibits superior gate control performance, which leads to excellent electrical characteristics such as a better ON/OFF ratio of $> 10^{10}$ and a lower subthreshold slope of 154.4 mV/decade than the conventional planar structure.