Field Oxide Thickness Research Articles

Modeling Inter-Device Leakage in 90 nm Bulk CMOS Devices

We demonstrate an analytical modeling approach that captures the effects of total ionizing dose (TID) on the <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$I_{d} -V_{gs}$</tex></formula> characteristics of field-oxide-field-effect-transistors (FOXFETs) fabricated in a low-standby power commercial bulk CMOS technology. Radiation-enabled technology computer aided design (TCAD) simulations and experimental data allow validating the model against technological parameters such as doping concentration, field-oxide thickness, and geometry. When used in conjunction with the closed-form expressions for the surface potential, the analytical models for fixed oxide charge and interface trap density enables accurate modeling of radiation-induced degradation of the FOXFET <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$I_{d} -V_{gs}$</tex></formula> characteristics allowing the incorporation of TID into surface potential based compact models.

What controls the pore spacing in porous anodic oxides?

In this paper, we use energy-based perturbation criteria to examine whether strain or electrostatic energy acts as a driving force for porosity initiation in anodic oxides. By doing so, we also succeeded to rationalise the dependence of pore spacing on anodising conditions. Our experimental approach consists of measuring in-situ the internal stress in anodic oxide films grown galvanostatically on aluminium in phosphoric acid, and to correlate these data with the measured pore spacing of the obtained porous films. Our results indicate that the possibility of a strain energy-induced surface instability is unlikely, as for this case the constitutive dependence of pore spacing on internal stress was not verified. Instead, the measured pore spacing, electric field and barrier oxide thickness obtained on our anodic alumina films indicate that electrostatic energy is the main driving force for pore initiation, as well as the factor controlling the pore spacing. Corroborative quantitative evidence for this novel electrostatic-based scaling law is provided by data compiled from the literature for a range of other anodic oxide systems, including nanoporous alumina and nanotubular titania films.

HDP-CVD STI oxide process with in situ post deposition laterally enhanced sputter etchback for the reduction of pattern-dependent film topography in deep submicron technologies

This paper introduces a postdeposition pattern-dependent topography-reduction enhancement to the high-density plasma chemical-vapor deposition (HDP-CVD)oxide profile for shallow trench isolation in deep submicron technologies. The enhancement is labeled "laterally enhanced sputter etchback" (L-SEB) and is carried out in situ in the HDP-CVD reactor after film deposition. The L-SEB is set up using O/sub 2/ and Ar at high O/sub 2/ flow. A design of experiment was run to search for optimum gas flow conditions. The optimized process is shown to yield significant lateral "pull-in" of the sizeable HDP oxide cones over large thin-oxide features and flattening of smaller cones over dense small features, without appreciable impact on field oxide (FOX) thickness or corner integrity. This contributes a significant improvement to an STI module that incorporates downstream planarization processes of reverse-tone etch (RTE) and chemical mechanical polishing (CMP). It also allows a start with a thinner film thickness and usage of a smaller lithography compensation factor for the reverse-tone mask, thus facilitating a smaller minimum feature for RTE exposure. These advantages enhance the manufacturability of the STI process module in terms of reducing the starting HDP film thickness,cutting down on etching and polishing times of RTE and CMP, respectively,and yielding better post-CMP within-die and within-wafer FOX uniformities.

Performance Characteristics of Semi-Insulator- and Dielectric-Passivated Si Strip Detectors

The harsh radiation environment in present and future high-energy physics experiments, such as the Large Hadron Collider (LHC), is a driving force for the development of high-voltage Si strip detectors. It is well known that mobile surface ions can affect the stability and long-term behaviour of Si detectors. These instabilities can be nearly eliminated and the performance of Si detectors can be improved by implementing suitably passivated metal-overhang structures. This paper presents the influence of the relative permittivity of the passivant on the breakdown performance of the Si detectors using computer simulations. The semi-insulator and the dielectric-passivated metal-overhang structures are compared under optimal conditions. Influence of the salient design parameters such as field oxide thickness, junction depth, metal-overhang width, and the surface charge on the breakdown performance of these structures are systematically analyzed, thus providing a comprehensive picture of the behaviour of metal-overhang structures and helping in the detector optimization task. The results presented in this paper clearly demonstrate the superiority of the metal-overhang structure design employing semi-insulator-passivated structures over dielectric-passivated ones in realizing a given breakdown voltage.

Design curves of breakdown voltage at field plate edge and effect of interface charge

Useful design curves of breakdown voltage are provided, which allow determination of breakdown voltage at the field plate edge in terms of field plate length, oxide thickness, and substrate doping concentration. The effect of the interface charge on the breakdown voltage is analyzed and determined also from the curves. The analytical results show a fair agreement with the two-dimensional device simulations using MEDICI as well as with the experimental results reported.

Basic mechanisms of an atomic force microscope tip-induced nano-oxidation process of GaAs

An atomic force microscope (AFM) tip-induced direct nano-oxidation process of GaAs(100) substrates has been investigated, and is viewed as a promising method for the fabrication of nanometer-scale electronic devices such as single electron tunneling transistors. The effects of the AFM drawing parameters such as tip bias voltage and writing speed as well as the ambient humidity on the oxide line height and width were explored. The rate of reaction and its dependence on electric field strength and oxide thickness were examined to understand the basic mechanisms involved in the tip-induced oxidation of GaAs. The rate of oxidation/anodization was found to decrease rapidly with oxide film growth, which was explained at the simplest level in terms of a self-limiting influence of decreasing electric field strength.

Is there LOCOS after LOCOS?

Decreasing the field oxide thickness, increasing the temperature or oxidation pressure in a LOCOS type isolation improves field oxide thinning. Under the above regimes, the bird's beak growth results from a reaction-limited mechanism during the linear part of the oxidation process. The latter property is of major importance for the future shrink of LOCOS isolation towards sub-0.1 μm CMOS designs. Market pressure, because of the strong demand for low-voltage and low-power ULSI devices, is defining the framework. Matching the trend in depth-of-focus reduction in lithography tools and limiting process complexity will have to be weighed constantly. The reduction of isolation dimension losses to zero is not as urgent as it used to be. Shallow trench isolation has not come to maturity because of the technically difficult and economically practicable trade-off to be found between planarization and device leakage. Refilling and planarization process standards have not yet been established despite the major progress made in chemical mechanical polishing. The contradiction betwen the planarization issue and the need for an abrupt step at the isolation/active-area edge in order to avoid subthreshold leakage of the MOS active sidewalls still has to be solved. After a brief historical review, we point out and reconsider the main advantages and drawbacks of LOCOS type and shallow trench isolation processes. Within that framework, the impact of isolation design rules on device integration density and isolation performance is reviewed and commented on.

Elimination of Stress‐Induced Defects in Polybuffered LOCOS Isolation Scheme for Sub‐0.25 μm Designs

Decreasing field oxide thickness or (and) increasing field oxidation temperature up to 1100°C, in a polybuffered local oxidation of silicon (PBL) isolation scheme, has a positive impact on field oxide thinning in small spacings, stress‐induced voiding in small active areas, as well as on 5 nm thin gate oxide QBD. A low field oxide thickness and a high temperature field oxidation enable the use of 0.7 μm pitch PBL for sub‐0.25 μm complementary metal oxide semiconductor designs. The transition of the bird's beak growth from a direct oxidation to a diffusion limited mechanism is consistent with the evolution of stress in the middle of active area as a function of field oxide thickness or field oxidation temperature.

LOCOS-induced stress effects on thin-film SOI devices

LOCOS-induced stress effects on thin-film SOI devices are investigated. We show that as the field oxide thickness increases, degradation (enhancement) of nMOSFET's (pMOSFET's) I-V characteristics becomes increasingly pronounced. The total degradation or enhancement of I-V characteristics can reach /spl sim/40% of drive current for devices under certain processing conditions. Estimated stress results using four-point bending measurement show that the stress level on the silicon film is of order 1200 MPa for devices with /spl sim/40% of I-V degradation/enhancement. We attribute the stress phenomenon to the volumetric expansion of field oxide during the LOCOS process.

High Temperature Local Oxidation of Silicon Field Isolation Morphological Characterization

The morphological characterization of local oxidation of silicon (LOCOS) isolation has been carried out by using steam oxidation in the temperature range 1050 to 1180°C and as‐grown field oxide thickness between 150 and 600 nm. A bird's beak minimum is observed between 100 and 1140°C, corresponding to a change in the bird's beak growth mechanism from a diffusion type to a regime dependent on silicon surface oxidation and nitride oxidation rates. For the first time on LOCOS isolation, the improvement of field oxide thinning by reducing field oxide thickness is reported: that enables a possible scaling for subquarter micrometer design rules.

Analysis and optimal design of semi-insulator passivated high-voltage field plate structures and comparison with dielectric passivated structures

The influences of the field oxide thickness and the junction depth on the breakdown voltage of semi-insulator passivated planar junctions with the field plate are investigated using a 2D simulator. This is done by analyzing the two extreme situations: the planar junction with an infinitely long field plate, and the deep-depleted MOS structure having a finite size. This rather unconventional approach has offered a new physical insight into the role of the metal field plate and has revealed that the severe field crowding associated with a shallow planar junction can be greatly suppressed by using a thin field oxide. The breakdown voltage and the optimal field oxide thickness of the semi-insulator passivated field plate structures remain nearly constant over a wide variation in the junction depth, and therefore such structures are attractive for realizing high-voltages in vertical devices fabricated by low-voltage IC technology. The influences of the field plate width and the inter-electrode spacing are studied by the conventional approach, and a simple and widely applicable design guideline is given for both the nonpunchthrough and the punchthrough type structures. The influence of the surface charge in the range 0 to 10/sup 12/ cm/sup -2/ is found to be negligible. The semi-insulator passivated and the dielectric passivated field plate structures are compared under optimal conditions. This suggests that the semi-insulator passivated structures are attractive when thin field oxide and a shallow planar junction are needed and that the dielectric passivated structures are better when compactness is desired.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Effect of Device Processing Conditions on Extended Dislocations and Defects in Ti‐Salicided Source/Drain Regions of Silicon Integrated Circuits

The propagation of incipient n+ and p+ source/drain (S/D) implant damage into extended dislocations at gate and field edges was studied for a variety of different processing conditions used to fabricate typical Ti‐salicided complimentory metal oxide semiconductor transistors. Gate edge dislocations were observed predominantly in n‐wells, while field edge defects occurred in both n and p‐wells. Both gate edge and field edge dislocations were found to be strongly affected by stresses from field oxide edges and overlying dielectric spacer layers. The use of a low‐stress polysilicon‐to‐metal dielectric is effective in reducing the density of extended dislocations in both n‐ and p‐wells. Moderation of field oxide edge stress, either by reducing the field oxide thickness or by tapering the field to active area transition region, is also effective in reducing dislocation density in the n‐well.

Process-induced mechanical stress in isolation structures studied by micro-Raman spectroscopy

Micro-Raman spectroscopy is used to study mechanical stress in local isolation structures on silicon substrates (poly-buffered local oxidation of silicon, called PBLOCOS or LOPOS). The influence of processing parameters such as nitride film thickness and width, pad oxide thickness, and field oxide thickness is studied. Also the change of the local stress during the successive processing steps of the isolation is investigated: deposition of the nitride mask, field oxidation, and removal of the nitride mask. The results are explained using a simple analytical model. It is found that stress varies very much during the different processing stages. After deposition of the nitride film, the stress is compressive under the mask lines and tensile outside the lines, close to the line border. The stress magnitude is highly dependent on the thickness of the nitride film. It can be described by edge forces. During field oxidation, this edge-force-induced stress nearly completely relaxes. In LOPOS structures with field oxide, the magnitude and distribution of the mechanical stress is mainly determined by the compressive forces exerted by the field oxide and the bird’s beak on the silicon, and tensile forces which are related to the bending of the nitride film at the edges. The influence of nitride film thickness on the stress at the center of the lines, ωc, is much smaller after field oxidation. For wide lines ωc is compressive and much higher than before field oxidation. For small widths ωc becomes tensile due to the influence of the vertical forces acting at the bird’s beak edge. The tensile stress due to the bending of the nitride film edge is much larger than the field-oxide-induced compressive stress, and dominates the stress picture at the bird’s beak. Only when very thick field oxides and thin nitride films are used, the field-oxide-induced compressive stress becomes visible. This becomes more clear when, in a further process stage, the nitride film is removed. The stress picture is then completely determined by the field oxide and the stress in the active area is always compressive.

Temperature, field and technological dependences of thin oxide breakdown characteristics

The influence of the temperature, the applied field, and the process on the breakdown parameters of very thin oxides used in representative CMOS technologies is studied. Particularly, three temperature ranges with different activation energies are demonstrated, although the correlation between the bulk oxide trapped charge and the breakdown vs temperature is shown. The two main well-known quantitative models for breakdown are applied and discussed. The great importance of the oxidation step is shown, but the influence of the substrate is also proved. A law describing the evolution of the field acceleration factor vs oxide thickness at high fields is given. Throughout this study, some limitations for the estimation of the oxide reliability are reported.

Two-dimensional analysis and design considerations of high-voltage planar junctions equipped with field plate and guard ring

The breakdown voltages of planar junctions (both nonpunchthrough and punchthrough cases) equipped with field plates and guard rings are determined by evaluating the ionization integral using the potential distribution computed by solving Poisson's equation in two-dimensions by a finite difference method. The influence of various parameters, such as substrate doping concentration, n-layer thickness, field oxide thickness, cylindrical junction curvature, field plate width, and the spacing between field plate and guard ring, on the breakdown voltage is extensively studied. It is shown that an optimum value exists for the field oxide thickness to realize maximum breakdown voltage. The study also shows that the optimum oxide thickness depends upon cylindrical junction curvature, substrate doping concentration, and n-layer thickness. It is further shown that the permittivity of a passivant dielectric layer deposited over field plate structure influences the breakdown voltage when breakdown takes place at the field plate edge. The numerical results are compared with the experimental data, and good agreement between the two is observed. Based on this two-dimensional study, design guidelines are provided for achieving breakdown voltages close to maximum realizable values, by conserving the device area and reducing the ionization at the field plant edge. The results presented clearly demonstrate the superiority of the field plate design using punchthrough structures over nonpunchthrough structures in realizing a given breakdown voltage.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Two-dimensional simulation on the electric field spike of indium antimonide charge injection devices

The surface breakdown induced by the electric-field spike existing in the gate overlay region and the device perimeter region is suspected to be one of the main factors which limit the charge storage capacity of a narrow bandgap InSb dual-gate metal-insulator-semiconductor (MIS) charge injection device (CID). In this study, a two-dimensional theoretical simulation is used to investigate the effect of device parameters, including bias voltage, oxide thickness, gate structure, gate overlay length, and field oxide thickness on the electric-field spike height in an InSb CID. In addition, it is found that a graded oxide structure can be used to lower the electric field spike.

A self-aligned nitrogen implantation process (SNIP) to minimize field oxide thinning effect in submicrometer LOCOS

A self-aligned nitrogen implantation process (SNIP) utilizing low-energy and high-dose molecular nitrogen ions has been developed to minimize the field oxide thinning effect in submicrometer local oxidation of silicon (LOCOS) isolation. Molecular nitrogen ions with a dosage of 2.5*10/sup 16/ cm/sup -2/ were implanted at 20 keV into large isolation regions to selectively form a thin nitridelike layer which can effectively retard the thermal oxidation of silicon. Self-aligned spacers were developed to shield small-isolation regions from the nitrogen implantation. The oxidation rate in small-isolation regions was therefore not affected. The final field oxide thickness became more uniform for various isolation dimensions across the wafer. The device characteristics of the n- and p-MOSFET with the SNIP were similar to those of devices with the conventional LOCOS process. An increase in the magnitude of field threshold voltages at submicrometer isolation regions was measured for both n- and p-channel parasitic field-effect transistors with the SNIP. A minimal reduction in field oxide thickness of less than 10% and an acceptable field threshold voltage magnitude of higher than 7.5 V were achieved for an isolation width as narrow as 0.5 mu m. >

The dependence of silicon selective epitaxial growth rates on masking oxide thickness

Growth rates in selective epitaxial depositions (SEG) and epitaxial lateral overgrowth (ELO) in the SiCl2H2-HCl-H2 system were studied as a function of masking oxide thickness. Enhanced growth was observed on wafers with thin (80 nm), as compared to thick (&amp;gt;300 nm), masking oxides. The higher growth rates on wafers with thin oxides were attributed to their higher surface temperature. The higher surface temperature for wafers with thin oxides is demonstrated to be due to decreased radiant heat transfer as compared to wafers with thicker oxides. The dependence of oxide thickness on growth rates was global, meaning that the bulk or large area field oxide thickness, and not the local oxide thickness in the immediate vicinity of the seed window, determined the growth rates. Hence, the dependence of growth rates on masking oxide thickness is critical in understanding, designing, and comparing experiments studying epitaxial deposition processes, but is less critical for technological applications of SEG and ELO.

Experimental study of the electrical performance of isolation structures

The electrical behaviour of the parasitic Al-gate MOS transistor on LOCOS and SILO isolation structures is investigated. The influence of the two-dimensional parasitic channel on the isolation performances is pointed out by studying the bird's-beak length, the field oxide thickness, and the use of a semi- or fully recessed structure. The measured characteristics are discussed and explained with the assistance of the two-dimensional process simulations of the isolation structures. >

A bird's beak reduction technique for LOCOS in VLSI Fabrication

The local oxidation of silicon (LOCOS) enhancement technique using a thin nitridized pad oxide formed by thermally nitridizing a thin thermal oxide in ammonia gas ambient has been developed for fabricating a defect-free near-zero bird's beak field isolation structure. By directly measuring the bird's beak length from the SEM cross-sectional view of the enhanced LOCOS structure, the process regime for reducing the bird's beak length down to 0.1 µm with a field oxide thickness of 8000 Å has been exploited.