Field-effect Transistor Structure Research Articles

A Study on Nano-Flow Control of Bio-Inspired Nanosized Ion Channel

This study presents the possibility of control of nanofluidics in the bio-inspired nanosized ion channel using a field effect transistor (FET) structure. We analyzed effects from main dominant factors to control the ion flow in nanosized channel such as electro-osmosis, diffusion effect, Coulomb force between ions and pressure force. Additionally, we suggest a strategy to control the ion flow accurately at the specific position in the nanochannel by handling the viscosity, ion molecular density, pressure, gate and trans-cis voltages of FET structure.

Asymmetric doping induced nonlinear electron mobility in double V-shaped quantum well based FET structure under external electric field

The effect of asymmetric doping profile on the electron mobility μ is studied in a Field Effect Transistor (FET) structure based on Al x Ga 1−x As double V-shaped quantum well (D-VQW) in presence of an external electric field F. We introduce asymmetry in the structure by considering different doping concentrations in the side barriers along the substrate and surface. The resultant asymmetric potential is varied as a function of F. Accordingly the energy levels E l and wave functions ξ l within the coupled structure alter. By varying F suitably the resonance of subband states can be realized between the wells. Around the point of resonance, ξ l rearranges significantly. The change in ξ l influences the screened scattering potentials through intersubband effects leading to nonlinear μ. We consider ionized impurity (Imp-) scattering and alloy disorder (Al-) scattering for the D-VQW structure and show that under double subband occupancy, μ has an oscillatory behavior, basically due to Imp-scattering. The oscillatory μ enhances by increasing the well width and central barrier width and also by decreasing the height of the V-shaped well. Our results of nonlinear electron mobility can be employed to tune the transistor performance with gate electric field by adopting an optimized set of structure parameters.

Optimal asymmetry of transistor-based terahertz detectors

Detectors of terahertz radiation based on field-effect transistors (FETs) are among the most promising candidates for low-noise passive signal rectification both in imaging systems and wireless communications. However, it was not realized so far that geometric asymmetry of common FETs with respect to source-drain interchange is a strong objective to photovoltage harvesting. Here, we break the traditional scheme and reveal the optimally asymmetric FET structure, providing the maximization of THz responsivity. We fabricate a series of graphene transistors with variable top gate positions with respect to a mid-channel and compare their subterahertz responsivities in a wide range of carrier densities. We show that responsivity is maximized for input gate electrode shifted toward the source contact. Theoretical simulations show that for large channel resistance, exceeding the gate impedance, such a recipe for responsivity maximization is universal and holds for both resistive self-mixing and photo-thermoelectric detection pathways. In the limiting case of the small channel resistance, the thermoelectric and self-mixing voltages react differently upon changing the asymmetry, which may serve to disentangle the origin of nonlinearities in novel materials.

Paving the Way for Tunable Graphene Plasmonic THz Amplifiers

This study reviews recent advances in room-temperature coherent amplification of terahertz (THz) radiation in graphene, electrically driven by a dry cell battery. Our study explores THz light–plasmon coupling, light absorption, and amplification using a current-driven graphene-based system because of its excellent room temperature electrical and optical properties. An efficient method to exploit graphene Dirac plasmons (GDPs) for light generation and amplification is introduced. This approach is based on current-driven excitation of the GDPs in a dual-grating-gate high-mobility graphene channel field-effect transistor (DGG-GFET) structure. The temporal response of the DGG-GFETs to the polarization-managed incident THz pulsation is experimentally observed by using THz time-domain spectroscopy. Their Fourier spectra of the transmitted temporal waveform through the GDPs reveals the device functions 1) resonant absorption at low drain bias voltages below the first threshold level, 2) perfect transparency between the first and the second threshold drain bias levels, and 3) resonant amplification beyond the second threshold drain bias voltage. The maximal gain of 9% is obtained by a monolayer graphene at room temperatures, which is four times higher than the quantum limit that is given when THz photons directly interact with electrons. The results pave the way toward tunable graphene plasmonic THz amplifiers.

Feedback Stabilization of a Negative-Capacitance Ferroelectric and its Application to Improve the f T of a MOSFET

We propose a parallel negative-capacitance field-effect transistor (P-NCFET) structure, in which a ferroelectric operating in its negative-capacitance region is placed in parallel with the gate and source terminals of a MOSFET. The P-NCFET is stabilized by combining careful matching of the ferroelectric with the gate capacitance along with simple feedback realized using current mirrors. The novel stabilization approach opens the possibility for a variety of new applications that exploit the negative capacitance of ferroelectrics to cancel capacitance in integrated circuits. As an example, we show the P-NCFET structure has a significantly higher unity-current-gain frequency <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${f}_{T}$ </tex-math></inline-formula> compared to a conventional MOSFET.

An Efficient GFET Structure

A graphene field effect transistor, where the active area is made of monolayer large-area graphene, is simulated including a full 2D Poisson equation and a drift-diffusion model with mobilities deduced by a direct numerical solution of the semiclassical Boltzmann equations for charge transport by a suitable discontinuous Galerkin approach. The critical issue in a graphene field effect transistor is the difficulty of fixing the off state which requires an accurate calibration of the gate voltages. In the present paper we propose and simulate a graphene field effect transistor structure which has well-behaved characteristic curves similar to those of conventional (with gap) semiconductor materials. The introduced device has a clear off region and can be the prototype of devices suited for post-silicon nanoscale electron technology. The specific geometry overcomes the problems of triggering the minority charge current and gives a viable way for the design of electron devices based on large area monolayer graphene as substitute of standard semiconductors in the active area. The good field effect transistor behavior of the current versus the gate voltage makes the simulated device very promising and a challenging case for experimentalists.

Cointegration of single-transistor neurons and synapses by nanoscale CMOS fabrication for highly scalable neuromorphic hardware.

Cointegration of multistate single-transistor neurons and synapses was demonstrated for highly scalable neuromorphic hardware, using nanoscale complementary metal-oxide semiconductor (CMOS) fabrication. The neurons and synapses were integrated on the same plane with the same process because they have the same structure of a metal-oxide semiconductor field-effect transistor with different functions such as homotype. By virtue of 100% CMOS compatibility, it was also realized to cointegrate the neurons and synapses with additional CMOS circuits. Such cointegration can enhance packing density, reduce chip cost, and simplify fabrication procedures. The multistate single-transistor neuron that can control neuronal inhibition and the firing threshold voltage was achieved for an energy-efficient and reliable neural network. Spatiotemporal neuronal functionalities are demonstrated with fabricated single-transistor neurons and synapses. Image processing for letter pattern recognition and face image recognition is performed using experimental-based neuromorphic simulation.

Systematic Characterization of Plasma-Etched Trenches on 4H-SiC Wafers.

Silicon carbide power semiconductors overcome some limitations of silicon chips, and therefore, SiC is an attractive candidate for next-generation power electronics. In addition, the number of possible vertical devices that can be obtained on a given surface using the trench technique is significantly larger than that attainable using a planar setup. Moreover, a SiC trench power metal oxide semiconductor field-effect transistor (power MOSFET) structure removes the junction field-effect transistor (JFET) region (that would decrease the current flow width) and improves the channel density, thus reducing the specific electrical resistance. Consequently, in the present study, we report on the chemical bonding state of elements and structural characterization of trenches, obtained using SF6-based plasma etching, on the 4H-SiC polytype substrate. An interferometric algorithm that finds the endpoint to stop etching governed the trench depth. Scanning electron microscopy, transmission electron microscopy, atomic force microscopy, and X-ray photoelectron spectroscopy analyses stated the high quality and uniformity of the trenches. These materials are particularly promising for the fabrication of the SiC MOSFET to be implemented in the manufacturing of power devices.

A design of improved nanoscale U-Shaped TFET by energy band modification for high performance digital and analog/RF applications

In this study, a new nanoscale U-shaped tunnel field-effect transistor (US TFET) structure is proposed. In order to start the design process, the drain region of the conventional US TFET is divided into two distinct parts with N+ and N- doping which is named the drain doping engineering (DDE). It is considered that the tunneling barrier at the channel-drain junction is increased and consequently the ambipolar current is decreased considerably. To continue the design process, the dual work function (DW) in the DDE-US TFET has been used to ameliorate the DC characteristics and the cutoff frequency. Moreover, we have used the metal implant (MI) in the source-side oxide of DDE-DW-US TFET as a technique to improve the device for high-frequency and low-power applications. The 2-D TCAD simulation results not only indicate the superiority of the proposed structure (DDE-DW-MI-US TFET) compared to others in terms of the high-frequency performance, but also illustrate the improvement of the DC parameters. Finally, the proposed device has been investigated by increasing the length of implanted metal in the source-side oxide. It is found that selecting the appropriate length contributes significantly to improve high-frequency performance.

Terahertz emission spectroscopy of GaN-based heterostructures

This study investigates the band bending profile of gallium-nitride-based heterostructures with respect to the change in the direction of the induced current in the out-of-plane plane direction, which gives the phase of the terahertz emission peak and can be detected by laser THz emission microscopy. We use a wavelength-tunable laser THz emission spectroscope to observe the transport of charges within the band bending regions, excitation of nearby photocarriers, and carrier scattering. We observe flip-flop peak-to-peak THz emission waveforms for a GaN heterostructure field-effect transistor (FET) compared to a strong THz emission radiated from an Al0.3Ga0.7N/GaN high-electron-mobility-transistor (HEMT). The flip-flop THz emission indicates the emission from various interfaces inside the FET structure, and intense THz emission from the HEMT structure indicates band-edge excitation. Our results provide a valuable perspective for characterizing complex heterostructures that provide insight into possible defects, carrier mobilities, and band bending of multilayer interface electronic devices.

P-TiO2/GO heterojunction based VOC sensors: A new approach to amplify sensitivity in FET structure at optimized gate voltage

Graphene/graphene oxide (GO) field effect transistor (FET) is widely investigated for the mainstream electronics. On the other hand, GO and TiO2 nanocomposite is extensively reported for sensing and energy applications. In the current study, we developed p-type TiO2/GO hybrid channel based back gated FET sensors for the detection of volatile organic compounds (VOCs) of very low concentrations. High sensitivity at low concentration of VOC was achieved by high surface reactivity towards VOC by p-TiO2/GO heterojunctions and limited drain current at appropriate gate voltage near Dirac point. Ambipolar transport due to field effect is only observed in GO dominated nanocomposites where 1 vol% p-TiO2 and 99 vol% GO based FET exhibits best performance having 115% response in 100 ppm ethanol at 100 °C with VDS = 0.5 V, VGS = 0.7 V. The response is enlarged ~ 34 times at VGS = 0.7 V as compared to the VGS = 0 V extending the lower detection limit of ethanol up to 500 ppb.

Ternary 2D Layered Material FePSe3 and Near‐Infrared Photodetector

AbstractThe preparation of ternary 2D layered material (2DLM) FePSe3 and field‐effect transistor (FET) type photodetector are investigated. By advancing an optimized chemical vapor transport method, bulk crystal FePSe3 is synthesized within several growth hours instead of routinely required weeks, from which 2DLM FePSe3 flakes with a thickness of ≈22.0 nm and high crystalline quality are obtained through mechanical exfoliation. Ohmic contacts for FET structure with good linear conductivity and thermal stability are implemented through the combination of electron‐beam lithography and thermal evaporation techniques. Transfer characteristics prove the p‐type conductivity of the 2DLM FePSe3 channel. The transistor devices exhibit good performance at 637 nm with a detectivity of 1.17 × 107 Jones. More importantly, a wide photocurrent spectrum from visible (450 nm) to near‐infrared (940 nm) of ternary 2DLMs is observed, which is attributed to the improvement of crystal quality of 2DLM, relatively low surface defect states, and high‐performance Ohmic electrodes. This work promotes the development of ternary 2DLM and photodetector that are still in their infancy towards continuous broad‐spectrum technology.

Fabrication of Graphoepitaxial Gate-All-Around Si Circuitry Patterned Nanowire Arrays Using Block Copolymer Assisted Hard Mask Approach.

We demonstrate the fabrication of sub-20 nm gate-all-around silicon (Si) nanowire field effect transistor structures using self-assembly. To create nanopatterned Si feature arrays, a block-copolymer-assisted hard mask approach was utilized using a topographically patterned substrate with well-defined Si3N4 features for graphoepitaxially alignment of the self-assembled patterns. Microphase-separated long-range ordered polystyrene-b-poly(ethylene oxide) (PS-b-PEO) block-copolymer-derived dot and line nanopatterns were achieved by a thermo-solvent approach within the substrate topographically defined channels of various widths and lengths. Solvent annealing parameters (temperature, annealing time, etc.) were varied to achieve the desired patterns. The BCP structures were modified by anhydrous ethanol to facilitate insertion of iron oxide features within the graphoepitaxial trenches that maintained the parent BCP arrangements. Vertical and horizontal ordered Si nanowire structures within trenches were fabricated using the iron oxide features as hard masks in an inductively coupled plasma (ICP) etch process. Cross-sectional micrographs depict wires of persistent width and flat sidewalls indicating the effectiveness of the mask. The aspect ratios could be varied by varying etch times. The sharp boundaries between the transistor components was also examined through the elemental mapping.

Review of Nanosheet Transistors Technology

Nano-sheet transistor can be defined as a stacked horizontally gate surrounding the channel on all direction. This new structure is earning extremely attention from research to cope the restriction of current Fin Field Effect Transistor (FinFET) structure. To further understand the characteristics of nano-sheet transistors, this paper presents a review of this new nano-structure of Metal Oxide Semiconductor Field Effect Transistor (MOSFET), this new device that consists of a metal gate material. Lateral nano-sheet FET is now targeting for 3nm Complementary MOS (CMOS) technology node. In this review, the structure and characteristics of Nano-Sheet FET (NSFET), FinFET and NanoWire FET (NWFET) under 5nm technology node are presented and compared. According to the comparison, the NSFET shows to be more impregnable to mismatch in ON current than NWFET. Furthermore, as comparing with other nano-dimensional transistors, the NSFET has the superior control of gate all-around structures, also the NWFET realize lower mismatch in sub threshold slope (SS) and drain induced barrier lowering (DIBL).

Printable graphene BioFETs for DNA quantification in Lab-on-PCB microsystems

Lab-on-Chip is a technology that aims to transform the Point-of-Care (PoC) diagnostics field; nonetheless a commercial production compatible technology is yet to be established. Lab-on-Printed Circuit Board (Lab-on-PCB) is currently considered as a promising candidate technology for cost-aware but simultaneously high specification applications, requiring multi-component microsystem implementations, due to its inherent compatibility with electronics and the long-standing industrial manufacturing basis. In this work, we demonstrate the first electrolyte gated field-effect transistor (FET) DNA biosensor implemented on commercially fabricated PCB in a planar layout. Graphene ink was drop-casted to form the transistor channel and PNA probes were immobilized on the graphene channel, enabling label-free DNA detection. It is shown that the sensor can selectively detect the complementary DNA sequence, following a fully inkjet-printing compatible manufacturing process. The results demonstrate the potential for the effortless integration of FET sensors into Lab-on-PCB diagnostic platforms, paving the way for even higher sensitivity quantification than the current Lab-on-PCB state-of-the-art of passive electrode electrochemical sensing. The substitution of such biosensors with our presented FET structures, promises further reduction of the time-to-result in microsystems combining sequential DNA amplification and detection modules to few minutes, since much fewer amplification cycles are required even for low-abundance nucleic acid targets.

Intrinsic switching in Si-doped HfO2: A study of Curie–Weiss law and its implications for negative capacitance field-effect transistor

HfO2-based ferroelectrics are considered a promising class of materials for logic and memory applications due to their CMOS compatibility and ferroelectric figures of merit. A steep-slope field-effect-transistor (FET) switch is a device for logic applications in which a ferroelectric gate stack exploits a stabilized negative capacitance regime capable to differentially amplify the surface potential in a metal–oxide–semiconductor FET structure, resulting in the improvement of the subthreshold swing and overdrive. In a number of relevant studies of negative capacitance, intrinsic (thermodynamic) switching is assumed, since alternative switching scenarios predict undesirable hysteretic responses in logic devices. However, there is little support from the experimental data showing that the polarization reversal in HfO2-based ferroelectrics is really driven by the intrinsic switching mechanism. In this work, polarization hysteresis loops are measured over wide temperature ranges on polycrystalline Si-doped HfO2 (Si:HfO2) capacitors. The analysis herein, which is based on the classic Landau–Ginzburg–Devonshire theory, yields the temperature-dependent dielectric susceptibility values, which fit the Curie–Weiss law. The extrapolated Curie temperature value is in line with the data obtained for other HfO2-based ferroelectrics using different techniques. The work also illustrates a method to evaluate the ferroelectric equivalent negative capacitance value and range of voltages, aiming at study and optimization of a stabilized negative capacitance FET. This study indicates that the intrinsic switching provides an adequate description of the polarization hysteresis in Si:HfO2 films. This confirms the usability of hafnia-based ferroelectrics for negative capacitance logic devices, and the important role that the intrinsic mechanism plays in the dielectric response of these materials.

Investigation of 6-armchair graphene nanoribbon tunnel FETs

A simulation-based study of an n-type six-dimer-line armchair graphene nanoribbon (6-AGNR) tunnel field-effect transistor with asymmetric reservoir doping density is carried out. Tunnel field-effect transistor (TFET) structures are proposed based on a detailed investigation of the device behavior for different applied voltages, channel lengths, temperatures, insulator thicknesses, dielectric constants, and source impurity molar fractions. By suppressing the tunneling transmission in the off-state, the channel length of the device using HfO2 can be scaled down to 5 nm without increasing the leakage current. When using a supply voltage of 0.4 V, the ION/IOFF ratio reaches a high value of 3.6 × 1010 for the device with a 5-nm channel. Besides, a subthreshold swing (SS) of 3.8 mV/dec is measured for the same GNR-TFET. The high-performance 10-nm-channel device, when supplied with 0.6 V, exhibits a boosted ION value of up to 4.3 × 103 µA/µm, with SS, gm, and Dini values of 28 mV/dec, 11 µS, and 11 fs, respectively. Nevertheless, conventional GNR-TFETs with various channel lengths exhibit rather outstanding characteristics. Such 6-AGNR TFETs display promising functionality for application in future digital and analog integrated circuits.

Investigation of a novel 5nm top bottom gated junctionless FinFET for improved switching and analog performance

In this work, we have designed a Novel Top-Bottom Gated Junctionless (JL) Fin-Shaped Field Effect Transistor (FinFET) Structure. The main idea of designing this structure is to improve the output efficiency and reduce the Short Channel Effects (SCEs). This paper analyzes the Analog Performance of a Novel Junctionless FinFET Structure with 5nm Gate length investigated on Silvaco Atlas Technology Computer Aided Design (TCAD) Tools and compared to Conventional Junctionless Bulk FinFET Structure. This Novel JL FinFET has gates on both sides of the substrate, hence the name Top-Bottom Gated (TBG) FinFET. It is determined that the proposed novel device enhances the switching ratio by almost 100 times, hence improving the transconductance and output current. Our device also shows improvement in the output conductance over the conventional JL FinFET. The simulation results show that the Novel TBG JL FinFET structure has better ION/IOFF and thus reduces the short channel effects than the conventional bulk FinFET more effectively.

Demystifying the role of channel region in two-dimensional transistors

Back-gated field-effect transistor (BGFET) structures are the most prominently used device platform to study the electrical properties of two-dimensional materials. These devices are widely modeled as Schottky barrier (SB)-MOSFETs assuming that the current flow is limited by the source-contact in the OFF state, while the channel limits the current in the ON state. Here, using an analytical model and drift-diffusion simulations, we show that the channel limits the overall current in the OFF state and vice versa, in contrast to past studies. Furthermore, we demonstrate how this renewed understanding helps to clarify the general underestimation of extracted SB height in experimental long-channel BGFETs.

A Review of Graphene Nanoribbon Field-Effect Transistor Structures

The ascending trend of Moore’s law has stretched to the horizon, where the prospects of carbon-based materials show the potential of replacing the silicon-based complementary metal-oxide semiconductor technology. These alternatives include nanowire transistors, carbon nanotube field-effect transistors, quantum-dot cellular automata, and graphene nanoribbon field-effect transistors (GNRFETs). This paper presents a review of the evolution of graphene, its fabrication process, and graphene-based field-effect transistor device structures. The diverse features of graphene as a material are derived from its structural, electronic, and thermal properties. A brief review of the techniques utilized for the fabrication of GNRFETs is mentioned in this paper. GNRFETs are based on excellent electrical properties that include strong ballistic transport, high current ratio, better compatibility with high K dielectrics, high electron mobility, reliability, scalability, and transconductance. GNRFET structures are reviewed for several aspects which include the Ion/Ioff ratio, subthreshold swing, oxide thickness, high K dielectrics, etc. that help to monitor the improvement in the performance of GNRFET devices. A comparison of the structures is presented to help researchers have a fair idea of the impact of modifications on device performance. The compact model used to simulate GNRFET-based devices is also included in this paper. GNRFET-based devices have several applications to offer in the current scenario. This paper also reports several applications of present GNRFET-based devices.