Fabrication of Graphoepitaxial Gate-All-Around Si Circuitry Patterned Nanowire Arrays Using Block Copolymer Assisted Hard Mask Approach.

Tandra Ghoshal,Ross Lundy,Ramsankar Senthamaraikannan,Michael A Morris,Matthew T Shaw,Andrew Selkirk

doi:10.1021/acsnano.0c09232

Abstract

We demonstrate the fabrication of sub-20 nm gate-all-around silicon (Si) nanowire field effect transistor structures using self-assembly. To create nanopatterned Si feature arrays, a block-copolymer-assisted hard mask approach was utilized using a topographically patterned substrate with well-defined Si3N4 features for graphoepitaxially alignment of the self-assembled patterns. Microphase-separated long-range ordered polystyrene-b-poly(ethylene oxide) (PS-b-PEO) block-copolymer-derived dot and line nanopatterns were achieved by a thermo-solvent approach within the substrate topographically defined channels of various widths and lengths. Solvent annealing parameters (temperature, annealing time, etc.) were varied to achieve the desired patterns. The BCP structures were modified by anhydrous ethanol to facilitate insertion of iron oxide features within the graphoepitaxial trenches that maintained the parent BCP arrangements. Vertical and horizontal ordered Si nanowire structures within trenches were fabricated using the iron oxide features as hard masks in an inductively coupled plasma (ICP) etch process. Cross-sectional micrographs depict wires of persistent width and flat sidewalls indicating the effectiveness of the mask. The aspect ratios could be varied by varying etch times. The sharp boundaries between the transistor components was also examined through the elemental mapping.

Highlights

We demonstrate the fabrication of sub-20 nm gate-all-around silicon (Si) nanowire field effect transistor structures using self-assembly
We have explore the methodology further to achieve long-range, well-ordered vertical and horizontal Si nanowires through graphoepitaxy of SiO2/Si trenches with Si3N4 sidewall toward gate-all-around application
Horizontal (Scheme 2FI) and vertical (Scheme 2FII) Si nanowires with iron oxide at the tip were fabricated by silica followed by Si inductively coupled plasma (ICP) etch processes

Summary

Introduction

We demonstrate the fabrication of sub-20 nm gate-all-around silicon (Si) nanowire field effect transistor structures using self-assembly. A mixture of perpendicular and parallel orientation of cylinders (dots and lines) were observed for all the trench widths for the BCP films annealed for longer times (Figure 2f−h). Ordered oxide nanodots and nanowire arrays can be generated by the metal inclusion method through spin coating the precursor−ethanolic solution followed by UV/ ozone treatment as in our previous work[40] where iron oxide nanodots were used as a resistant mask to fabricate high aspect ratio nanopatterns.

Results

Conclusion