Field-effect Carrier Mobility Research Articles

(Digital Presentation) Improving Field-Effect Transistor Performance through Pulsed Laser Irradiation-Mediated MoS2-Metal Contact Engineering

Two-dimensional (2D) layered materials, such as MoS2, with their atomically thin characteristics, offer promising novel solutions for the field of nanoelectronics. MoS2 has been identified as a prospective building block for flexible and transparent nanoelectronics in the future, and has the potential to contribute to the continuation of Moore's law by enabling high integration levels with low power consumption. Although the use of 2D semiconductor materials as contact interfaces presents advantages over conventional Si-based metal-semiconductor contacts practical applications still face several obstacles. One of the biggest concerns being is the presence of the large contact resistance which can caps the available field effect carrier mobility making intrinsic quantum transport phenomena in the material inaccessible. In this work, we demonstrate the use of 1064 nm pulsed-laser to selectively anneal the metal contacts of the CVD synthesized MoS2 based back gated FET. The improved metal–semiconductor interface after laser annealing resulted in higher mobility and improved On-Off ratio (10^6~10^7). This selective contact annealing enhanced back gated MoS2 FET overall performance metrics by increasing peak field effect mobility, improving current saturation due to decreased contact resistance.Our findings suggest that Pulsed laser annealing of metal contacts in TMD-based FETs can significantly reduce contact resistivity without causing channel or substrate distortion, which is not possible with conventional thermal annealing. This approach can provide most promising application in the field of high-performance two-dimensional semiconductor in flexible/ wearable electronics. Keywords: TMDCs, CVD, MoS2 FET, laser annealing, contact resistance.

2D Amorphous GaOX Gate Dielectric for β-Ga2O3 Field-Effect Transistors.

Appropriate gate dielectrics must be identified to fabricate metal-insulator-semiconductor field-effect transistors (MISFETs); however, this has been challenging for compound semiconductors owing to the absence of high-quality native oxides. This study uses the liquid-gallium squeezing technique to fabricate 2D amorphous gallium oxide (GaOX) with a high dielectric constant, where its thickness is precisely controlled at the atomic scale (monolayer, ∼4.5 nm; bilayer, ∼8.5 nm). Beta-phase gallium oxide (β-Ga2O3) with an ultrawide energy bandgap (4.5-4.9 eV) has emerged as a next-generation power semiconductor material and is presented here as the channel material. The 2D amorphous GaOX dielectric is combined with a β-Ga2O3 conducting nanolayer, and the resulting β-Ga2O3 MISFET is stable up to 250 °C. The 2D amorphous GaOX is oxygen-deficient, and a high-quality interface with excellent uniformity and scalability forms between the 2D amorphous GaOX and β-Ga2O3. The fabricated MISFET exhibits a wide gate-voltage swing of approximately +5 V, a high current on/off ratio, moderate field-effect carrier mobility, and a decent three-terminal breakdown voltage (∼138 V). The carrier transport of the Ni/GaOX/β-Ga2O3 metal-insulator-semiconductor (MIS) structure displays a combination of Schottky emission and Fowler-Nordheim (F-N) tunneling in the high-gate-bias region at 25 °C, whereas at elevated temperatures it shows Schottky emission and F-N tunneling in the low- and high-gate-bias regions, respectively. This study demonstrates that a 2D GaOX gate dielectric layer can be produced and incorporated into an active channel layer to form an MIS structure at room temperature (∼25 °C), which enables the facile fabrication of MISFET devices.

Plasma-optimized contact for high-performance PdSe2 nanoflake-based field-effect transistors

Low-resistance contact has long been pursued in the two-dimensional (2D) electronic/optoelectronic device community. Still, an economy-efficient method highly compatible with the conventional 2D device fabrication process in laboratory remains to be explored. Herein, we report a plasma-optimized contact strategy for high-performance PdSe2 nanoflake-based field-effect transistors (FETs). Selenium vacancies created by air plasma can introduce p-type doping in the contact area, thus optimizing the device performance. The effect of plasma treatment on PdSe2 nanoflake is corroborated by high-resolution transmission electron microscopy, energy-dispersive x-ray spectroscopy spectrum, atomic force microscopy, and Kelvin probe force microscopy. The PdSe2 FET with plasma-optimized contact exhibits significantly improved field-effect carrier mobilities, current on/off ratios, and reduced contact resistance than that without plasma treatment fabricated from the same PdSe2 nanoflake. Moreover, this strategy has also been proven effective to prepare high-performance FETs based on 2D WSe2 and MoSe2 nanoflakes, further demonstrating its application prospect.

Temperature dependence of carrier mobility in hydrogenated germanane field-effect transistor with various electrode materials

Germanane, a layered material in which single-layer germanium is terminated by hydrogen atoms, was utilized as a channel material in back-gate-type FETs. Titanium, aluminum, and nickel were used as source and drain electrodes of FETs, and most of the fabricated FETs showed ambipolar characteristics. Among the three electrode materials, nickel was the best for high field-effect carrier mobility. It was also found that the mobility changes with temperature T according to the T −3/2 law below 273 K, whereas the mobility change deviates from the law of T −3/2 above 293 K.

Electrical and Optical Properties of P-Type NiO Films Grown Via Nickelocene Precursor in a Hollow-Cathode Plasma-ALD Reactor

Electrical and Optical Properties of P-type NiO Films Grown via Nickelocene Precursor in a Hollow-Cathode Plasma-ALD Reactor In contrast to the relative abundance of as-grown unintentionally doped n-type semiconductor materials, there are only a few alternative alloys showing p-type conduction without needing extra high-temperature doping processes. Among them, CuO, Bi2O3, SnO, and NiO represent the most widely studied metal oxides which exhibit native p-type properties. NiO is of particular interest mainly due to its stability and promising performance as hole-transport layers in emerging solar cell device structures. However, to broaden the NiO application domain towards potential back-end-of-the-line (BEOL) transistor devices as potential p-type channel layers, the transport properties of NiO needs to be improved significantly. While low-temperature thermal, plasma, and ozone-assisted ALD efforts have resulted in p-type NiO films with atomic-level precision and large-area uniformity, the hole mobility is far from being sufficient, typically lower than 1 cm2/Vs.In an attempt to enhance the hole transport properties in low-temperature as-grown NiO layers, in this study we have carried out a systematic study on plasma-enhanced ALD (PEALD) of NiO films on Si and glass substrates using nickelocene (NiCp2) and O2/Ar plasma mixture in two separate reactors: (i) 8” plasma-ALD reactor with a quartz-based inductively-coupled plasma (ICP) source; (ii) 4” plasma-ALD reactor with a stainless steel-based hollow-cathode plasma (HCP) source, equipped with an in-situ ellipsometer. 300 cycle ICP-ALD growth experiments with 300 W O2/Ar plasma at 150 °C substrate temperature were carried out to identify the optimal NiCp2 precursor temperature (50 - 110 °C) and observe the influence of precursor pulse time (0.1 - 1 s). Detailed saturation studies using in-situ ellipsometer monitoring were carried out in the HCP-ALD reactor, scanning for NiCp2 pulse time, O2 plasma exposure time, purge time, and plasma power. Optimal growth conditions were identified as 90 ms NiCp2 pulse / 5 s purge / 10 s O2-plasma at 100 W plasma exposure / 5 s purge. To check the growth linearity and obtain thicker films for materials characterization, 800 cycle runs were conducted to evaluate the substrate temperature impact (100 - 250 °C) on growth-per-cycle (GPC) and film properties. The last growth parameter studied was the plasma gas composition, where several O2/Ar mixtures (20/0, 20/20, 50/0 sccm) were tested at the optimal substrate temperature of 200 °C.The resulting NiO films are characterized for their structural, optical, and electrical properties. Films grown at optimal conditions (200 °C) exhibit refractive index values reaching 2.3, which is in good agreement with reported values for the best polycrystalline NiO films in the literature. NiO films deposited on both Si and glass substrates exhibit polycrystalline single-phase cubic structure (c-NiO). Hall measurements of the as-grown NiO layers on glass substrates, revealed film resistivity values about 40 and 150 ohm-cm for HCP and ICP samples, respectively. Post-deposition annealing within 200 – 400 °C temperature range resulted in a significant reduction of resistivity for more than two orders of magnitude. However, the relatively volatile and unstable Hall voltage values led to unreliable carrier concentration and Hall mobility values, therefore we were not able to confirm the type of transport via Hall measurements.In order to determine the carrier type and extract field-effect mobility values, we have fabricated vertical NiO/n-Si p-n junction diodes as well as NiO/Al2O3/Si thin-film-transistor (TFT) device prototypes to characterize diode I-V behavior and confirm p-type layer structure for NiO, and extract the field-effect carrier mobility, respectively. Our I-V measurement results confirmed p-n junction diode characteristics with decent ON/OFF ratios for forward and reverse diode current values. TFT characterization results and findings will be presented as well.

Single β-Ga2O3 nanowire back-gate field-effect transistor

In this work, a normally-on single-monocrystal β-Ga2O3 nanowire (NW) back-gate field-effect transistor (FET) has been demonstrated by transferring metal-organic chemical vapor deposition-grown β-Ga2O3 NWs on sapphire onto SiO2(300 nm)/p +-Si substrate. When the gate voltage (V G) exceeds −14 V, the device is pinched off, with an on/off ratio greater than 108 and a drain leakage current density as low as ∼7.34 fA. The maximum field-effect carrier mobility for these n-doped single β-Ga2O3 NW FETs reaches ∼62.2 cm2 (V s)−1. A prompt degradation in the on/off ratio for these β-Ga2O3 NW back-gate FETs is observed as the operation temperature increased up to 400 K. With strong evidence, the temperature-dependent degradation in the performance is determined by the activation of self-trapped holes and intrinsic vacancy-related defects, both of which would lead to a rapid increase in the channel leakage current at high temperatures.

Perfectness of the main-chain alignment in the conjugated polymer films prepared by the floating film transfer method

Polymer semiconductor/gate dielectric interface is well known to influence the charge transport behaviors in organic field-effect transistors (OFETs). In the unidirectional floating-film transfer method (UFTM), thin floating films of uniaxially aligned π-conjugated polymers are solidified at the air/liquid interface before transferring them onto device substrates. Therefore, packing structures in the films prepared by UFTM are not affected by the strong interactions with the device substrate as usually seen in other film growth methods. Here, one question arises: will the difference in interactions between the liquid substrate and air impact the orientational structure of the polymer chain near the two surfaces or not? To answer this question, we have studied the charge-transport anisotropy in top- and bottom-gate OFETs by changing the film thickness. As a result, the field-effect carrier mobility and its anisotropy did not significantly differ for both surfaces and were constant against the film thickness. These results indicate that the UFTM can provide unidirectional alignment of polymer chains throughout the film thickness and gives a similar superior performance either for a bottom- or a top-gate OFET.

Improved Temporal Response of MoS2 Photodetectors by Mild Oxygen Plasma Treatment.

Temporal response is an important factor limiting the performance of two-dimensional (2D) material photodetectors. The deep trap states caused by intrinsic defects are the main factor to prolong the response time. In this work, it is demonstrated that the trap states in 2D molybdenum disulfide (MoS2) can be efficiently modulated by defect engineering through mild oxygen plasma treatment. The response time of the few-layer MoS2 photodetector is accelerated by 2–3 orders of magnitude, which is mainly attributed to the deep trap states that can be easily filled when O2 or oxygen ions are chemically bonded with MoS2 at sulfur vacancies (SV) sites. We characterized the defect engineering of plasma-exposed MoS2 by Raman, PL and electric properties. Under the optimal processing conditions of 30 W, 50 Pa and 30 s, we found 30-fold enhancements in photoluminescence (PL) intensity and a nearly 2-fold enhancement in carrier field-effect mobility, while the rise and fall response times reached 110 ms and 55 ms, respectively, at the illumination wavelength of 532 nm. This work would, therefore, offer a practical route to improve the performance of 2D dichalcogenide-based devices for future consideration in optoelectronics research.

Study on the Field-effect Carrier Transport of Epitaxial Graphene on SiC

We have studied the field-effect carrier transport of graphene on 4H silicon carbide substrate. In order to extract the electrical parameters, the top-gated field effect transistor has been fabricated. By fitting the measured results with Kim’s model, the field effect carrier mobility (µ) and the metal/graphene contact resistance (Rc) and the residual carrier concentration (n0) are derived to be 3382cm2/Vs, 2250Ω▪µm and 2.18×1013cm-2, respectively. It is noted that the large contact resistance did not affect the high field effect carrier mobility of our device. The high carrier mobility suggests that the SiC epitaxial graphene may be quite suitable for the future high speed electronic applications.

Characterization of Electrical Properties of Suspended ZnO Nanowires Using a Nanorobotic Manipulation System Inside a Scanning Electron Microscope for Nanoelectronic Applications

Electrical characterization of semiconducting oxide nanowires (NWs) is mostly performed using complex techniques, which necessitates a series of costly nanofabrication procedures. In this work, with the aim to provide a low-cost, feasible, facile, and reproducible approach for enabling the study of NW electrical properties, we report direct electrical measurements on individual and overlapped suspended zinc oxide NWs (ZnO NWs). We have succeeded in constructing both two- and three-terminal devices simply by employing tungsten (W) nanoprobes with the aid of a nanomanipulation system embedded inside a scanning electron microscope’s vacuum chamber. Stable contacts were established using the Joule heating effect and e-beam exposure at the junctions between the NW and the pre-cleaned W tips. P-channel field-effect transistor devices were achieved with an on–off current ratio of ∼101, a threshold voltage (>1.5 V), a transconductance of ∼16 μS, a sub-threshold swing of ∼220 mV/decade, and field-effect carrier mobility roughly estimated to be around 926.4 cm2/(V·s) after correction for contact resistances/optimization. The average resistivity of ZnO NWs was calculated to be ∼2.23 × 10–2 Ω·cm for NWs with diameters between 70 and 500 nm. Besides, we have demonstrated a contact resistance of ∼19.60 kΩ and a Schottky barrier height of ∼0.37 eV present at W/ZnO NW interfaces. The contact resistance between two overlapped ZnO NWs was estimated to be ∼283 kΩ, which is relatively higher than that offered between W/ZnO NWs. This work provides a solid experimental procedure to address true intrinsic electrical properties at metal/semiconductor interfaces, and our findings have potential applications in next-generation 3D suspended ZnO NW-based nanoelectronic devices.

Benzohexacene guide in accurate determination of field effect carrier mobilities in long acenes.

Oligoacenes are promising materials in the field of electronic devices since they exhibit high charge carrier mobility and more particularly as a semiconductor in thin film transistors. Herein, we investigate the field effect charge carrier mobility of benzohexacene, recently obtained by cheletropic decarbonylation at moderate temperature. Initially, high performance bottom contact organic thin-film transistors (OTFTs) were fabricated using tetracene to validate the fabrication process. For easier comparison, the geometries and channel sizes of the fabricated devices are the same for the two acenes. The charge transport in OTFTs being closely related to the organic thin film at the dielectric/organic semiconductor interface, the structural and morphological features of the thin films of both materials are therefore studied according to deposition conditions. Finally, by extracting relevant device parameters the benzohexacene based OTFT shows a four-probe contact-corrected hole mobility value of up to 0.2 cm2 V−1 s−1.

Cross-Scale Synthesis of Organic High-k Semiconductors Based on Spiro-Gridized Nanopolymers.

High dielectric constants in organic semiconductors have been identified as a central challenge for the improvement in not only piezoelectric, pyroelectric, and ferroelectric effects but also photoelectric conversion efficiency in OPVs, carrier mobility in OFETs, and charge density in charge-trapping memories. Herein, we report an ultralong persistence length (lp ≈ 41 nm) effect of spiro-fused organic nanopolymers on dielectric properties, together with excitonic and charge carrier behaviors. The state-of-the-art nanopolymers, namely, nanopolyspirogrids (NPSGs), are synthesized via the simple cross-scale Friedel-Crafts polygridization of A2B2-type nanomonomers. The high dielectric constant (k = 8.43) of NPSG is firstly achieved by locking spiro-polygridization effect that results in the enhancement of dipole polarization. When doping into a polystyrene-based dielectric layer, such a high-k feature of NPSG increases the field-effect carrier mobility from 0.20 to 0.90 cm2 V−1 s−1 in pentacene OFET devices. Meanwhile, amorphous NPSG film exhibits an ultralow energy disorder (<50 meV) for an excellent zero-field hole mobility of 3.94 × 10−3 cm2 V−1 s−1, surpassing most of the amorphous π-conjugated polymers. Organic nanopolymers with high dielectric constants open a new way to break through the bottleneck of efficiency and multifunctionality in the blueprint of the fourth-generation semiconductors.

Memory Characteristics of Thin Film Transistor with Catalytic Metal Layer Induced Crystallized Indium-Gallium-Zinc-Oxide (IGZO) Channel

The memory characteristics of a flash memory device using c-axis aligned crystal indium gallium zinc oxide (CAAC-IGZO) thin film as a channel material were demonstrated. The CAAC-IGZO thin films can replace the current poly-silicon channel, which has reduced mobility because of grain-induced degradation. The CAAC-IGZO thin films were achieved using a tantalum catalyst layer with annealing. A thin film transistor (TFT) with SiO2/Si3N4/Al2O3 and CAAC-IGZO thin films, where Al2O3 was used for the tunneling layer, was evaluated for a flash memory application and compared with a device using an amorphous IGZO (a-IGZO) channel. A source and drain using indium-tin oxide and aluminum were also evaluated for TFT flash memory devices with crystallized and amorphous channel materials. Compared with the a-IGZO device, higher on-current (Ion), improved field effect carrier mobility (μFE), a lower body trap (Nss), a wider memory window (ΔVth), and better retention and endurance characteristics were attained using the CAAC-IGZO device.

Fully vertical gallium nitride trench MOSFETs fabricated with metal-free gate first process

We report on the fabrication and characterization of fully vertical gallium nitride trench metal oxide semiconductor field effect transistors on native substrates with a metal-free gate first process and a chlorine-free trench etching method. Trenches were fabricated using sulfur hexafluoride and argon plasma etching in combination with alkaline wet etching posttreatment to create crystal oriented trenches along the a- and m-planes. Low pressure chemical vapor deposited silicon dioxide was used as gate dielectric with a poly-silicon gate contact. The metal-free gate structure was separated by a silicon dioxide passivation from any subsequent metal containing contact formation processing steps. The breakdown robustness of the gate structure was examined in the forward direction and no temperature dependence was observed up to 450 K. Fabricated trench MOSFETs showed only small hysteresis effects during transfer characterization but a positive threshold shift was observed. An inversion channel carrier field effect mobility of ≈10 cm2/V s was extracted. The area specific on resistance was calculated to be 5.8 mΩ cm2. Results for devices with differently oriented trenches were comparable and no significant performance difference was observed.

Improvement of device characteristics of plasma-treated indium gallium zinc oxide thin-film transistors through thermal annealing

In this study, an Ar/O2 plasma mixture treatment with different proportions of O2 was used to reduce the oxygen vacancy density in an amorphous indium gallium zinc oxide (a-IGZO) thin film. The objective was to enhance the field-effect carrier mobility in a thin-film transistor (TFT) with the IGZO film as the channel layer. Atomic force microscopy revealed that the roughness of the IGZO film after plasma treatment was higher than that of the untreated film; however, the surface roughness of the IGZO film decreased after the proportion of O2 was increased in the plasma. The Hall measurement results showed that the resistivity of the plasma-treated IGZO film increased with a decrease in the electron concentration in the film; in addition, the carrier mobility considerably increased. The IGZO TFT fabricated from this film exhibited a high field-effect carrier mobility of 36 cm2 V−1 s−1, a subthreshold swing (SS) of 1.25 V/decade, an I OFF current of 4.58 × 10−11 A, and an I ON/I OFF current ratio of 7.55 × 105. To further improve the device performance, the plasma-treated IGZO films were subjected to thermal annealing with the annealing temperature ranging from 100 °C to 300 °C. After the annealing process, the plasma-treated IGZO TFTs demonstrated a further improvement in the device performance with a field-effect carrier mobility of 38.8 cm2 V−1 s−1, SS of 0.7 V/decade, I OFF current of 1.04 × 10−11 A, and an I ON/I OFF current ratio of 9.93 × 106. In addition, a reliability test was performed to evaluate the stability of the IGZO TFT devices, which revealed that the threshold voltage maintained a high degree of stability during the long-term tests. Therefore, the plasma-treated IGZO TFTs with subsequent postgrowth annealing could be helpful for the fabrication of next-generation flat-panel displays.

Synchronous growth of 30°-twisted bilayer graphene domains with millimeter scale

Bilayer graphene (BLG) with 30°-twist (30°-tBLG) has been proven to possess a quasicrystal structure potentially providing novel applications. Despite the growth of BLG, especially the AB-stacking bilayer, has gained great attention, the growth of 30°-tBLG has been rarely achieved. Herein, for the first time, the decaborane-assisted synchronous growth of millimeter-sized single-crystalline 30°-tBLG was achieved on Cu foil by controlling the nucleation density and growth kinetics of graphene during chemical vapor deposition using diluted methane gas as the carbon source. The synchronous growth kinetics and decaborane-assisted co-catalysis mechanism are revealed by monitoring the growth process from the initial stage of graphene seeds to the millimeter-size scale. A 30°-tBLG based field effect transistor was fabricated and was found to possess a field-effect carrier mobility as high as 3671.3 cm2 V−1 s−1 at room temperature. Thus, this work provides a new strategy to grow high-quality and large-scale 30°-tBLG domains which will facilitate their application in the quasicrystal field.

Low Operating Voltage Organic Field-Effect Transistors with Gelatin as a Moisture-Induced Ionic Dielectric Layer: The Issues of High Carrier Mobility.

We have developed low-voltage (<2 V) flexible organic field-effect transistors (OFETs) with high carrier mobility using gelatin as a moisture-induced ionic gate dielectric system. Ionic concentration in the gelatin layer depends on the relative humidity condition during the measurement. The capacitance of the dielectric layer used for the calculation of field-effect carrier mobility for the OFETs crucially depends on the frequency at which the capacitance was measured. The results of frequency-dependent gate capacitance together with the anomalous bias-stress effect have been used to determine the exact frequency at which the carrier mobility should be calculated. The observed carrier mobility of the devices is 0.33 cm2/Vs with the capacitance measured at frequency 20 mHz. It can be overestimated to 14 cm2/Vs with the capacitance measured at 100 kHz. The devices can be used as highly sensitive humidity sensors. About three orders of magnitude variation in device current have been observed on the changes in relative humidity (RH) levels from 10 to 80%. The devices show a fast response with a response and recovery times of ∼100 and ∼110 ms, respectively. The devices are flexible up to a 5 mm bending radius.

Temperature-stable black phosphorus field-effect transistors through effective phonon scattering suppression on atomic layer deposited aluminum nitride

Abstract Black phosphorus (BP) shows great potential in electronic and optoelectronic applications; however, maintaining the stable performance of BP devices over temperature is still challenging. Here, a novel BP field-effect transistor (FET) fabricated on the atomic layer deposited AlN/SiO2/Si substrate is demonstrated. Electrical measurement results show that BP FETs on the AlN substrate possess superior electrical performance compared with those fabricated on the conventional SiO2/Si substrate. It exhibits a large on-off current ratio of 5 × 108, a low subthreshold swing of &lt;0.26 V/dec, and a high normalized field-effect carrier mobility of 1071 cm2 V−1 s−1 in the temperature range from 77 to 400 K. However, these stable electrical performances are not found in the BP FETs on SiO2/Si substrate when the temperature increases up to 400 K; instead, the electrical performance of BP FETs on the SiO2/Si substrate degrades drastically. Furthermore, to gain a physical understanding on the stable performance of BP FETs on the AlN substrate, low-frequency noise analysis was performed, and it revealed that the AlN film plays a significant role in suppressing the lattice scattering and charge trapping effects at high temperatures.

Mobility improvement in CVD graphene by using local metal side-gate

It has been anticipated that using a side-gate helps in the improvement of mobility over more common top-gate or back-gate graphene transistors. In this work, we presented a method of quantifying the mobility improvement. Transistors are fabricated using chemical vapour deposition graphene on SiO2/Si substrate. Characteristics of two graphene transistors with slightly different geometry are presented. The transistors are fabricated with both, a back-gate and a side-gate. Using results from experiment and technology computer-aided design simulations, field effect mobility of majority carriers (holes) is calculated by two methods. It has been observed that switching from back-gate to side-gate operation on the same transistor results in a mobility improvement of at least 1.64 times. Simulation results presented in this work exhibit a non-perpendicular direction of majority side-gate electric field induced to the two-dimensional graphene channel. This could be one of the reasons behind the mobility improvement. Because in both cases (back-gate and side-gate) the graphene channel is in contact with ambient air on top and SiO2 substrate on bottom.

Contact resistance and mobility in back-gate graphene transistors

The metal-graphene contact resistance is one of the major limiting factors toward the technological exploitation of graphene in electronic devices and sensors. High contact resistance can be detrimental to device performance and spoil the intrinsic great properties of graphene. In this paper, we fabricate back-gate graphene field-effect transistors with different geometries to study the contact and channel resistance as well as the carrier mobility as a function of gate voltage and temperature. We apply the transfer length method and the y-function method showing that the two approaches can complement each other to evaluate the contact resistance and prevent artifacts in the estimation of carrier mobility dependence on the gate-voltage. We find that the gate voltage modulates both the contact and the channel resistance in a similar way but does not change the carrier mobility. We also show that raising the temperature lowers the carrier mobility, has a negligible effect on the contact resistance, and can induce a transition from a semiconducting to a metallic behavior of the graphene sheet resistance, depending on the applied gate voltage. Finally, we show that eliminating the detrimental effects of the contact resistance on the transistor channel current almost doubles the carrier field-effect mobility and that a competitive contact resistance as low as 700 Ω·μm can be achieved by the zig-zag shaping of the Ni contact.