FFT Architecture Research Articles

Reconfigurable data parallel constant geometry fast Fourier transform architectures on Network-on-Chip

This paper reports the design and development of reconfigurable (up to 8192-point), data parallel, constant geometry fast Fourier transform (CG-FFT) architectures based on Network-on-Chip (NoC) paradigm. Twiddle factor multiplications have been realized using pipelined CORDIC rotators in the proposed architecture in order to ensure its high throughput. Mapping of FFT functions to cores has been done by considering the proposed signal flow graph (SFG) for CG-FFT architecture, which helps in optimizing the design of network components (routers and network interfaces) and reducing the latency of FFT computation. The proposed input-size aware architecture can withstand faults in other processing elements (PEs) as it can accomplish the entire FFT computation using only one PE as well. When mapped onto mesh based NoC, the proposed architectures could achieve reduction in latency by 5×, compared to several existing FFT architectures on NoC. Hardware realization of the PE and the network components of the proposed architectures have been done using Xilinx Kintex-7 family field-programmable gate array (FPGA) device. The maximum operating frequency of a PE in the proposed architecture has been found to be 184.010 MHz, which meets the timing specifications of several application standards, such as DVB-T/H, DAB, 802.11a/n and UWB. In addition to the FPGA-prototype, the proposed architectures have also been synthesized in ASIC design flow to obtain area and power results.

FFT Architectures for Real Valued Signals based Different Radices Algorithm

Objectives: The objective of this work is to design efficient FFT architectures for real valued signals. For higher value of N, the design of FFT architecture has many butterflies in the same column. A considerable amount of power is needed for such architecture. The hardware complexity also increases. Methods: The throughput depends on the number of input data paths available, which also increases hardware complexity for higher values of N. This work aims at overcoming these shortcomings by employing one of the effective techniques such as parallel pipelined architectures. One butterfly structure is introduced in one column. For handling the complex data paths, different butterfly structures have been introduced using parallel processing and Folding methodology. The design is simulated in Xilinxs14.3, and synthesized in Cadence RTL compiler. Findings: The hardware complexity is reduced by introducing one butterfly structure in one column. Comparison is made between the different radix algorithms and pipelined architectures and Radix-2 multi path delay commutator (R2MDC) in terms of the required number of adders, delay elements, multiplier units, throughput and control complexity. Although the parallel architecture consumes more power, it occupies less area when compared to the R2MDC architecture. Parallel architecture is more area efficient than R2MDC, whereas the radix-2 multi-path delay commutator is simple to implement, since feedback is not needed in the design. Conclusion: This work can be extended to higher order N-values of DIF and DIT-FFT flow graphs.

A Modified Design of FFT Architecture forWi-Max OFDM Standards to Support bothVariable Length and Multi-streaming

The FFT architecture was reconfigurable for supporting both variable length and multistreaming. They are able to process architecture in 1 stream of 2048-pt FFT or two streams of 1024-pt FFT or 4 stream of 512-pt FFT. The architecture having SDF pipelined stages and in each stage radix-2 butterfly is calculate. The sampling frequency is changed in depend upon the FFT length. The word length and buffer length in each stage is calculate by FFT length. Power consumption was decreases by use of latch gating. Experimental result show that the design increase the throughput expected by the Wi-Max standard. The architecture used fewer amounts of the total available FPGA resources and clock frequency of the system was 13.67 MHz achieved.

Low Power 128 Point Split Radix FFT for LTE Application

In this paper, we describe a processor architecture customized to Split radix FFT algorithm. The proposed architecture supports all FFT sizes, required by the LTE applications. The proposed design is aimed to reduce the area, latency, power and also to reduce the number of computational path in order to speed up FFT processor computation. The proposed low power 128 point split radix FFT architecture applies various periodicity properties of twiddle factors multiplier.We implement the processor in 128-point MDC architecture with split radix algorithm. The processor has been synthesized on a Xilinx ISE 10.1design technology and both energy-efficiency and performance have been evaluated.

Design and Implementation of 1-D and 2-D Mixed Architecture FFT Processor in Heterogeneous Multi-core SoC based on FPGA

A novel architecture FFT processor which can carry on 1-D FFT algorithm or 2-D FFT algorithm corresponding different size of FFT is proposed in this paper. The architecture is served as a scalable IP Core which is suitable for the heterogeneous multi-core SoC on chip application. The mixed architecture FFT processor achieves balance between high processing speed and resources. Compared with a conventional 1-D FFT processor, this FFT processor is characterized by having smaller resources consumption; compared with a 2-D FFT processor which is mapped onto a long point FFT architecture, it has higher processing speed. It employs the Radix-2 DIT-FFT algorithm and fixed addressing structure. It takes two ways to hide time consumed on data-path, one is read-ahead operation of dual-port RAM to hide the delay introduced by 12-stages pipeline of butterfly-unit and Memory access delay; the other is Ping-Pong operation of 3 groups of RAM to conceal data transmitting time. It also adopt twiddle factor compression algorithm to reduce ROM space. It can carry out 2 n (n is from range of 5 to 14) single-precision floating-point FFT/IFFT directly. As a result, we have implemented the mixed architecture FFT processor based on FPGA, and successfully applied it into the heterogeneous multi-core SoC.

A Highly Efficient Multicore Floating-Point FFT Architecture Based on Hybrid Linear Algebra/FFT Cores

FFT algorithms have memory access patterns that prevent many architectures from achieving high computational utilization, particularly when parallel processing is required to achieve the desired levels of performance. Starting with a highly efficient hybrid linear algebra/FFT core, we co-design the on-chip memory hierarchy, on-chip interconnect, and FFT algorithms for a multicore FFT processor. We show that it is possible to to achieve excellent parallel scaling while maintaining power and area efficiency comparable to that of the single-core solution. The result is an architecture that can effectively use up to 16 hybrid cores for transform sizes that can be contained in on-chip SRAM. When configured with 12MiB of on-chip SRAM, our technology evaluation shows that the proposed 16-core FFT accelerator should sustain 388 GFLOPS of nominal double-precision performance, with power and area efficiencies of 30 GFLOPS/W and 2.66 GFLOPS/mm2, respectively.

An Implementation of Pipelined Radix-4 FFT Architecture on FPGAs

An Implementation of Pipelined Radix-4 FFT Architecture on FPGAs

A Novel Architecture for Radix-4 Pipelined FFT Processor using Vedic Mathematics Algorithm

The FFT processor is a critical block in all multi-carrier systems used primarily in the mobile environment. The portability requirement of these systems is mainly responsible for the need of low power FFT architectures. In this study, an efficient addressing scheme for radix-4 64 point FFT processor is presented. It avoids the modulo-r addition in the address generation; hence, the critical path is significantly shorter than the conventional radix-4 pipelined FFT processor by modifying its operation sequence. The complex multiplier is one of the most power consuming blocks in the FFT processor. A significant property of the proposed method is that the critical path of the address generator is independent from the FFT transform length N, making it extremely efficient for large FFT transforms. The results confirm the speed and area advantages for large FFTs. Although only radix-4 FFT address generation is presented in the paper, it can be used for higher radix-4FFT.

Continuous-flow Parallel Bit-Reversal Circuit for MDF and MDC FFT Architectures

This paper presents a bit reversal circuit for continuous-flow parallel pipelined FFT processors. In addition to two flexible commutators, the circuit consists of two memory groups, where each group has P memory banks. For the consideration of achieving both low delay time and area complexity, a novel write/read scheduling mechanism is devised, so that FFT outputs can be stored in those memory banks in an optimized way. The proposed scheduling mechanism can write the current successively generated FFT output data samples to the locations without any delay right after they are successively released by the previous symbol. Therefore, total memory space of only N data samples is enough for continuous-flow FFT operations. Since read operation is not overlapped with write operation during the entire period, only single-port memory is required, which leads to great area reduction. The proposed bit-reversal circuit architecture can generate natural-order FFT output and support variable power-of-2 FFT lengths.

An In-Place FFT Architecture for Real-Valued Signals

This brief presents a novel scalable architecture for in-place fast Fourier transform (IFFT) computation for real-valued signals. The proposed computation is based on a modified radix-2 algorithm, which removes the redundant operations from the flow graph. A new processing element (PE) is proposed using two radix-2 butterflies that can process four inputs in parallel. A novel conflict-free memory-addressing scheme is proposed to ensure the continuous operation of the FFT processor. Furthermore, the addressing scheme is extended to support multiple parallel PEs. The proposed real-FFT processor simultaneously requires fewer computation cycles and lower hardware cost compared to prior work. For example, the proposed design with two PEs reduces the computation cycles by a factor of 2 for a 256-point real fast Fourier transform (RFFT) compared to a prior work while maintaining a lower hardware complexity. The number of computation cycles is reduced proportionately with the increase in the number of PEs.

Distributed Arithmetic based Split-Radix FFT

In this paper we have designed a Split-radix type FFT unit without using multipliers. All the complex multiplications required for this type of FFT are implemented using Distributed Arithmetic (DA) technique. A method is incorporated to overcome the result overflow problem introduced by DA method. Proposed FFT architecture is implemented in 180 nm CMOS technology at a supply voltage of 1.8 V.

Low Power R4SDC Pipelined FFT Processor Architecture

When the real-time signal processing is required pipelined FFT is the suitable option because of its high throughput and low power demands. A number of FFT architectures are there. Radix-4 single delay commutator (R4SDC) architecture is researched in this paper. R4SDC is the most popular pipeline FFT architectures, because of its efficient use of butterflies and multipliers. In this a low power technique for the pipeline FFT architecture is discussed. In this, Conventional R4SDC architecture, complex multiplier, and multiplier-less architecture based on common sub-expression technique are implemented and compared for 16, 64 and 256-point FFT architectures. A new type of multiplier algorithm called Multiplier-less architecture is implemented and compared with the carry save array, Wallace and Conventional complex multiplier (NBW).

Pipelined Radix-$2^{k}$ Feedforward FFT Architectures

The appearance of radix-2 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> was a milestone in the design of pipelined FFT hardware architectures. Later, radix-2 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> was extended to radix-2 <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">k</i> . However, radix-2 <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">k</i> was only proposed for single-path delay feedback (SDF) architectures, but not for feedforward ones, also called multi-path delay commutator (MDC). This paper presents the radix-2 <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">k</i> feedforward (MDC) FFT architectures. In feedforward architectures radix-2 <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">k</i> can be used for any number of parallel samples which is a power of two. Furthermore, both decimation in frequency (DIF) and decimation in time (DIT) decompositions can be used. In addition to this, the designs can achieve very high throughputs, which makes them suitable for the most demanding applications. Indeed, the proposed radix-2 <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">k</i> feedforward architectures require fewer hardware resources than parallel feedback ones, also called multi-path delay feedback (MDF), when several samples in parallel must be processed. As a result, the proposed radix-2 <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">k</i> feedforward architectures not only offer an attractive solution for current applications, but also open up a new research line on feedforward structures.

A new low-power butterfly unit for single-path delay feedback FFT architectures

A new low-power butterfly unit for single-path delay feedback FFT architectures

Design of a Radix-8/4/2 variable FFT processor for OFDM systems

In this paper, we propose an efficient variable-length radix-8/4/2 FFT architecture for OFDM systems. The FFT processor is based on radix-8 FFT algorithm and also supports radix-4 or radix-2 FFT computation. We are using efficient In-place memory access method to maintain conflict-free data access and minimize memory size. Also we replace a very large lookup table with a twiddle factor generator which consumes less area then a ROM-based lookup table. The proposed FFT processor performs variable-length FFT including 64, 256, 512, 1024, 2048, 4096 and 8192 points which cover all the required FFT lengths used in 802.11a, 802.16a, DAB, DVB-T, VDSL and ADSL.

Design of dynamically reconfigurable fully optimized low power FFT architecture for MC-CDMA receiver

Design of dynamically reconfigurable fully optimized low power FFT architecture for MC-CDMA receiver

Dynamic Partial Reconfigurable FFT for OFDM Based Communication Systems

This paper presents a novel scalable and runtime dynamically reconfigurable FFT architecture for different wireless standards. With only 8 butterfly units, a reconfigurable FFT architecture for three different FFT points is realized using mixed radix-22/23/24 FFT algorithm in a modified Single-path Delay Feedback (SDF) pipelined architecture. Via a proper data flow reconfiguration it can support 64, 128 and 256. It can even be extended up to 8192-point transforms and uses only 13 butterfly units to realize 8192 points. This paper describes the implementation method of 256 and 128 point FFT, which is reconfigured partially from 64 point FFT. The whole system is implemented on a Xilinx XC2VP30 FPGA device. The implementation design addresses area efficiency and flexibility allowing the insertion of the partial modules dynamically to realize various FFT sizes. To verify the efficacy of this dynamic partial reconfigurable FFT design method, a conventional multiplexer based reconfigurable architecture was designed and tested on the same platform. Tested FPGA results for the Dynamic Partial Reconfigurable (DPR) method show the configuration time improvement and good area efficiency as compared to the reconfigurable architecture using conventional multiplexer techniques.

효율적인 파이프라인 구조와 스케줄링 기법을 적용한 고속 8-병렬 FFT/IFFT 프로세서

본 논문에서는 고속 데이터 전송을 위해 OFDM 시스템에 적용 가능한 고속 FFT/IFFT 프로세서를 제안하였다. 제안하는 프로세서는 높은 데이터 처리율을 만족하기 위해서 MDC 구조와 다중 병렬 처리 기법을 채택하였다. 하드웨어 복잡도를 줄이기 위해서 본 논문에서는 연산에 필요한 연산기의 수를 줄이는 구조로 버터플라이 연산기의 수를 줄인 MRMDC 구조와 효율적인 스케줄링 기법을 적용하여 복소 곱셈기의 수를 줄이는 구조를 제안한다. 제안하는 구조를 적용함으로써 연산 싸이클을 증가시키지 않고 하드웨어 복잡도를 줄일 수 있다. UWB, WiMAX, O-OFDM과 같은 고속 OFDM 시스템을 위해 제안하는 프로세서는 128-포인트와 256-포인트 두 가지 모드를 지원 가능하다. 제안하는 프로세서는 IBM 90nm 공정으로 합성하여 메모리를 제외한 전체 게이트 수가 760,000개를 보이며, 동작속도는 430MHz를 나타내었다. This paper presents a novel eight-parallel 128/256-point mixed-radix multi-path delay commutator (MRMDC) FFT/IFFT processor for orthogonal frequency-division multiplexing (OFDM) systems. The proposed FFT architecture can provide a high throughput rate and low hardware complexity by using an eight-parallel data-path scheme, a modified mixed-radix multi-path delay commutator structure and an efficient scheduling scheme of complex multiplications. The efficient scheduling scheme can reduce the number of complex multipliers at the second stage from 88 to 40. The proposed FFT/IFFT processor has been designed and implemented with the 90nm CMOS technology. The proposed eight-parallel FFT/IFFT processor can provide a throughput rate of up to 27.5Gsample/s at 430MHz.

Comparison of area-efficient FFT algorithms for DVB-T2 receivers

Comparison at implementation level of several pipeline-SDF radix 2k FFT architectures is proposed in order to obtain efficient algorithms for DVB-T2 receivers. In the analysis, the area and performance of the algorithms are compared. A variable datapath optimisation has been added to the comparison.

A Pipelined FFT Architecture for Real-Valued Signals

This paper presents a new pipelined hardware architecture for the computation of the real-valued fast Fourier transform (RFFT). The proposed architecture takes advantage of the reduced number of operations of the RFFT with respect to the complex fast Fourier transform (CFFT), and requires less area while achieving higher throughput and lower latency. The architecture is based on a novel algorithm for the computation of the RFFT, which, contrary to previous approaches, presents a regular geometry suitable for the implementation of hardware structures. Moreover, the algorithm can be used for both the decimation in time (DIT) and decimation in frequency (DIF) decompositions of the RFFT and requires the lowest number of operations reported for radix 2. Finally, as in previous works, when calculating the RFFT the output samples are obtained in a scrambled order. The problem of reordering these samples is solved in this paper and a pipelined circuit that performs this reordering is proposed.