FET Model Research Articles

A new analytical drain current model of cylindrical gate silicon tunnel FET with source δ-doping

A new δ-doped cylindrical gate silicon tunnel FET (DCG-TFET) analytical model is developed and investigated extensively, with the aim of addressing the challenges of the conventional CG-TFET. The improvement in tunneling probability of charge carriers has been achieved by inserting a δ-doping sheet in the source region which leads to high drain current as compared to CG-TFET. The effect of distance between the δ-doping sheet and source/channel interface on the current performance, sub-threshold swing (SS) and threshold voltage (Vth) has been examined. The instantaneous position of δ-doping region from the tunneling junction is optimized based on the trade-off between current ratio and SS. The present model exhibit maximum switching current ratio (IONIOFF≅1012) for an optimum distance of 2 nm without degrading SS (SS∼55 mV/decade) and Vth performance. The electrostatic behavior of the present model is obtained using the solution of Poisson’s equation in the cylindrical coordinate system. However the impact of scaling of the gate oxide thickness and cylindrical pillar diameter on drain current performance has been discussed. In future, DCG-TFET can be one of the potential successors for ultra-low-power applications because of its improved drain current and switching ratio.

Analysis of independent gate operation in Si nano tube FET and threshold prediction model using 3D numerical simulation

In this paper, silicon nanotube field effect transistors (SiNT-FETs) are investigated for independent gate operation using 3D numerical simulation. The parameters, $$\mathrm{I_{ON} , I_{OFF}, V_{T}}$$ION,IOFF,VT, and the unity gain cut-off frequency $$\mathrm{(f_{T}}$$(fT) are studied in the independent-gate mode. The SiNT-FET we have considered has two gates, namely outer and inner gates, and can be simultaneously driven or independently driven. The physical gate oxide thicknesses of the outer and inner gates of the device are to be converted into effective gate oxide thicknesses due to the non-Euclidean geometry associated with the tube structure. The effective gate oxide thicknesses are different for the same outer and inner physical gate oxide thickness. Since the inner and outer gates are asymmetric, the device parameters extracted at the outer and inner gates are different. Since the independent gate operation allows dynamic threshold voltage adjustment, a model to predict the threshold voltage also known as the threshold voltage sensitivity model is developed for the SiNT device by modifying the double gate FinFET model. These models are verified by TCAD simulation results to validate their accuracy.

Comments on “Optimization of a Compact I–V Model for Graphene FETs: Extending Parameter Scalability for Circuit Design Exploration”

In the above paper, Iannazzo et al. propose an improvement of the compact model by introducing a new expression for the description of the bias-dependent saturation velocity. They compare their model to simulation results using the compact model. We comment on this paper, since Iannazzo et al. use inappropriate parameter values for the compact model. We further show that with suitable parameter values, the results from both models are very close.

Author’s Reply to “Comments on ‘Optimization of a Compact I–V Model for Graphene FETs: Extending Parameter Scalability for Circuit Design Exploration’ ” S. Frégonèse and T. Zimmer

We appreciate the careful analysis and comments by Fregonese and Zimmer [1] with respect to [2] , where they show that the model proposed in [3] accurately reproduces experimental data from graphene FETs (GFETs) when an appropriate smoothing factor is used. In [2] , we have proposed an extension of this model by Fregonese et al. [3] with an exact calculation of a denominator. We compared the model extension with the original work. Unfortunately, we did not use a suitable smoothing factor in our comparison, which lead to a strong artifact in the calculations and was absent in the exact solution. Following the argument in [1] , we agree with our colleagues that there is no artifact at the Dirac point in their GFET compact-model when a proper smoothing factor is used. We were not aware of the requirement of such a factor in specific cases when implementing the model because it is not mentioned in [3] ; therefore, we apologize for misrepresenting their work.

III–V Tunnel FET Model With Closed-Form Analytical Solution

Using an idealized semianalytical model of charge transport for InAs-based tunneling FET, it is shown that the output and transfer characteristics can be accurately reproduced and could be used to develop compact models. The use of a mathematical approximation for the analytical solution of the surface potential is vital here to minimize the computation time. The 20-nm gate homojunction and 40-nm gate heterojunction transistors have been simulated and compared with the calibrated numerical simulation results. The results are in good agreement.

A Gaussian approach for analytical subthreshold current model of cylindrical nanowire FET with quantum mechanical effects

This paper proposes an analytical subthreshold current model for undoped/lightly doped Cylindrical Nanowire FETs (CGNWFETS) including quantum effects. The model is derived from direct use of Gauss's law, Drift Diffusion Approach (DDA) and effective Band Gap Widening (BGW). The Quantum Mechanical Effects (QMEs) are included in the model by taking the effects of BGW, which reduces the electron density in the subthreshold regime and reduces the subthreshold current consequently. The model explicitly shows how the oxide thickness, gate workfunction, and silicon thickness have an effect on the subthreshold current. The results obtained using proposed model is verified by comparison through SILVACO Atlas TCAD simulation; quite good agreement has been observed between model and numerical simulations results.

Effect of Edge Roughness on Static Characteristics of Graphene Nanoribbon Field Effect Transistor

In this paper, we present a physics-based analytical model of GNR FET, which allows for the evaluation of GNR FET performance including the effects of line-edge roughness as its practical specific non-ideality. The line-edge roughness is modeled in edge-enhanced band-to-band-tunneling and localization regimes, and then verified for various roughness amplitudes. Corresponding to these two regimes, the off-current is initially increased, then decreased; while, on the other hand, the on-current is continuously decreased by increasing the roughness amplitude.

Modeling of nonlinear thermal resistance in FinFETs

In this paper, self-consistent three-dimensional (3D) device simulations for exact analysis of thermal transport in FinFETs are performed. We analyze the temperature rise in FinFET devices with the variation in the number of fins (Nfin), shape of fins and fin pitch (Fpitch). We investigate that the thermal resistance Rth has nonlinear dependency on Nfin and Fpitch. We formulate a model for thermal resistance behavior correctly with Nfin and Fpitch variation. The proposed formulation is implemented in industry standard Berkeley short-channel independent gate FET model for common multi-gate transistors (BSIM-CMG) and validated with both experimental data and TCAD simulations.

A New Short-Channel-Effect-Degraded Subthrehold Behavior Model for Double-Fin Multi-Channel FETs (DFMcFETs)

On the basis of the quasi-three-dimensional scaling equation and minimum bottom-central potential, a new short-channel-effect-degraded subthreshold behavior model for double-Fin multichannel FET (DFMcFET) is presented. It is shown that the deep trench of the DFMcFET is superior to the shallow one in respect of suppressing short-channel effects (SCEs) and reducing the threshold voltage roll-off and subthreshold roll-up. Meanwhile, the wide trench and thin gate oxide are required to resist SCEs and reduce the subthreshold behavior degradation as the channel length is further decreased. In comparison to the counterpart of conventional FinFET, DFMcFET not only provides the more conducting channel, but also enhances the immunity to SCEs due to its shorter scaling length. Besides, both threshold voltage roll-off Δ V TH and subthreshold swing roll-up ΔSS can be well controlled by the scaling theory. The allowable minimum channel length can be uniquely determined according to the criterion of the scaling factor. With its computational efficiency and simple form, the model can be easily used for the circuit application of the DFMcFET.

Modeling and Simulation of Junction Temperature Rise of GaN Devices for Class D Resonant Converters

Reliability of power electronic devices is related to their thermal performance. This paper presents the development of an electro-thermal model used to estimate junction temperature rise from self-heating effect in a GaN FET. Transient thermal impedances of the power device and the customized heat sink are extracted as a Foster thermal network before converting to a Cauer network to allow direct integration between multiple thermal networks. The proposed thermal impedance networks provide junction temperature information to the temperature-dependent SPICE model of the GaN FET so that self-heating effect is captured. The model is validated in SPICE simulation using a class D resonant converter as a case study. The results reveal the tendency of mismatch device temperature over a period of time posing a concern for the converter.

A Non-Quasi-Static FET Model Extraction Procedure Using the Dynamic-Bias Technique

We extend the recently proposed dynamic-bias measurement technique to the identification of non-quasi-static FET models. In particular, we propose to exploit two high-frequency tickles superimposed on the low-frequency large-signal excitation. The tickle frequencies are chosen in order to separately extract the quasi-static and non-quasi-static model parameters. As case study, we extracted and validated the model of an $800\times 0.35-\mu{\rm m}^{2}$ GaAs pHEMT.

An Accurate Physics-Based Compact Model for Dual-Gate Bilayer Graphene FETs

In this paper, an accurate compact model based on physical mechanisms for dual-gate bilayer graphene FETs is presented. This model is developed based on the 2-D density of states of bilayer graphene and is implemented in Verilog-A. Furthermore, physical equations describing the behavior of the source and drain access regions under back-gate bias are proposed. The accuracy of the developed large-signal compact model has been verified by comparison with measurement data from the literature.

Resistance-Based Approach for Drain Current Modeling in Graphene FETs

In this paper, a resistance-based drain current model for dual-gate graphene FETs (GFETs) is presented, in which an existing analytical model for the sheet charge density for dual-gate structures has been extended for single-gate architectures. In addition, in order to ensure charge and potential continuity throughout the device, unaccounted for in the literature, a new parameter, Debye length, for graphene has been introduced, and a heuristic model for it has been proposed. The carrier mobility in graphene has been modeled in this paper by proposing a new hypothesis for carrier transport in the graphene layer of GFETs, and is a function only of the applied voltages—resulting in significant savings in terms of computational time. Also, the source and drain region resistances (assumed constant in the literature, which is physically unacceptable) have been modeled in this paper based on the charge distributions in these regions. The modeled drain current not only produced well-behaved drain conductance and transconductance over the entire bias range but also showed a very good match with the experimental data published elsewhere, while reducing the maximum error as compared with the simulated results of some existing works.

High-Voltage Organic Thin-Film Transistors on Flexible and Curved Surfaces

A pentacene (C22H14)-based high-voltage organic thin-film transistor (HVOTFT) was demonstrated on both a rigid and a flexible substrate. The HVOTFT showed minimal degradation of the current–voltage ( $I$ – $V$ ) characteristics under flexure. Consistent with the previous reports on amorphous silicon (a-Si) TFTs, the offset drain/source structure enabled high-voltage operation, allowing for the HVOTFT to switch very large drain-to-source voltages ( $V_{\text {DS}} > 300$ V) with a relatively lower controlling voltage (0 $\text {V} V). The HVOTFT was evaluated with three different gate insulators to assess how the dielectric constant and interface states influence device performance. Due to the high electric field generated in the device, the HVOTFT suffered from impeded charge injection into the gated semiconductor channel, similar to that reported in a-Si-based high-voltage TFTs, as well as from a nonsaturating $I$ – $V$ characteristic behavior similar to the short-channel effects found in FETs. A field plate was implemented to improve charge injection into the gated semiconductor channel. Output characteristics of the HVOTFT were numerically corrected to demonstrate that the device $I$ – $V$ can be modeled with the existing Si-based FET models.

A Physics-Based Model of Double-Gate Tunnel FET for Circuit Simulation

ABSTRACTTunnel FETs (TFETs) having better ON–OFF switching performance is an alternative nano-device that replaces MOSFET (metal oxide field effect transistor) in low-power VLSI (very large scale integration) circuits. The physics-based models of TFETs are essential to integrate with circuit simulators for design and optimization of TFET-based circuits. There is no built-in TFET model available in any commercial circuit simulators. This paper presents the development of an accurate physics-based model for double-gate TFET and its integration in Cadence circuit simulator SPECTRE. The model captures all device physics and is evaluated for various device parameters such as channel length, oxide thickness, and high-κ dielectrics and validated with results from TCAD (Technology Computer Aided Design) Sentaurus. The integrated model is used to develop digital libraries of logic gates and adders. These digital libraries can be used to design TFET-based VLSI circuits. This method of integration using physics-based model of TFET, compared to look-up table approach which is purely data-driven, gives flexibility to circuit designers to design TFET-based low-power circuits taking into account the dependence on bias, temperature, scaling, and other process parameters.

Small-signal microwave measurements and modeling of GaN FET devices manufactured by ITME

Small-signal microwave measurements and modeling of GaN FET devices manufactured by ITME

A new approach for signal and noise FET modeling including wave propagation effects

AbstractIn the millimeter‐wave frequency range, electromagnetic effects can significantly influence a device behavior. As the core of modern communication systems, active devices such as field‐effect transistors require up‐to‐date models to accurately integrate such effects, especially in terms of noise performance because most of communication systems operate in noisy environments. Based on the active coupled line concept, a novel approach for efficient noise performance modeling of millimeter‐wave field‐effect transistors is proposed. This distributed model considers the effect of wave propagation along the device electrodes, which can significantly affect the noise performance, especially in the millimeter‐wave range. Copyright © 2015 John Wiley & Sons, Ltd.

A new analytical threshold voltage model of cylindrical gate tunnel FET (CG-TFET)

The cylindrical gate tunnel FET (CG-TFET) is one of the potential candidates for future nano-technology, as it exhibit greater scaling capability and low subthreshold swing (SS) as compared to conventional MOSFET. In this paper, a new analytical approach is proposed to extract the gate dependent threshold voltage for CG-TFET. The potential distribution and electric field distribution in the cylindrical channel has been obtained using the 2-D Poisson’s equation which in turn computes the shortest tunneling distance and tunneling current. The threshold voltage is extracted using peak transconductance change method based on the saturation of tunneling barrier width. The impact of scaling of effective oxide thickness, cylindrical pillar diameter and gate length on the threshold voltage has been investigated. The consistency of the proposed model is validated with the TCAD simulated results. The present model can be a handful for the study of switching behavior of TFET.

A Core Compact Model for Multiple-Gate Junctionless FETs

A core model for multiple-gate junctionless FETs (Mug-JL-FETs) is proposed. The derived charge model is obtained via assumptions of simple potential profile for different types of Mug-JL-FETs. It was found that the linear potential approach is not accurate enough for a double-gate (DG) JL-FET, whereas it was reasonably precise for a DG inversion-mode FET. This discrepancy arises from their different operating mechanisms. Thus, the parabolic potential assumption, which is intuitively close to an actual potential profile in the Mug-FETs, was applied. As a consequence, two different formulas of the charge model in terms of depletion charges, gate capacitance, and capacitance inside the channel were found: one for a tetragonal shape of a cross-sectional channel based on a Cartesian coordinate and the other for a circular shape of a cross-sectional channel based on a cylindrical coordinate. Moreover, the proposed approach was applied for a realistically shaped channel, which is close to elliptic geometry, with a circular profile at the top and bottom parts of the channel and a rectangular profile at the center part of the channel. By applying the decoupling method reported previously, a drain current model, which is extended from the above-mentioned charge model, was also obtained.

An Analytic Model for Heterojunction Tunnel FETs With Exponential Barrier

This paper presents an analytic model for double-gate tunnel FETs with an exponential barrier. By carrying out the Wentzel-Kramer–Brillouin integral in closed form, an $I$ – $V$ model is formulated in terms of a single integral of a continuous function with respect to energy. The model shows that source degeneracy helps the linear region $I_{\mathbf {ds}}$ – $V_{\mathbf {ds}}$ characteristics, but degrades the saturation current. Also investigated is the role of the effective density of states on the debiasing of $V_{\mathbf {gs}}$ due to channel inversion charge at low $V_{\mathbf {ds}}$ . A high effective density of states is shown to lead to superlinear $I_{\mathbf {ds}}$ – $V_{\mathbf {ds}}$ characteristics.