Ferroelectric Transistors Research Articles

Exploration of structural influences on the ferroelectric switching characteristics of ferroelectric thin-film transistors.

In this paper, quantitative analysis was performed focusing on the structural effect on the ferroelectric switching of ferroelectric thin-film transistors (FeTFTs). FeTFTs and ferroelectric capacitor (FeCap) test element groups (TEGs) were designed and fabricated, and positive-up-negative-down (PUND) measurements were performed to analyze the switching characteristics of ferroelectric films in various structures constituting an FeTFT. It was verified that TiN/HZO/a-IGZO/Mo (MFSM, FeTFT source/drain contact) mostly contributed to the memory operation of an FeTFT, while TiN/HZO/a-IGZO (MFS, FeTFT channel) exhibits one-time memory operation with irreversible polarization switching. In addition, the switching characteristics of MFSM and MFS were different from those of MFM, especially after a few cycles, related to the oxygen vacancy migration between a-IGZO channels and HZO films. The extracted 2Pr values for MFS, MFSM and TiN/HZO/Mo (MFM, FeTFT source/drain parasitic capacitor) were 38, 28 and 20 [μC cm-2], respectively. Based on the operation differences according to the device structure, it was found that irreversible switching in the MFS region (channel) causes a rapid decrease in the memory window after the first switching in an FeTFT and degradation of a-IGZO and HZO films in the MFSM region (contact) including oxygen vacancy exchange and related defect generation causes subthreshold slope increases and negative threshold voltage shifts as cycling stress was applied.

Fully Electrically Modulated Hetero-Synapses With Lateral Multigate Ferroelectric Thin Film Transistor

Fully Electrically Modulated Hetero-Synapses With Lateral Multigate Ferroelectric Thin Film Transistor

Comparative Evaluation of Ferroelectric Negative Capacitance MFMIS and MFIS Transistors for Analog/Radio-Frequency Applications

Comparative Evaluation of Ferroelectric Negative Capacitance MFMIS and MFIS Transistors for Analog/Radio-Frequency Applications

On the Potential of Ambipolar Schottky-Based Ferroelectric Transistor Designs for Enhanced Memory Windows in Scaled Devices

On the Potential of Ambipolar Schottky-Based Ferroelectric Transistor Designs for Enhanced Memory Windows in Scaled Devices

Integration of Machine Learning with Statistical Variation Analysis for Ferroelectric Transistor (FE-MOSFETs)

This paper investigates a comparative analysis of technology computer-aided design (TCAD) versus machine learning (ML) technique for ferroelectric-based substrate metal oxide semiconductor field effect transistor (FE-MOSFET), which shows the low power energy storage device and ML algorithms reduce the time or overall process. The simulations carried out through TCAD require approximately 44–46 days, encompassing variations in input parameters like gate work function ([Formula: see text]), doping concentration ([Formula: see text]), channel doping ([Formula: see text]), gate-to-source voltage ([Formula: see text]), and drain-to-source voltage ([Formula: see text]). In order to lower the computing cost of numerical TCAD device simulations, a new ML-assisted technique is provided for studying the FE-MOSFET. To reduce the runtime of physics-based TCAD by about 10–12[Formula: see text]h for each iteration, a ML-based prediction alternative is created. The proposed combination of TCAD device simulation and ML algorithms is the future of the next generation of electronics.

Optimization Method for Conductance Modulation in Ferroelectric Transistor for Neuromorphic Computing

AbstractThe learning accuracy of neuromorphic computing that mimics the biological brain, is affected by the conductance‐modulation characteristics of an artificial synapse. In ferroelectric‐based devices, these characteristics are implemented using a distribution of polarization values. Therefore, the distribution in a ferroelectric thin film with various external voltage signals is investigate. As polarization switching proceeds with voltage pulse, the domains of the switched polarization become larger. In ferroelectric‐gate field effect transistors, the channel layer assumed to lie beneath the ferroelectrics experiences a local conductance change, according to the polarization distribution of the ferroelectric layer. It is found that small clusters with high conductivity become large clusters in the channel layer as the polarization switching proceeds. When the additional pulses are applied, the high conductive regions eventually connect (i.e., percolate) in the channel layer and the conductance of the layer is greatly increased. Adjusting the height of the applied voltage can slow down or speed up this phenomenon. Also, the nanosecond voltage pulses are employed and the width of the conductive pathway is adjusted. It enables to fine‐tune the conductance of the channel layer. It demonstrates that conductance modulation is optimized with an appropriate voltage pulse train pattern.

Hierarchical processing enabled by 2D ferroelectric semiconductor transistor for low-power and high-efficiency AI vision system

The growth of data and Internet of Things challenges traditional hardware, which encounters efficiency and power issues owing to separate functional units for sensors, memory, and computation. In this study, we designed an α-phase indium selenide (α-In2Se3) transistor, which is a two-dimensional ferroelectric semiconductor as the channel material, to create artificial optic-neural and electro-neural synapses, enabling cutting-edge processing-in-sensor (PIS) and computing-in-memory (CIM) functionalities. As an optic-neural synapse for low-level sensory processing, the α-In2Se3 transistor exhibits a high photoresponsivity (2855 A/W) and detectivity (2.91 × 1014 Jones), facilitating efficient feature extraction. For high-level processing tasks as an electro-neural synapse, it offers a fast program/erase speed of 40 ns/50 µs and ultralow energy consumption of 0.37 aJ/spike. An AI vision system using α-In2Se3 transistors has been demonstrated. It achieved an impressive recognition accuracy of 92.63% within 12 epochs owing to the synergistic combination of the PIS and CIM functionalities. This study demonstrates the potential of the α-In2Se3 transistor in future vision hardware, enhancing processing, power efficiency, and AI applications.

Degradation of the Properties of SOS Ferroelectric Pseudo-MOS Transistors after Irradiation with Fast Heavy Xe and Bi Ions

Degradation of the Properties of SOS Ferroelectric Pseudo-MOS Transistors after Irradiation with Fast Heavy Xe and Bi Ions

Ferroelectric transistors based on shear-transformation-mediated rhombohedral-stacked molybdenum disulfide

Ferroelectric transistors based on shear-transformation-mediated rhombohedral-stacked molybdenum disulfide

Dopant Engineering of Hafnia-Based Ferroelectrics for Long Data Retention and High Thermal Stability.

Hafnia-based ferroelectrics have gained much attention because they can be used in highly scaled, advanced complementary metal-oxide semiconductor (CMOS) memory devices. However, thermal stability should be considered when integrating hafnia-based ferroelectric transistors in advanced CMOS devices, as they can be exposed to high-temperature processes. This work proposed that doping of Al in hafnia-based ferroelectric material can lead to high thermal stability. A ferroelectric capacitor based on Al-doped hafnia, which can be used for one-transistor-one-capacitor applications, exhibits stable operation even after annealing at 900°C. Moreover, it demonstrates that the ferroelectric transistors based on Al-doped hafnia for one-transistor applications, such as ferroelectric NAND, retain their memory states for 10 years at 100°C. This study presents a practical method to achieve thermally stable ferroelectric memories capable of enduring high-temperature processes and operation conditions.

Low-Thermal-Budget Ferroelectric Field-Effect Transistors Based on CuInP2S6 and InZnO.

In this paper, we demonstrate low-thermal-budget ferroelectric field-effect transistors (FeFETs) based on the two-dimensional ferroelectric CuInP2S6 (CIPS) and oxide semiconductor InZnO (IZO). The CIPS/IZO FeFETs exhibit nonvolatile memory windows of ∼1 V, low off-state drain currents, and high carrier mobilities. The ferroelectric CIPS layer serves a dual purpose by providing electrostatic doping in IZO and acting as a passivation layer for the IZO channel. We also investigate the CIPS/IZO FeFETs as artificial synaptic devices for neural networks. The CIPS/IZO synapse demonstrates a sizable dynamic ratio (125) and maintains stable multilevel states. Neural networks based on CIPS/IZO FeFETs achieve an accuracy rate of over 80% in recognizing MNIST handwritten digits. These ferroelectric transistors can be vertically stacked on silicon complementary metal-oxide semiconductor (CMOS) with a low thermal budget, offering broad applications in CMOS+X technologies and energy-efficient 3D neural networks.

Polarization Switching and Charge Trapping in HfO2-Based Ferroelectric Transistors

Polarization Switching and Charge Trapping in HfO₂-Based Ferroelectric Transistors

Nonvolatile Memory Organic Light-Emitting Transistors.

In the field of active-matrix organic light emitting display (AMOLED), large-size and ultra-high-definition AMOLED applications have escalated the demand for the integration density of driver chips. However, as Moore's Law approaches the limit, the traditional technology of improving integration density that relies on scaling down device dimension is facing a huge challenge. Thus, developing a multifunctional and highly integrated device is a promising route for improving the integration density of pixel circuits. Here, a novel nonvolatile memory ferroelectric organic light-emitting transistor (Fe-OLET) device which integrates the switching capability, light-emitting capability and nonvolatile memory function into a single device is reported. The nonvolatile memory function of Fe-OLET is achieved through the remnant polarization property of ferroelectric polymer, enabling the device to maintain light emission at zero gate bias. The reliable nonvolatile memory operations are also demonstrated. The proof-of-concept device optimized through interfacial modification approach exhibits 20 times improved field-effect mobility and five times increased luminance. The integration of nonvolatile memory, switching and light-emitting capabilities within Fe-OLET provides a promising internal-storage-driving paradigm, thus creating a new pathway for deploying storage capacitor-free circuitry to improve the pixel aperture ratio and the integration density of circuits toward the on-chip advanced display applications.

Ferroelectric Hafnia-Based M3D FeTFTs Annealed at Extremely Low Temperatures and TCAM Cells for Computing-in-Memory Applications.

In order to overcome the bottleneck between the central processor unit and memory as well as the issue of energy consumption, computing-in-memory (CIM) is becoming more popular as an alternative to the traditional von Neumann structure. However, as artificial intelligence advances, the networks require CIM devices to store billions of parameters in order to handle huge data traffic demands. Monolithic three-dimensional (M3D) stacked ferroelectric thin-film transistors (FeTFTs) are one of the promising techniques for realizing high-density CIM devices that can store billions of parameters. In particular, oxide channel-based FeTFTs are well suited for these applications due to low-temperature processes, nonvolatility, and 3D integration capability. Nevertheless, the M3D-integrated CIM devices including hafnia ferroelectric films need the high-temperature annealing process to crystallize the ferroelectric layer, making M3D integration difficult. When the FeTFTs are fabricated with an M3D structure, the high-temperature process causes thermal issues in the underlying devices. Here, we present the focused microwave annealed (FMA) oxide FeTFTs with M3D integration at a low temperature of 250 °C. We confirmed that the FeTFTs with metal-ferroelectric-metal-insulator-semiconductor structure exhibited a large memory window of 3.2 V, good endurance over 106 cycles, and a long retention time of 105 s. To understand the different electrical characteristics of FeTFTs in the top and bottom layers, we experimentally analyzed the density of the state of the oxide channel and ferroelectric properties of the ferroelectric gate insulator by using multifrequency capacitance-voltage measurement and nucleation-limited-switching model analysis, respectively. With our approach, we demonstrate for the first time a vertical stacked FeTFTs-based ternary-content-addressable memory (TCAM) cell for CIM application. We believe that the proposed M3D-stacked TCAM cells composed of FeTFTs can be used in high-density memory, energy-efficient memory, and CIM technology.

Enhanced Switching Reliability of Hf0.5Zr0.5O2 Ferroelectric Films Induced by Interface Engineering.

Ferroelectric materials have been widely researched for applications in memory and energy storage. Among these materials and benefiting from their excellent chemical compatibility with complementary metal-oxide-semiconductor (CMOS) devices, hafnia-based ferroelectric thin films hold great promise for highly scaled semiconductor memories, including nonvolatile ferroelectric capacitors and transistors. However, variation in the switched polarization of this material during field cycling and a limited understanding of the responsible mechanisms have impeded their implementation in technology. Here, we show that ferroelectric Hf0.5Zr0.5O2 (HZO) capacitors that are nearly free of polarization "wake-up"─a gradual increase in switched polarization as a function of the number of switching cycles─can be achieved by introducing ultrathin HfO2 buffer layers at the HZO/electrodes interface. High-resolution transmission electron microscopy (HRTEM) reveals crystallite sizes substantially greater than the film thickness for the buffer layer capacitors, indicating that the presence of the buffer layers influences the crystallization of the film (e.g., a lower ratio of nucleation rate to growth rate) during postdeposition annealing. This evidently promotes the formation of a polar orthorhombic (O) phase in the as-fabricated buffer layer samples. Synchrotron X-ray diffraction (XRD) reveals the conversion of the nonpolar tetragonal (T) phase to the polar orthorhombic (O) phase during electric field cycling in the control (no buffer) devices, consistent with the polarization wake-up observed for these capacitors. The extent of T-O transformation in the nonbuffer samples is directly dependent on the duration over which the field is applied. These results provide insight into the role of the HZO/electrodes interface in the performance of hafnia-based ferroelectrics and the mechanisms driving the polarization wake-up effect.

Non‐Volatile Hybrid Optical Phase Shifter Driven by a Ferroelectric Transistor

AbstractOptical phase shifters are essential elements in photonic integrated circuits (PICs) and function as a direct interface to program the PICs. Non‐volatile phase shifters, which can retain information without a power supply, are highly desirable for low‐power static operations. Here a non‐volatile optical phase shifter is demonstrated by driving a III‐V/Si hybrid metal‐oxide‐semiconductor (MOS) phase shifter with a ferroelectric field‐effect transistor (FeFET) operating in the source follower mode. Owing to the various polarization states in the FeFET, multistate non‐volatile phase shifts up to 1.25π are obtained with CMOS‐compatible operation voltages and low switching energy up to 3.3 nJ. Furthermore, a crossbar array architecture is proposed to simplify the control of non‐volatile phase shifters in large‐scale PICs and verify its feasibility by confirming the selective write‐in operation of a targeted FeFET with a negligible disturbance to the others. This work paves the way for realizing large‐scale non‐volatile programmable PICs for emerging computing applications such as deep learning and quantum computing.

A Piezotronic and Magnetic Dual‐Gated Ferroelectric Semiconductor Transistor

AbstractPiezotronics is the coupling effect of the piezoelectric and semiconductor properties; however, the piezoelectric constant of the piezoelectric semiconductor is relatively small while the ferroelectric materials with large piezoelectric constant typically possess weak semiconductor properties, thus limiting the effective coupling coefficient of the piezotronic materials and devices. Here, a piezotronics and magnetic dual‐gated ferroelectric semiconductor transistor (PM‐FEST) is fabricated by Terfenol‐D, aluminum oxide (Al2O3), and ferroelectric semiconductor α‐In2Se3, which has a large piezoelectric coefficient, room‐temperature ferroelectricity, and dipole locking. The charge carrier transport and corresponding drain current of the PM‐FEST can be directly modulated by either the applied magnetic field or external strain. At a low magnetic field (<200 mT), the maximum current on/off ratio of α‐In2Se3 based PM‐FEST is as high as 1700%. Compared with traditional piezotronic devices, the PM‐FEST demonstrates a higher gauge factor (2.3 × 104) than that of the piezoelectric semiconductors. This work provides a possibility of realizing magnetism‐modulated electronics in semiconductors by exploiting the coupling of piezotronics and magnetostriction.

Neuromorphic Systems: Devices, Architecture, and Algorithms

The application of the structure and principles of the human brain opens up great opportunities for creating artificial systems based on silicon technology. The energy efficiency and performance of a biosimilar architecture can be significantly higher compared to the traditional von Neumann architecture. This paper presents an overview of the most promising artificial neural network (ANN) and spiking neural network (SNN) architectures for biosimilar systems, called neuromorphic systems. Devices for biosimilar systems, such as memristors and ferroelectric transistors, are considered for use as artificial synapses that determine the possibility of creating various architectures of neuromorphic systems; methods and rules for training structures to work correctly when mimicking biological learning rules, such as long-term synaptic plasticity. Problems hindering the implementation of biosimilar systems and examples of architectures that have been practically implemented are discussed.

ADRA: Extending Digital Computing-In-Memory With Asymmetric Dual-Row-Activation

Computing in-memory (CiM) has emerged as an attractive technique to mitigate the von-Neumann bottleneck. Current digital CiM approaches for in-memory operands are based on multi-wordline assertion for computing bit-wise Boolean functions and arithmetic functions such as addition. However, most of these techniques, due to the many-to-one mapping of input vectors to bitline voltages, are limited to CiM of commutative functions, leaving out an important class of computations such as subtraction. In this paper, we propose a CiM approach, which solves the mapping problem through an asymmetric wordline biasing scheme, enabling (a) simultaneous single-cycle memory read and CiM of primitive Boolean functions (b) computation of any Boolean function and (c) CiM of non-commutative functions such as subtraction and comparison. While the proposed technique is technology-agnostic, we show its utility for ferroelectric transistor (FeFET)-based non-volatile memory. Compared to the standard near-memory methods (which require two full memory accesses per operation), we show that our method can achieve a full scale two-operand digital CiM using just one memory access, leading to a 23.2% -72.6% decrease in energy-delay product (EDP).

Fabrication of non-volatile memory transistor by charge compensation of interfacial ionic polarization of a ferroelectric gate dielectric

Lithium niobate (LiNbO3) is a popular lead free perovskite ferroelectric materials, but its implementation as a gate dielectric for developing a ferroelectric thin film transistor (FeTFT) has not been investigated much due to its low band gap. Low band gap introduces high gate leakage current that results in very low retention time of the device. In this report a solution processed Li5AlO4/LiNbO3/Li5AlO4 stacked layer has been used as a gate dielectric of a metal oxide thin film transistor which reduces gate leakage current by four orders of magnitude with respect to the single layer LiNbO3 gate dielectric device. Besides, due to the ionic polarization of Li5AlO4 thin film that originated from the mobile Li+, charge compensation of the depolarization field has been nearly removed. By reducing these factors, it becomes possible to fabricate metal oxide based FeTFT that has retention time of 7 h which is ∼200 times higher with respect to the LiNbO3 only FeTFT. The ratio of On and Off state of FeTFT is ∼103 which retains ∼ 95% after 7 h of operation. The carrier mobility, ON/OFF ratio and subthreshold swing (SS) of this FeTFT are 2.9 cm2 V − 1 s − 1,7.2 × 104 and 328 mV.decade−1 respectively.