Ferroelectric Transistors Research Articles

Low-Power OR Logic Ferroelectric In-Situ Transistor Based on a CuInP2S6/MoS2 Van Der Waals Heterojunction.

Due to the limitations of thermodynamics, the Boltzmann distribution of electrons hinders the further reduction of the power consumption of field-effect transistors. However, with the emergence of ferroelectric materials, this problem is expected to be solved. Herein, we demonstrate an OR logic ferroelectric in-situ transistor based on a CIPS/MoS2 Van der Waals heterojunction. Utilizing the electric field amplification of ferroelectric materials, the CIPS/MoS2 vdW ferroelectric transistor offers an average subthreshold swing (SS) of 52 mV/dec over three orders of magnitude, and a minimum SS of 40 mV/dec, which breaks the Boltzmann limit at room temperature. The dual-gated ferroelectric in-situ transistor exhibits excellent OR logic operation with a supply voltage of less than 1 V. The results indicate that the CIPS/MoS2 vdW ferroelectric transistor has great potential in ultra-low-power applications due to its in-situ construction, steep-slope subthreshold swing and low supply voltage.

Solution‐Processed Dual Gate Ferroelectric–Ferroelectric Organic Polymer Field‐Effect Transistor for the Multibit Nonvolatile Memory

AbstractThe stable multibit storage operation of solution‐processed organic nonvolatile memories (ONVMs) based on ferroelectric field‐effect transistors (FeFETs) for high density data storage devices are demonstrated. The proposed multibit ONVM structure consists of a p‐type polymer semiconductor sandwiched between poly(vinylidene fluoride‐trifluoroethylene) [P(VDF‐TrFE)] layers serving as ferroelectric gate insulators to form a dual gate ferroelectric–ferroelectric memory transistor (DG Fe‐FeMT). With the extra memory space created by the spatially separated ferroelectrics, a 2‐bit memory representation (“11”, “10”, “01” and “00”) with clear memory margins is achieved due to the bistability of each P(VDF‐TrFE) and the high performance of the polymer semiconductor. The distinct four‐level reading of memory output currents (IM,OUTs) results from the independent programming voltages of the dual gates. An excellent distinct six‐levelIM,OUTsare also achieved in DG Fe‐FeMT using the intermediate programming voltages. Finally, the possibility of 3−bit, or 8 memory states, are demonstrated by optimizing the bistability and intermediate polarization states of the ferroelectrics without increasing the device area horizontally. The DG Fe‐FeMT has a great potential for cost−effective flexible nonvolatile multibit data storage devices due to its solution‐process and low annealing temperatures.

Impact of reduced pressure crystallization on ferroelectric properties in hafnium-zirconium dioxide films deposited by sputtering

The impact of reduced pressure annealing on ferroelectric properties in hafnium-zirconium oxide (HZO) films deposited by sputtering has been investigated. It is demonstrated that the HZO films annealed at 600 °C at less than 100 Pa show excellent ferroelectric properties, whereas the HZO films annealed at more than 1000 Pa show degraded electrical properties. This is presumably due to the introduction of oxygen vacancies, which stabilize the ferroelectric orthorhombic phase. Thermal stability can be also improved for the HZO films annealed at reduced pressures. In addition, ferroelectric gate transistor operation is demonstrated using an HZO gate insulator annealed at 100 Pa with the indium-tin-oxide channel.

Out-of-plane and in-plane ferroelectricity of atom-thick two-dimensional InSe

Two-dimensional (2D) ferroelectric materials are promising substitutes of three-dimensional perovskite based ferroelectric ceramic materials. Yet most studies have been focused on the construction of non-centrosymmetric 2D van der Waals materials and only a few are constructed experimentally. Herein, we experimentally demonstrate the co-existence of voltage-tunable out-of-plane (OOP) and in-plane (IP) ferroelectricity in few-layer InSe prepared by a solution-processable method and fabricate ferroelectric semiconductor channel transistors. The reversible polarization can initiate instant switch of resistance with high ON/OFF ratios and a comparable subthreshold swing of 160 mV/dec under gate modulation. The origins of such unique OOP and IP ferroelectricity of the centrosymmetric structure are theoretically analyzed.

Logic and in-memory computing achieved in a single ferroelectric semiconductor transistor

Exploring materials with multiple properties who can endow a simple device with integrated functionalities has attracted enormous attention in the microelectronic field. One reason is the imperious demand for processors with continuously higher performance and totally new architecture. Combining ferroelectric with semiconducting properties is a promising solution. Here, we show that logic, in-memory computing, and optoelectrical logic and non-volatile computing functionalities can be integrated into a single transistor with ferroelectric semiconducting α-In2Se3 as the channel. Two-input AND, OR, and non-volatile NOR and NAND logic operations with current on/off ratios reaching up to five orders, good endurance (1000 operation cycles), and fast operating speed (10 μs) are realized. In addition, optoelectrical OR logic and non-volatile implication (IMP) operations, as well as ternary-input optoelectrical logic and in-memory computing functions are achieved by introducing light as an additional input signal. Our work highlights the potential of integrating complex logic functions and new-type computing into a simple device based on emerging ferroelectric semiconductors.

Ferroelectric HfO2 Memory Transistors With High-κ Interfacial Layer and Write Endurance Exceeding 1010 Cycles

We demonstrate ferroelectric (FE) memory transistors on a crystalline silicon channel with endurance exceeding 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">10</sup> cycles. The ferroelectric transistors (FeFETs) incorporate a high- κ interfacial layer (IL) of thermally grown silicon nitride (SiN <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">x</sub> ) and a thin 4.5 nm layer of Zr-doped FE-HfO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> (HZO) on a ~30 nm silicon on insulator (SOI) channel. The device shows a ~1V memory window (MW) in a DC sweep of just ± 2.5V, and can be programmed and erased with voltage pulses of V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> G</sub> = ± 3V at a pulse width of 250 ns. The device also shows very good retention behavior. These results indicate that appropriate engineering of the IL layer could substantially improve FeFET device performance and reliability.

Nanoscale channel organic ferroelectric synaptic transistor array for high recognition accuracy neuromorphic computing

Benefiting from solution processability, material diversity and biocompatibility properties of organic semiconductors, organic synaptic transistor is a promising alternative to execute neuromorphic computing. Unfortunately, conventional planner organic synaptic transistors suffer from poor analog weight update and fault tolerance, which limits the pattern recognition accuracy of organic neuromorphic system. Herein, a scalable and reconfigurable nanoscale channel organic ferroelectric synaptic transistor array (NOFST) is firstly demonstrated. Different from planner synaptic devices whose synaptic properties mostly rely on manipulating carrier densities, the operation mechanism of NOFST is associated with the virtual contact formation of pseudo-conductive channel and polarization tuned distribution of carriers, which manipulates the injection of carries into semiconductor. Hence, benefiting from the nanoscale channel length and the above unique operation mechanism, NOFST exhibits excellent gate control ability contributing to the improvement of fault tolerance and weight update properties. Finally, the neuromorphic system built from NOFST achieves 91.38% recognition accuracy of handwriting digit, which is record high for organic field-effect synaptic transistors. The special device structure is wildly applicable for other organic semiconductor materials, providing a new pathway for developing organic neuromorphic hardware systems with high recognition accuracy.

Ferroelectric Synaptic Transistor Network for Associative Memory

AbstractBrain‐inspired associative memory is meaningful for pattern recognitions and image/speech processing. Here, a ferroelectric synaptic transistor network is proposed that is capable of associative learning and one‐step recalling of a whole set of data from only partial information. The competition between an external field and the internal depolarization field governs the ferroelectric creep of domain walls and offers each single ferroelectric synapse a full and subfemtojoule‐energy‐cost Hebbian synaptic plasticity, including short‐term memory (STM) to long‐term memory (LTM) transition, and remarkably both spike‐timing‐dependent plasticity (STDP) and spike‐rate‐dependent plasticity (SRDP). Assisted by the third terminal to control the ferroelectric domain dynamics, self‐adaptive coupling between neurons is realized by updating synaptic weight concurrently. Pavlov's dog experiment and multiassociative memories are demonstrated in this ferroelectric synaptic transistor network. Such ferroelectric synaptic transistor network is available for building multilayer neural networks and provides new avenues for associative‐memory information processing.

Enhancement of the Retention Characteristics in Solution-Processed Ferroelectric Memory Transistor with Dual-Gate Structure.

We demonstrated the enhancement of the retention characteristics in solution-processed ferroelectric memory transistors. For enhanced retention characteristics, solution-processed Indium Gallium Zinc Oxide (InGaZnO) semiconductor is used as an active layer in a dual-gate structure to achieve high memory on-current and low memory off-current respectively. In our dual-gate oxide ferroelectric thin-film transistor (DG Ox-FeTFT), while conventional TFT characteristic is observed during bottom-gate sweeping, large hysteresis is exhibited during top-gate sweeping with high memory on-current due to the high mobility of the InGaZnO. The voltage applied to the counter bottom-gate electrode causes variations in the turn-on voltage position, which controlled the memory on- and off-current in retention characteristics. Specifically, due to the full depletion of semiconductor by the high negative counter gate bias, the memory off-current in reading operation is dramatically reduced by 10⁴. The application of a high negative counter field to the dual-gate solution-processed ferroelectric memory gives a high memory on- and off-current ratio useful for the production of high performance multi-bit memory devices.

Van der Waals engineering of ferroelectric heterostructures for long-retention memory

The limited memory retention for a ferroelectric field-effect transistor has prevented the commercialization of its nonvolatile memory potential using the commercially available ferroelectrics. Here, we show a long-retention ferroelectric transistor memory cell featuring a metal-ferroelectric-metal-insulator-semiconductor architecture built from all van der Waals single crystals. Our device exhibits 17 mV dec−1 operation, a memory window larger than 3.8 V, and program/erase ratio greater than 107. Thanks to the trap-free interfaces and the minimized depolarization effects via van der Waals engineering, more than 104 cycles endurance, a 10-year memory retention and sub-5 μs program/erase speed are achieved. A single pulse as short as 100 ns is enough for polarization reversal, and a 4-bit/cell operation of a van der Waals ferroelectric transistor is demonstrated under a 100 ns pulse train. These device characteristics suggest that van der Waals engineering is a promising direction to improve ferroelectronic memory performance and reliability for future applications.

Analysis of Edge Effect Occurring in Non-Volatile Ferroelectric Transistors

This study focuses on the interaction between the oxide layer area of a transistor and its ferroelectric layer area. An experimental comparison of transistor oxide layer area demonstrates that the larger the ratio of oxide to ferroelectric layers, the larger the on/off ratio, thus improving performance. A subsequent experiment aimed to further demonstrate this in different sized devices, and changing the ratio of $\text{A}_{\text {HZO}}/\text{A}_{\text {SiO2}}$ (the area of HfZrOx divided by oxide layer) showed the same tendency as above, but also produced an unexpected finding in that a comparison of on/off ratio exhibits an abnormal electric characteristic. This study discusses this abnormal electric characteristic and proposes an explanatory physical model.

High-performance polymer semiconductor-based ferroelectric transistor nonvolatile memory with a self-organized ferroelectric/dielectric gate insulator

Ferroelectric organic field-effect transistor nonvolatile memories (Fe-OFET-NVMs) offer attractive features for future memory applications, such as flexible and wearable electronics. Polymer semiconductor-based top-gate Fe-OFET-NVMs possess natural advantages in the device structure and processing manufacturing, compared to small-molecule semiconductor-based bottom-gate Fe-OFET-NVMs. However, their performances, such as mobility and operating voltages, should be further improved to be comparable to those of the latter. In this Letter, we develop a route to achieve high-performance top-gate Fe-OFET-NVMs, by employing a polymer semiconductor channel and self-organized ferroelectric/dielectric gate insulators, which were processed by a solution spin-coating technique. The optimal Fe-OFET-NVM exhibits a high mobility of 1.96 cm2/V s on average, a reliable endurance over 400 cycles, a stable retention capability over 6 × 104 s, and a life more than one year. Furthermore, the operating voltage of the Fe-OFET-NVM is reduced to ±20 V by scaling down the thickness of the ferroelectric/dielectric gate insulator. The whole performances of our memories are comparable to or better than those of the previous Fe-OFET-NVMs.

Oxide semiconductor-based ferroelectric thin-film transistors for advanced neuromorphic computing

Neuromorphic computing that mimics the biological brain has been demonstrated as a next-generation computing method due to its low power consumption and parallel data processing characteristics. To realize neuromorphic computing, diverse neural networks such as deep neural networks (DNNs) and spiking neural networks (SNNs) have been introduced. DNNs require artificial synapses that have analog conductance modulation characteristics, whereas SNNs require artificial synapses that have conductance modulation characteristics controlled by temporal relationships between signals, so the development of a multifunctional artificial synapse is required. In this work, we report a ferroelectric thin-film transistor (FeTFT) that uses zirconium-doped hafnia (HfZrOx) and indium zinc tin oxide (IZTO) for neuromorphic applications. With reliable conductance modulation characteristics, we suggest that the FeTFT with HfZrOx and IZTO can be used as an artificial synapse for both DNNs and SNNs. The linear and symmetric conductance modulation characteristics in FeTFTs result in high recognition accuracy (93.1%) of hand-written images, which is close to the accuracy (94.1%) of an ideal neural network. Also, we show that the FeTFTs can emulate diverse forms of spike-time-dependent plasticity, which is an important learning rule for SNNs. These results suggest that FeTFT is a promising candidate to realize neuromorphic computing hardware.

Indium oxide and indium-tin-oxide channel ferroelectric gate thin film transistors with yttrium doped hafnium-zirconium dioxide gate insulator prepared by chemical solution process

Ferroelectric gate transistor (FGT) with yttrium doped hafnium-zirconium dioxide (Y-HZO) gate insulator and oxide channel with various thicknesses of In2O3 and ITO were fabricated by chemical solution deposition. First, ferroelectric properties of Y-HZO in the metal-ferroelectric-semiconductor structure with 5–22 nm thick In2O3 and 6–24 nm thick ITO, have been confirmed by polarization–voltage and capacitance–voltage (C–V) characteristics. The C–V curves showed clear butterfly loops showing the depletion of In2O3 and ITO layer. Secondly, the device performance of FGTs has been evaluated with various thicknesses of In2O3 and ITO channel layer. The fabricated FGTs exhibited typical n-channel transistor operation with a counterclockwise hysteresis loop due to the ferroelectric nature of the Y-HZO-gate insulator. It was found that FGT shows a low subthreshold voltage swing, high on/off drain current ratio of 106, large on current, and memory window.

Two-dimensional ferroelectric channel transistors integrating ultra-fast memory and neural computing

With the advent of the big data era, applications are more data-centric and energy efficiency issues caused by frequent data interactions, due to the physical separation of memory and computing, will become increasingly severe. Emerging technologies have been proposed to perform analog computing with memory to address the dilemma. Ferroelectric memory has become a promising technology due to field-driven fast switching and non-destructive readout, but endurance and miniaturization are limited. Here, we demonstrate the α-In2Se3 ferroelectric semiconductor channel device that integrates non-volatile memory and neural computation functions. Remarkable performance includes ultra-fast write speed of 40 ns, improved endurance through the internal electric field, flexible adjustment of neural plasticity, ultra-low energy consumption of 234/40 fJ per event for excitation/inhibition, and thermally modulated 94.74% high-precision iris recognition classification simulation. This prototypical demonstration lays the foundation for an integrated memory computing system with high density and energy efficiency.

Ferroelectric transistors with asymmetric double gate for memory window exceeding 12 V and disturb-free read.

Ferroelectric field-effect transistors (FeFETs) with a single gate structure and using the newly discovered ferroelectric hafnium oxide as an active material are attracting considerable interest for nonvolatile memory devices. However, such FeFETs struggle to achieve a large separation between the two logic states (memory window, MW) because of the thickness limitations of the ferroelectric film. Moreover, they are affected by detrimental disturbs coming from the read operation because of the shared write and read paths. Therefore, significant performance improvements are needed for the device to compete with established memory technologies like flash. Here, we present an asymmetric double-gate FeFET structure, where only one gate stack comprises the ferroelectric layer. We propose a novel read operation at the non-ferroelectric gate and demonstrate an amplified MW exceeding 12 V thanks to the enhanced body effect factor and the increased sensitivity of the transfer characteristics to the ferroelectric polarization. As a result, the above physical limitation is circumvented, thus by far outperforming the MW values reported in the literature. Based on this, we implement the multi-level cell storage featuring 4 bits per cell and stable data retention. Finally, an essential benefit originating from the separated write and read paths in our structure is exploited to demonstrate the fully disturb-free read operation. Besides memory, this could be particularly favorable for those neuromorphic and in-memory computing concepts with an occasional update of the stored variable but a very frequent read.

Suppression of short channel effects in ferroelectric Si junctionless transistors with a sub-10 nm gate length defined by helium ion beam lithography

Short channel effects in Si junctionless transistors with a gate length below 10 nm are reduced by the ferroelectric Hf0.5Zr0.5O2gate oxide.

A Ferroelectric Thin-Film Transistor Based on Sputtered HfZrO and IGZO

In recent years, because of increased demand in IoTs devices, wearable displays, circuits, sensors, and other high technology devices, the thin film transistors (TFTs) gated by ferroelectric film as memory devices are of considerable interest. Ferroelectric (FE) materials including Pb(Zr0.4Ti0.6)O3 (PZT), (1-x)[Pb(Mg1/3Nb2/3)O3]-x[PbTiO3] (PMN-PT), and polymer poly (vinylidenefluoride-trifluoroethylene) (P[VDF-TrFE]) have been used to realize ferroelectric transistors with nonvolatile memory. Particularly, HfO2-based materials have attracted a great deal of attention since the breakthrough in the ferroelectricity of Si-doped HfO2, which can overcome some of limitations of current ferroelectrics such as scalability, lead-free materials and suitable for high-temperature process. Moreover, HfO2-based materials exhibit better performance in terms of a switching characteristic than low-k gate insulator (SiO2) as well as high-k materials.In this study, the performance of sputter-deposited ferroelectric hafnium zirconium oxide (HfZrO)/high-k HfO2 gate dielectric for a-IGZO TFTs on glass substrates was investigated. The sputterd HfZrO film was crystallized with orthorhombic phases after rapid-thermal-annealing at temperature of 400 °C for 30 min in air and exhibited ferroelectricity. The performance of the FE-TFT based on HfZrO/HfO₂ (15 nm/185 nm) was compared to typical TFTs fabricated with PECVD-SiO₂ (200 nm) and sputtered HfO₂ only (200 nm) gate insulators. The transfer characteristics of the FE-TFTs were demonstrated with low operating voltage of 0.1 V, one order higher on-off ratio and drain current than the typical TFTs with the SiO₂ and HfO₂ gates, high field effect mobility 5.04 cm2V-1s-1 and small subthreshold slope (SS) about 117 mV/dec. The low operating voltage and small SS results of the HfZrO/HfO₂-based device indicates that the use of the HfZrO/HfO₂ could serve as a potential gate for the fabrication of high-performance FE-TFTs.

(Invited) Ferroelectric Transistors for Synaptic Devices: Challenges and Prospects

Ferroelectric device based on HfZrOx (HZO) is an emerging non-volatile memory that is able to store multi-level weights of the deep neural network (DNN) models and enables the compute-in-memory paradigm. In this presentation, we will present our recent progresses in HZO based ferroelectric transistor (FeFET) design for inference as well as in-situ training. Hybrid synapse bit cell design, drain-erase scheme for 3D NAND array, and physical insights into minor loop history effect will be discussed and validated with 22nm/28nm FeFET experimental data. Then we will present our DNN+NeuroSim benchmark framework to evaluate the pros and cons of the FeFET technology for accelerating large-scale DNN models.

A memory window expression to evaluate the endurance of ferroelectric FETs

The recent discovery of ferroelectricity in HfO2 has revived the interest into non-volatile memories based on ferroelectric transistors (FeFETs). The key advantages of these FeFETs include the low power consumption and the compatibility with the existing CMOS process. On the other hand, issues related mainly to endurance still represent a challenge to the development of the technology. In this Letter, we propose to exploit an analytical expression for the Memory Window (MW) as a simple yet effective characterization tool to evaluate the endurance of FeFETs. The MW is defined as the difference between threshold voltages occurring due to polarization switching. The analytical formulation of the MW allows one to quickly estimate the generated trap concentration as a function of number of writing cycles (or time) without recurring to numerical simulations. With the aid of the analytical model, we find that for typical program/erase pulse amplitudes and duration, endurance has a weak dependence on writing conditions. The characterization technique based on the MW would allow the systematic comparison of the performance and endurance of next-generation FeFETs.