Ferroelectric-gate Field-effect Transistors Research Articles

Ultralow-power non-volatile memory cells based on P(VDF-TrFE) ferroelectric-gate CMOS silicon nanowire channel field-effect transistors.

Nanowire-based ferroelectric-complementary metal-oxide-semiconductor (NW FeCMOS) nonvolatile memory devices were successfully fabricated by utilizing single n- and p-type Si nanowire ferroelectric-gate field effect transistors (NW FeFETs) as individual memory cells. In addition to having the advantages of single channel n- and p-type Si NW FeFET memory, Si NW FeCMOS memory devices exhibit a direct readout voltage and ultralow power consumption. The reading state power consumption of this device is less than 0.1 pW, which is more than 10(5) times lower than the ON-state power consumption of single-channel ferroelectric memory. This result implies that Si NW FeCMOS memory devices are well suited for use in non-volatile memory chips in modern portable electronic devices, especially where low power consumption is critical for energy conservation and long-term use.

Novel process for widening memory window of sub-200 nm ferroelectric-gate field-effect transistor by ferroelectric coating the gate-stack sidewall

Ferroelectric-gate field-effect transistors (FeFETs) with metallurgical-gate lengths of 140 nm, 160 nm and 190 nm were successfully fabricated using a novel fabrication process. The gate stacks of the FeFETs were Pt/Sr0.8Ca0.2Bi2Ta2O9(SCBT)/HfO2/Si. Key to the process was covering the as-etched gate-stack sidewalls with SCBT precursor films and annealing altogether. The FeFETs which underwent the novel process showed larger memory windows than those without the process by about 0.5 V at scanned gate-voltages of 1 ± 5 V. Endurances of the FeFETs made by the novel process were measured up to 109 cycles with good separations of the on- and off-states. The endurance pulses were 1 ± 5 V with 2 μs period. Good data-retentions of them were also demonstrated which were measured for at least 6.5 days.

Low-Programmable-Voltage Nonvolatile Memory Devices Based on Omega-shaped Gate Organic Ferroelectric P(VDF-TrFE) Field Effect Transistors Using p-type Silicon Nanowire Channels.

A facile approach was demonstrated for fabricating high-performance nonvolatile memory devices based on ferroelectric-gate field effect transistors using a p-type Si nanowire coated with omega-shaped gate organic ferroelectric poly(vinylidene fluoride-trifluoroethylene) (P(VDF-TrFE)). We overcame the interfacial layer problem by incorporating P(VDF-TrFE) as a ferroelectric gate using a low-temperature fabrication process. Our memory devices exhibited excellent memory characteristics with a low programming voltage of ±5 V, a large modulation in channel conductance between ON and OFF states exceeding 105, a long retention time greater than 3 × 104 s, and a high endurance of over 105 programming cycles while maintaining an ION/IOFF ratio higher than 102.

Multi-channel ferroelectric-gate field effect transistors with excellent performance based on ZnO nanofibers

Bottom-gate multi-channel ferroelectric-gate field effect transistors (FETs) based on ZnO nanofibers were fabricated, using Bi3.15Nd0.85Ti3O12 (BNT) thin film as the gate insulator and ZnO nanofibers as the semiconductor multi-channel. The electrical characteristics of the multi-channel ZnO nanofiber ferroelectric-gate FETs showed typical p-channel transistor properties with a low threshold voltage of −0.5 V, a high effective field effect mobility, and a large on/off current ratio of 104. These excellent performances are attributed to the multi-channel ZnO nanofiber and BNT ferroelectric-gate insulator.

Thin reduced graphene oxide interlayer with a conjugated block copolymer for high performance non-volatile ferroelectric polymer memory

Polymer ferroelectric-gate field effect transistors (Fe-FETs) employing ferroelectric polymer thin films as gate insulators are highly attractive as a next-generation non-volatile memory. For minimizing gate leakage current of a device which arises from electrically defective ferroelectric polymer layer in particular at low operation voltage, the materials design of interlayers between the ferroelectric insulator and gate electrode is essential. Here, we introduce a new solution-processed interlayer of conductive reduced graphene oxides (rGOs) modified with a conjugated block copolymer, poly(styrene-block-paraphenylene) (PS-b-PPP). A FeFET with a solution-processed p-type oligomeric semiconducting channel and ferroelectric poly(vinylidene fluoride-co-trifluoroethylene) (PVDF-TrFE) insulator exhibited characteristic source–drain current hysteresis arising from ferroelectric polarization switching of a PVDF-TrFE insulator. Our PS-b-PPP modified rGOs (PMrGOs) with conductive moieties embedded in insulating polymer matrix not only significantly reduced the gate leakage current but also efficiently lowered operation voltage of the device. In consequence, the device showed large memory gate voltage window and high ON/OFF source–drain current ratio with excellent data retention and read/write cycle endurance. Furthermore, our PMrGOs interlayers were successfully employed to FeFETs fabricated on mechanically flexible substrates with promising non-volatile memory performance under repetitive bending deformation.

Formation of solution-processed multistacked ferroelectric layers for performance improvement of ferroelectric-gated pentacene field-effect transistors

In solution-processes, the formation of multistacked layers (MSLs) is difficult because of natural dissolution and/or damage to the underlying film by the solvent used for the upper film. To form MSLs in solution-processes, using orthogonal solvents for each layer is a representative remedy. As the number of MSLs increases, the selection of appropriate solvents for every layer becomes harder. In this work, we report a viable method to form MSLs, even when using one material for the entire solution-process. We present that solution-processed MSLs can be formed by tuning the solubility by mixing an orthogonal solvent. We fabricated ferroelectric MSLs using a ferroelectric polymer and applied the MSLs into a ferroelectric-gated field-effect transistor. We obtained improvements in electrical properties such as current on/off ratio, subthreshold swing, and mobility in transistors with MSLs, in comparison to the single layer case.

Tunable threshold voltage of an n-type Si nanowire ferroelectric-gate field effect transistor for high-performance nonvolatile memory applications

We successfully fabricated ferroelectric-gate field effect transistor (FEFET)-based nonvolatile memory devices using an n-type Si nanowire coated with omega-shaped-gate organic ferroelectric poly(vinylidene fluoride-trifluoroethylene) via a low-temperature fabrication process. Our FEFET memory devices with controllable threshold voltage via adjustment of the doping concentration exhibit excellent memory characteristics with ultra-low ON state power dissipation (≦̸3 nW), a large modulation in channel conductance between the ON and OFF states exceeding 105, a long retention time of over 3 × 104 s and a high endurance of over 105 programming cycles whilst maintaining an ION/IOFF ratio higher than 103. This result may be promising for next-generation nonvolatile memory on flexible substrate applications.

Non‐Volatile Ferroelectric Memory with Position‐Addressable Polymer Semiconducting Nanowire

One-dimensional nanowires (NWs) have been extensively examined for numerous potential nano-electronic device applications such as transistors, sensors, memories, and photodetectors. The ferroelectric-gate field effect transistors (Fe-FETs) with semiconducting NWs in particular in combination with ferroelectric polymers as gate insulating layers have attracted great attention because of their potential in high density memory integration. However, most of the devices still suffer from low yield of devices mainly due to the ill-control of the location of NWs on a substrate. NWs randomly deposited on a substrate from solution-dispersed droplet made it extremely difficult to fabricate arrays of NW Fe-FETs. Moreover, rigid inorganic NWs were rarely applicable for flexible non-volatile memories. Here, we present the NW Fe-FETs with position-addressable polymer semiconducting NWs. Polymer NWs precisely controlled in both location and number between source and drain electrode were achieved by direct electrohydrodynamic NW printing. The polymer NW Fe-FETs with a ferroelectric poly(vinylidene fluoride-co-trifluoroethylene) exhibited non-volatile ON/OFF current margin at zero gate voltage of approximately 10(2) with time-dependent data retention and read/write endurance of more than 10(4) seconds and 10(2) cycles, respectively. Furthermore, our device showed characteristic bistable current hysteresis curves when being deformed with various bending radii and multiple bending cycles over 1000 times.

Organic ferroelectric gate field-effect transistor memory using high-mobility rubrene thin film

An organic ferroelectric gate field-effect transistor (FET) memory has been fabricated using an organic semiconductor of rubrene thin film with a high mobility and a gate insulating layer of poly(vinylidene fluoride–tetrafluoroethylene) [P(VDF–TeFE)] thin film. A rubrene thin-film sheet was grown by physical vapor transport (PVT), and placed onto a spin-coated P(VDF–TeFE) thin-film layer, and Au source and drain electrodes were formed on this rubrene thin film. A hysteresis loop of the drain current–gate voltage (ID–VG) characteristic has been clearly observed in the ferroelectric gate FET, and is caused by the ferroelectricity. The maximum drain current is 1.5 × 10−6 A, which is about two orders of magnitude larger than that of the P(VDF–TeFE) gate FET using a pentacene thin film. Moreover, the mobility of this organic ferroelectric gate FET using rubrene thin film is 0.71 cm2 V−1 s−1, which is 35 times larger than that of the FET with pentacene thin film.

Single event effect in a ferroelectric-gate field-effect transistor under heavy-ion irradiation

The single event effect in ferroelectric-gate field-effect transistor (FeFET) under heavy ion irradiation is investigated in this paper. The simulation results show that the transient responses are much lower in a FeFET than in a conventional metal–oxide–semiconductor field-effect transistor (MOSFET) when the ion strikes the channel. The main reason is that the polarization-induced charges (the polarization direction here is away from the silicon surface) bring a negative surface potential which will affect the distribution of carriers and charge collection in different electrodes significantly. The simulation results are expected to explain that the FeFET has a relatively good immunity to single event effect.

Wafer-Scale Arrays of Nonvolatile Polymer Memories with Microprinted Semiconducting Small Molecule/Polymer Blends

Nonvolatile ferroelectric-gate field-effect transistors (Fe-FETs) memories with solution-processed ferroelectric polymers are of great interest because of their potential for use in low-cost flexible devices. In particular, the development of a process for patterning high-performance semiconducting channel layers with mechanical flexibility is essential not only for proper cell-to-cell isolation but also for arrays of flexible nonvolatile memories. We demonstrate a robust route for printing large-scale micropatterns of solution-processed semiconducting small molecules/insulating polymer blends for high performance arrays of nonvolatile ferroelectric polymer memory. The nonvolatile memory devices are based on top-gate/bottom-contact Fe-FET with ferroelectric polymer insulator and micropatterned semiconducting blend channels. Printed micropatterns of a thin blended semiconducting film were achieved by our selective contact evaporation printing, with which semiconducting small molecules in contact with a micropatterned elastomeric poly(dimethylsiloxane) (PDMS) mold were preferentially evaporated and absorbed into the PDMS mold while insulating polymer remained intact. Well-defined micrometer-scale patterns with various shapes and dimensions were readily developed over a very large area on a 4 in. wafer, allowing for fabrication of large-scale printed arrays of Fe-FETs with highly uniform device performance. We statistically analyzed the memory properties of Fe-FETs, including ON/OFF ratio, operation voltage, retention, and endurance, as a function of the micropattern dimensions of the semiconducting films. Furthermore, roll-up memory arrays were produced by successfully detaching large-area Fe-FETs printed on a flexible substrate with a transient adhesive layer from a hard substrate and subsequently transferring them to a nonplanar surface.

High Performance Multi‐Level Non‐Volatile Polymer Memory with Solution‐Blended Ferroelectric Polymer/High‐k Insulators for Low Voltage Operation

AbstractPolymer ferroelectric‐gate field effect transistors (Fe‐FETs) employing ferroelectric polymer thin films as gate insulators are highly attractive as a next‐generation non‐volatile memory. Furthermore, polymer Fe‐FETs have been recently of interest owing to their capability of storing data in more than 2 states in a single device, that is, they have multi‐level cell (MLC) operation potential for high density data storage. However, among a variety of technological issues of MLC polymer Fe‐FETs, the requirement of high voltage for cell operation is one of the most urgent problems. Here, a low voltage operating MLC polymer Fe‐FET memory with a high dielectric constant (k) ferroelectric polymer insulator is presented. Effective enhancement of capacitance of the ferroelectric gate insulator layer is achieved by a simple binary solution‐blend of a ferroelectric poly(vinylidene fluoride‐co‐trifluoroethylene) (PVDF‐TrFE) (k ≈ 8) with a relaxer high‐k poly(vinylidene‐fluoride–trifluoroethylene–chlorotrifluoroethylene) (PVDF‐TrFE‐CTFE) (k ≈ 18). At optimized conditions, a ferroelectric insulator with a PVDF‐TrFE/PVDF‐TrFE‐CTFE (10/5) blend composition enables the discrete six‐level multi‐state operation of a MLC Fe‐FET at a gate voltage sweep of ±18 V with excellent data retention and endurance of each state of more than 104 s and 120 cycles, respectively.

Electrical properties of CaxSr1−xBi2Ta2O9 ferroelectric-gate field-effect transistors

Pt/CaxSr1−xBi2Ta2O9(CSBT)/Hf-Al-O(HAO)/Si ferroelectric-gate field-effect transistors (FeFETs) with x = 0, 0.1, 0.2, 0.5 and 1 were fabricated and characterized. As-deposited layer thicknesses of the CSBT and HAO were fixed at 200 nm and 7 nm. The memory window (Vw) values of the FeFETs with the CSBTs of x = 0, 0.1, 0.2 and 0.5 were 0.75 V, 0.89 V, 0.84 V and 0.43 V, respectively, when the gate voltage Vg was scanned from −4 to 6 V. The Vw values of the FeFETs with x = 0.1 and 0.2 were 19% and 12% larger than those of the FeFET with pure SrBi2Ta2O9 (x = 0). The Vw of the FeFET with pure CaBi2Ta2O9 (x = 1) was almost zero. The Bi-layered perovskite crystalline structure of the CSBTs in the Pt/CSBT/HAO/Si stacks was confirmed by x-ray diffraction pattern characterization. The FeFETs with the CSBTs of x = 0.1 and 0.2 showed good retention characteristics measured for at least 4.6 days and high endurance performance over 108 cycles.

Dynamic Observation of Brain-Like Learning in a Ferroelectric Synapse Device

A brain-like learning function was implemented in an electronic synapse device using a ferroelectric-gate field effect transistor (FeFET). The FeFET was a bottom-gate type FET with a ZnO channel and a ferroelectric Pb(Zr,Ti)O3 (PZT) gate insulator. The synaptic weight, which is represented by the channel conductance of the FeFET, is updated by applying a gate voltage through a change in the ferroelectric polarization in the PZT. A learning function based on the symmetric spike-timing dependent synaptic plasticity was implemented in the synapse device using the multilevel weight update by applying a pulse gate voltage. The dynamic weighting and learning behavior in the synapse device was observed as a change in the membrane potential in a spiking neuron circuit.

GIZO/P(VDF-TrFE) based dual-channel ferroelectric-gate fieldeffect transistor: influence on memory retention and switching mechanisms

GIZO/P(VDF-TrFE) based dual-channel ferroelectric-gate fieldeffect transistor: influence on memory retention and switching mechanisms

Effect of Ferroelectric Polarization on Carrier Transport in Controlled Polarization-Type Ferroelectric Gate Field-Effect Transistors with Poly(vinylidene fluoride–tetrafluoroethylene)/ZnO Heterostructure

The carrier transport properties of ferroelectric gate field-effect transistors composed of oxide polar semiconductors, ZnO, and organic ferroelectrics, poly(vinylidene fluoride–tetrafluoroethylene) [P(VDF–TeFE)], were investigated. The P(VDF–TeFE)/ZnO heterostructure with a 100-nm-thick channel shows a large ON/OFF ratio of 105 in the drain current while that with a channel thickness of 500 nm shows small changes. To clarify the effect of ferroelectric polarization on the carrier transport properties, Hall effect measurement was carried out after poling treatment. Although the Hall mobility for the channel thickness of 500 nm shows no dependence on the poling voltage, that for the channel thickness of 100 nm increases with increasing poling voltage. The temperature dependence of the carrier transport properties indicates that the Hall mobility for the channel thickness of 100 nm increases when the carriers are accumulated at the interface between P(VDF–TeFE) and ZnO, especially below 200 K. The results suggest that the reduction in ionized impurity scattering, which originates from the carrier accumulation due to ferroelectric polarization, increases the mobility.

Effect of Ferroelectric Polarization on Carrier Transport in Controlled Polarization-Type Ferroelectric Gate Field-Effect Transistors with Poly(vinylidene fluoride–tetrafluoroethylene)/ZnO Heterostructure

The carrier transport properties of ferroelectric gate field-effect transistors composed of oxide polar semiconductors, ZnO, and organic ferroelectrics, poly(vinylidene fluoride–tetrafluoroethylene) [P(VDF–TeFE)], were investigated. The P(VDF–TeFE)/ZnO heterostructure with a 100-nm-thick channel shows a large ON/OFF ratio of 105 in the drain current while that with a channel thickness of 500 nm shows small changes. To clarify the effect of ferroelectric polarization on the carrier transport properties, Hall effect measurement was carried out after poling treatment. Although the Hall mobility for the channel thickness of 500 nm shows no dependence on the poling voltage, that for the channel thickness of 100 nm increases with increasing poling voltage. The temperature dependence of the carrier transport properties indicates that the Hall mobility for the channel thickness of 100 nm increases when the carriers are accumulated at the interface between P(VDF–TeFE) and ZnO, especially below 200 K. The results suggest that the reduction in ionized impurity scattering, which originates from the carrier accumulation due to ferroelectric polarization, increases the mobility.

Ferroelectric Random Access Memories

Ferroelectric random access memory (FeRAM) is a nonvolatile memory, in which data are stored using hysteretic P-E (polarization vs. electric field) characteristics in a ferroelectric film. In this review, history and characteristics of FeRAMs are first introduced. It is described that there are two types of FeRAMs, capacitor-type and FET-type, and that only the capacitor-type FeRAM is now commercially available. In chapter 2, properties of ferroelectric films are discussed from a viewpoint of FeRAM application, in which particular attention is paid to those of Pb(Zr,Ti)O3, SrBi2Ta2O9, and BiFeO3. Then, cell structures and operation principle of the capacitor-type FeRAMs are discussed in chapter 3. It is described that the stacked technology of ferroelectric capacitors and development of new materials with large remanent polarization are important for fabricating high-density memories. Finally, in chapter 4, the optimized gate structure in ferroelectric-gate field-effect transistors is discussed and experimental results showing excellent data retention characteristics are presented.

Simple Synthesis of Palladium Nanoparticles, β-Phase Formation, and the Control of Chain and Dipole Orientations in Palladium-Doped Poly(vinylidene fluoride) Thin Films

Palladium nanoparticles (Pd-NP's) are prepared by a simple one-step procedure when poly(vinylidene fluoride) (PVDF) is used as a polymer stabilizer. High-quality Pd-NP-doped PVDF thin films are fabricated where the heat-controlled spin-coating technique is adopted. The effect of Pd-NP's on the crystal modifications and lamellae orientation in PVDF films is investigated using Fourier transform infrared-grazing incidence reflection absorption spectroscopy. The electroactive β phase and edge-on crystalline lamellae are found to be formed preferentially in Pd-NP-doped PVDF films. As a result, Pd-NP-doped PVDF ultrathin films gave a very good discernible contrast between the written and erased data bits, which suggests that they can be used as a scanning-probe-microscopy-based ferroelectric memory device or a ferroelectric gate field-effect transistor memory device in the future.

Three-terminal ferroelectric synapse device with concurrent learning function for artificial neural networks

Spike-timing-dependent synaptic plasticity (STDP) is demonstrated in a synapse device based on a ferroelectric-gate field-effect transistor (FeFET). STDP is a key of the learning functions observed in human brains, where the synaptic weight changes only depending on the spike timing of the pre- and post-neurons. The FeFET is composed of the stacked oxide materials with ZnO/Pr(Zr,Ti)O3 (PZT)/SrRuO3. In the FeFET, the channel conductance can be altered depending on the density of electrons induced by the polarization of PZT film, which can be controlled by applying the gate voltage in a non-volatile manner. Applying a pulse gate voltage enables the multi-valued modulation of the conductance, which is expected to be caused by a change in PZT polarization. This variation depends on the height and the duration of the pulse gate voltage. Utilizing these characteristics, symmetric and asymmetric STDP learning functions are successfully implemented in the FeFET-based synapse device by applying the non-linear pulse gate voltage generated from a set of two pulses in a sampling circuit, in which the two pulses correspond to the spikes from the pre- and post-neurons. The three-terminal structure of the synapse device enables the concurrent learning, in which the weight update can be performed without canceling signal transmission among neurons, while the neural networks using the previously reported two-terminal synapse devices need to stop signal transmission for learning.