Ferroelectric-gate Transistors Research Articles

Impact of reduced pressure crystallization on ferroelectric properties in hafnium-zirconium dioxide films deposited by sputtering

The impact of reduced pressure annealing on ferroelectric properties in hafnium-zirconium oxide (HZO) films deposited by sputtering has been investigated. It is demonstrated that the HZO films annealed at 600 °C at less than 100 Pa show excellent ferroelectric properties, whereas the HZO films annealed at more than 1000 Pa show degraded electrical properties. This is presumably due to the introduction of oxygen vacancies, which stabilize the ferroelectric orthorhombic phase. Thermal stability can be also improved for the HZO films annealed at reduced pressures. In addition, ferroelectric gate transistor operation is demonstrated using an HZO gate insulator annealed at 100 Pa with the indium-tin-oxide channel.

Thermal stability of ferroelectricity in hafnium–zirconium dioxide films deposited by sputtering and chemical solution deposition for oxide-channel ferroelectric-gate transistor applications

Stability of ferroelectricity in hafnium–zirconium oxide (HZO) films deposited by sputtering and chemical solution deposition (CSD) has been investigated. After confirming the ferroelectricity of both sputtered HZO and CSD yttrium-doped HZO (Y-HZO) films, indium-tin-oxide (ITO) was deposited by sputtering on sputtered HZO or CSD Y-HZO layer to fabricate metal-ferroelectric-semiconductor (MFS) structure. It was found that the sputtered HZO films in the MFS structure became paraelectric after re-annealing in N2 which was confirmed by both X-ray diffraction pattern and electrical measurements. On the other hand, the CSD Y-HZO films showed ferroelectric nature even after re-annealing with a negligible monoclinic phase.

Indium oxide and indium-tin-oxide channel ferroelectric gate thin film transistors with yttrium doped hafnium-zirconium dioxide gate insulator prepared by chemical solution process

Ferroelectric gate transistor (FGT) with yttrium doped hafnium-zirconium dioxide (Y-HZO) gate insulator and oxide channel with various thicknesses of In2O3 and ITO were fabricated by chemical solution deposition. First, ferroelectric properties of Y-HZO in the metal-ferroelectric-semiconductor structure with 5–22 nm thick In2O3 and 6–24 nm thick ITO, have been confirmed by polarization–voltage and capacitance–voltage (C–V) characteristics. The C–V curves showed clear butterfly loops showing the depletion of In2O3 and ITO layer. Secondly, the device performance of FGTs has been evaluated with various thicknesses of In2O3 and ITO channel layer. The fabricated FGTs exhibited typical n-channel transistor operation with a counterclockwise hysteresis loop due to the ferroelectric nature of the Y-HZO-gate insulator. It was found that FGT shows a low subthreshold voltage swing, high on/off drain current ratio of 106, large on current, and memory window.

Kelvin probe force microscopy study on operating In-Sn-O-channel ferroelectric-gate thin-film transistors

Surface potentials of an operating In-Sn-O channel ferroelectric-gate transistor (FGT) were mapped by Kelvin probe force microscopy. We clearly observed a gradual transition within the channel from linear potential profile to superlinear ones when drain voltage approaches and overcomes gate voltage, which is related to the physics of electronic transport under field-effect doping. The dependence of field-effect mobility on gate-bias and lateral field, as well as the effect of source/drain electrode materials on transport properties, was also elucidated. This study provides useful information for optimizing the FGT performance and for understanding its underlying physics.

Croconic Acid Thin Film Formation for Ferroelectric Gate OFETs

ABSTRACTPentacene-based ferroelectric gate transistors with croconic acid (CrA) thin film was fabricated for the first time. The memory window (MW) of 1.9 V was obtained from the capacitance-voltage (C-V) characteristics of Al/CrA(50 nm)/SiO2/Si(100) metal-ferroelectric-insulator-semiconductor (MFIS) diode, where the deposition temperature of CrA was room temperature (RT). Butterfly type C-V characteristics was observed for Al/CrA(50 nm)/Al/SiO2/ Si(100) metal-ferroelectric-metal (MFM) diode. Furthermore, a pentacene-based p-type organic field-effect transistor (OFET) with CrA gate insulator was fabricated, and clockwise hysteresis loop was observed in ID-VG characteristic, which is attributed to the ferroelectric properties of CrA gate insulator.

Analysis of carrier modulation in channel of ferroelectric-gate transistors having polar semiconductor

We have been fabricated and characterized a ferroelectric-gate thin-film transistors (TFTs) using ZnO as a channel polar semiconductor and YMnO 3 as a ferroelectric gate. A typical n-channel transistor property showing clear drain current saturation in I D– V D (drain current – drain voltage) characteristics was recognized. When the 3 V of the gate voltage is applied under the 4 V of drain voltage, the large drain current of about 1.1 mA is obtained. These controlled-polarization-type ferroelectric-gate TFTs using ZnO-channel TFTs operate in the accumulation–depletion mode and the ON/OFF state of the ferroelectric-gate TFTs strongly depends on the polarization switching of P SFe. In this paper, therefore, the polarization switching of P SFe in the TFT is carefully examined and the relationship between the polarization switching and the carrier accumulation (depletion) state is discussed using impedance spectroscopy and Capacitance–Voltage (C–V) measurements at applied the gate voltage.

Fabrication and characterization of metal-ferroelectric-insulator-Si diodes and transistors with different HfSiON buffer layer thickness

Metal-ferroelectric-insulator-Si (MFIS) structures using HfSiON as buffer layers were fabricated, and the impact of buffer layer thickness on the electrical properties of the MFIS devices was investigated. HfSiON films with thickness ranging from 1 to 4 nm were deposited by electron beam evaporation, which exhibited much reduced leakage current when compared to that of SiO2 with the same equivalent oxide thickness. From the viewpoint of polarization and charge injection, the flatband voltage and memory window width dependent on the sweeping voltages were discussed for the MFIS diodes with 1-, 2-, and 4-nm-thick HfSiON buffer layers. Small leakage current as well as excellent long-term data retention characteristics were found for all of these samples. It was also found that MFIS diodes with 2-nm-thick HfSiON buffer layer have the largest memory window width. Ferroelectric-gate transistors fabricated with a Pt/SBT(300nm)/HfSiON (2 nm)/Si gate structure showed a memory window of 0.8 V and a high drain current on/off ratio of 108 for the gate voltage sweep between +4 and −4 V. All of these excellent electrical properties proved that HfSiON acts as an excellent barrier for suppressing both leakage current and atomic interdiffusion.

Metal–ferroelectric–insulator–Si devices using HfTaO buffer layers

Metal–ferroelectric–insulator–Si (MFIS) diodes and transistors using Pt/Sr0.8Bi2.2Ta2O9 (SBT)/HfTaO/Si gate structures were fabricated. HfTaO films were deposited at room temperature by electron beam evaporation under a background vacuum of ∼1.5 × 10−9 Torr. By process optimization of post-deposition annealing, a small effective oxide thickness of 1.6 nm, a small leakage current of 2.4 × 10−4 A cm−2 at a voltage shifted from the flat band voltage by 1 V and a negligible hysteresis loop were obtained for Al/HfTaO (4 nm)/Si diodes. The MFIS diodes were fabricated by the deposition of SBT films on the HfTaO (4 nm)/Si substrate using chemical solution deposition. A memory window of 0.62 V was obtained for Pt/SBT (300 nm)/HfTaO (4 nm)/Si diodes for a voltage sweep between +4 V and −4 V. P-channel ferroelectric-gate transistors were fabricated using the same gate structure, which showed a memory window of 0.6 V and good long-term retention characteristics. A drain current ON/OFF ratio as high as 103 was attained at a fixed reading voltage of −0.7 V even after over 104 s has elapsed.

Ｐｔ／ＳｒＢｉ２Ｔａ２Ｏ９／Ｈｆ‐Ａｌ‐Ｏ／Ｓｉダイオードの素子特性に及ぼすＨｆ‐Ａｌ‐Ｏ層への窒素導入の効果

A metal/ferroelectric/insulator/semiconductor Pt/SrBi2Ta2O9(SBT)/Hf-Al-O(HAO)/Si is a promising gate structure for a ferroelectric-gate transistor. Effects of adding nitrogen into the HAO were investigated. Pt/SBT/HAO(N)/Si and Pt/SBT/HAO(O)/Si were prepared by depositing the HAO in N2 and O2, respectively. Nitrogen inclusion in the HAO(N) was confirmed by secondary ion mass spectrometry (SIMS). The SIMS results also indicated that diffusions of Sr, Bi and Ta into the HAO(N) were much more suppressed than those into HAO(O). Scanning transmission electron microscope (STEM) images showed that the HAO(N) was amorphous and fine while the HAO(O) was polycrystallized and rugged. The STEM image also showed an interfacial layer (IL) between the HAO and Si, grown mainly during an annealing process at 800°C for 1h for SBT polycrystallization. The major components of the IL were Si and O. The IL thicknesses of the HAO(N) and the HAO(O) were 3.4 nm and 7.4 nm respectively. Capacitance-voltage measurements of the Pt/SBT/HAO(N)/Si showed a 0.9V memory window at ±6V gate-voltage swing, which was three times larger than the memory window of the Pt/SBT/HAO(O)/Si. We concluded that adding nitrogen into the HAO of Pt/SBT/HAO/Si was effective for obtaining a large memory window by suppressing material diffusions and the IL layer growth.

Fabrication of Ferroelectric Gate Transistors with Sr(Ti,Ru)O3 as a Channel

Fabrication of Ferroelectric Gate Transistors with Sr(Ti,Ru)O3 as a Channel

Selective etching process of SrBi2Ta2O9 and CeO2 for self-aligned ferroelectric gate structure

We have investigated an etch-stop process and fabricated the ferroelectric gate transistor without damage of source and drain regions using etching selectivity between etch rates of SrBi2Ta2O9 (SBT) and CeO2. The SBT and CeO2 were etched with inductively coupled plasma (ICP) reactive ion etching at various Ar/Cl2 gas mixing ratios, ICP powers, and rf bias powers. The etching selectivity of SBT/CeO2 was 6.8 and the vertical etching angle of SBT was 82° at the condition of 50% Cl2 concentration with the ICP power of 900 W and the rf bias power of 100 W. The characteristics of devices fabricated with an etch-stop process showed that there was no degradation of the ferroelectric characteristics and on/off ratio of programmable operation was 104.

Investigation of Retention Properties for YMnO3 Based Metal/Ferroelectric/Insulator/Semiconductor Capacitors

ABSTRACTThe memory retention properties of Pt/YMnO3/Y2O3/Si capacitors were investigated for the application of ferroelectric gate transistors. The epitaxially grown Pt/YMnO3/Y2O3/Si capacitors showed ferroelectric type hysteresis loop on the capacitance-voltage properties. Although the retention time of the as-deposited capacitors was ∼103 s, it was prolonged up to 104 s when the leakage current density was reduced from 4×10-8 A/cm2 to 2×10-9 A/cm2 by the annealing under N2 ambience. To reveal the relationship between the retention time and leakage current, the leakage current mechanism was investigated comparing several conduction mechanisms. It was found that the dominant leakage mechanisms at high and low electric fields were Poole-Frenkel emission from the Y2O3 layer and ohmic conduction, respectively. This result indicates that the leakage current was limited by the Y2O3 layer at high electric field and was mainly dominated by the amount of defects in the YMnO3 layer at low electric field. From the pseudo isothermal capacitance transient spectroscopy (ICTS), it was determined that the trap density was in an order of 1015 cm-3. Since the variation of the leakage current by annealing was observed only in the low electric field region, it is suggested that the retention properties of the Pt/YMnO3/Y2O3/Si capacitors was influenced by the amount of defects in the YMnO3 layer.

Investigation of Retention Properties for YMnO3 Based Metal/Ferroelectric/Insulator/Semiconductor Capacitors

ABSTRACTThe memory retention properties of Pt/YMnO3/Y2O3/Si capacitors were investigated for the application of ferroelectric gate transistors. The epitaxially grown Pt/YMnO3/Y2O3/Si capacitors showed ferroelectric type hysteresis loop on the capacitance-voltage properties. Although the retention time of the as-deposited capacitors was ∼103 s, it was prolonged up to 104 s when the leakage current density was reduced from 4×10−8 A/cm2 to 2×10−9 A/cm2 by the annealing under N2 ambience. To reveal the relationship between the retention time and leakage current, the leakage current mechanism was investigated comparing several conduction mechanisms. It was found that the dominant leakage mechanisms at high and low electric fields were Poole-Frenkel emission from the Y2O3 layer and ohmic conduction, respectively. This result indicates that the leakage current was limited by the Y2O3 layer at high electric field and was mainly dominated by the amount of defects in the YMnO3 layer at low electric field. From the pseudo isothermal capacitance transient spectroscopy (ICTS), it was determined that the trap density was in an order of 1015 cm−3. Since the variation of the leakage current by annealing was observed only in the low electric field region, it is suggested that the retention properties of the Pt/YMnO3/Y2O3/Si capacitors was influenced by the amount of defects in the YMnO3 layer.

Growth process and interfacial structure of epitaxial Y 2O 3/Si thin films deposited by pulsed laser deposition

We have proposed the use of YMnO 3 as a ferroelectric layer and of Y 2O 3 as an insulator layer for ferroelectric gate transistor applications. Insertion of the Y 2O 3 layer at the YMnO 3/Si interface significantly improves the crystallinity of the YMnO 3 layer. Although we have used [1 1 1]-oriented Y 2O 3 layers so far, the epitaxially grown Y 2O 3 films have a potential to improve the ferroelectricity of the ferroelectric film. Furthermore, the Y 2O 3 films have a relatively large dielectric constant ( ε=14–17), as well as good thermal stability. However, it still remains unknown what the relationship is between dielectric properties and interfacial structure of epitaxial Y 2O 3/Si films. We have recently succeeded in obtaining epitaxially grown (1 1 1)Y 2O 3 on (1 1 1)Si surface by pulsed laser deposition method. In this report, the relationship between the crystallinity of the Y 2O 3 epitaxial film and the dielectric properties is discussed.

Fabrication and Characterization of Metal-Ferroelectric-Metal-Insulator-Semiconductor (MFMIS) Structures Using Ferroelectric (Bi, La)4Ti3O12 Films

We have fabricated and characterized Pt/(Bi, La)4Ti3O12(BLT)/Pt/Ti/SiO2/Si metal-ferroelectric-metal-insulator-semiconductor (MFMIS) structures for ferroelectric-gate transistor applications. It is demonstrated that BLT films fabricated using the metalorganic decomposition (MOD) technique at 750°C have excellent electrical properties. Remanent polarization 2Pr as large as 30 µC/cm2 can be obtained. It is also shown that in the memory window increases with the area ratio SF:SM of the MFMIS structure and that a large memory window (3 V) can be obtained for a voltage sweep of ±5 V for MFMIS structures with an area ratio SF:SM of 1:15. In addition, it is demonstrated that MFMIS structures with an area ratio SF:SM of 1:15 have good data retention characteristics.

Improvement of Retention Property of YMnO3/Y2O3/Si MFIS Capacitor

AbstractWe have been proposing YMnO3 with low remanent polarization and permittivity as a ferroelectric gate transistor, and reported that c-oriented YMnO3 films were obtained on (111)Si with (111) oriented Y2O3 buffer layer. The ferroelectricity was confirmed by pulsed C-V measurement. However, the retention property was not satisfied because of its poor crystallinity. To improve the crystallinity of YMnO3 films, deposition conditions of Pulsed Laser Deposition (PLD) were optimized. The laser power, oxygen pressure and introducing Ozone gas are effective for maintaining the stoichiometry during the deposition. Improvement of the crystallinity of the YMnO3 film makes the retention property better. We also demonstrate the use of epitaxially grown Y2O3 buffer layer to improve the crystallinity of the YMnO3 films.

Ferroelectric-gate transistor as a capacitor-less DRAM cell (FEDRAM)

The Metal-Ferroelectric-Insulator-Semiconductor FET structure (or MFISFET) has been studied as a non-volatile memory device1-4 ever since the IEEE publication by Wu4 in 1974. However, so far there has not been any commercial product, because of some severe problems, including interface problems and retention time problem, among others.

Ferroelectric gate transistors

Abstract The characteristics of a field effect transistor with a lithium niobate gate insulator are reported. Shifts in the gate characteristics consistent with polarization switching have been observed. Comparisons with the results of some of the recently published theoretical models for ferroelectric gate transistors are made. Advantages and disadvantages of buffer layers in the gate structure are also discussed.

PIMOD processing and properties of a LiNbO3-based MFSFET for nonvolatile memories

Abstract The photo-induced metallo-organic decomposition (PIMOD) process has been successfully used to deposit a lithium niobate thin film acting as the gate oxide of the conventional MFSFET structure. The use of the low-temperature PIMOD process for thin film deposition has increased the device yields of the molybdenum liftoff for small area isolation. The electronic alteration of the properties of the ferroelectric gate transistor was previously shown to be caused by charges in the semiconductor being injected into the ferroelectric film. To prevent this problem, a thin SiO2 buffer layer was thermally grown on the silicon substrate immediately before lithium niobate deposition. The silicon-lithium niobate interface was stabilized and the charge injection effect was eliminated due to the formation of the buffer layer. The channel current was shown to be greatly altered by the application of voltage pulses between the gate of the device and the substrate. Upon switching, the change in surface conductivity...