Ferroelectric-gate Thin Film Transistors Research Articles

Crystallization of (Hf, Zr)O2 thin films via non-heating process and their application to ferroelectric-gate thin film transistors

HfO2-based ferroelectric materials do not necessarily require high-temperature annealing for crystallization, making them attractive for applications in transparent electronic devices on plastic or glass substrate. In this study, (Hf, Zr)O2 (HZO) films prepared via non-heating sputtering are investigated and their application to ferroelectric-gate thin-film transistors (TFTs) is demonstrated. The internal tensile stress induced by (In, Sn)O x (ITO) top-electrode deposition is found to promote the crystallization of HZO from the amorphous state to the ferroelectric phase. ITO/HZO (15–25 nm)/ITO capacitors prepared via the non-heating process exhibit ferroelectric hysteresis loops with remanent polarizations of 6–9 μC cm−2 and coercive fields of 0.6–1.1 MV cm−1. Ferroelectric-gate TFTs with a 10 nm thick ITO channel are also fabricated via the non-heating process. These TFTs show nonvolatile operation with an on/off ratio of ∼10. These findings demonstrate the potential of HZO for transparent devices on substrates with low thermal resistance prepared via the non-heating process.

Indium oxide and indium-tin-oxide channel ferroelectric gate thin film transistors with yttrium doped hafnium-zirconium dioxide gate insulator prepared by chemical solution process

Ferroelectric gate transistor (FGT) with yttrium doped hafnium-zirconium dioxide (Y-HZO) gate insulator and oxide channel with various thicknesses of In2O3 and ITO were fabricated by chemical solution deposition. First, ferroelectric properties of Y-HZO in the metal-ferroelectric-semiconductor structure with 5–22 nm thick In2O3 and 6–24 nm thick ITO, have been confirmed by polarization–voltage and capacitance–voltage (C–V) characteristics. The C–V curves showed clear butterfly loops showing the depletion of In2O3 and ITO layer. Secondly, the device performance of FGTs has been evaluated with various thicknesses of In2O3 and ITO channel layer. The fabricated FGTs exhibited typical n-channel transistor operation with a counterclockwise hysteresis loop due to the ferroelectric nature of the Y-HZO-gate insulator. It was found that FGT shows a low subthreshold voltage swing, high on/off drain current ratio of 106, large on current, and memory window.

Electrical properties of yttrium-doped hafnium-zirconium dioxide thin films prepared by solution process for ferroelectric gate insulator TFT application

Ferroelectric yttrium-doped hafnium-zirconium dioxide (Y-HZO) thin films were fabricated by solution process on Pt/Ti/SiO2/Si substrates. Both metal–ferroelectric–metal (MFM) structures with Pt top electrode and metal–ferroelectric–semiconductor (MFS) structures with indium tin oxide (ITO) top electrode were fabricated and characterized. Solution-derived Y-HZO films annealed at 600 °C–800 °C showed ferroelectric properties which were confirmed by polarization–voltage loops (P–V) and capacitance–voltage (C–V) curves. The ferroelectric properties of Y-HZO were superior to those of undoped HZO, Y-doped HfO2 and undoped HfO2 samples. C–V curves showed clear butterfly loops with depletion of top ITO layer in the case of MFS, while no depletion was observed in the case of MFM structures. Large memory window was obtained for MFS structures and ferroelectric properties were observed even after high temperature annealing process during the solution deposition of ITO electrodes. These results suggest that a solution processed Y-HZO is a promising candidate for ferroelectric gate thin film transistor.

Demonstration on Ferroelectric-gate Thin Film Transistor NAND-type Array with Disturbance-free Operation

Abstract: A novel concept of NAND memory array has been proposed by using only ferroelectric-gate thin film transistors (FGTs), whose structure is constructed from a sol-gel ITO channel and a sol-gel stacked ferroelectric between Bi3.25La0.75Ti3O12 and PbZr0.52TiO0.48O3 (BLT/PZT) gate insulator. Interestingly, ferroelectric cells with a wide memory window of 3 V and a large on/off current ratio of 6 orders, have been successfully integrated in a NAND memory circuit. To protect data writing or reading from disturbance, ferroelectric transistor cells are directly used, instead of paraelectric transistor cells as usual. As a result, we have verified disturbance-free operation for data reading and writing, with a small loss of the memory state and a low power consumption, in principle.
 Keywords: ITO, PZT, NAND, FeRAM, ferroelectric.

Low-temperature PZT thin-film ferroelectric memories fabricated on SiO 2 /Si and glass substrates

Abstract In a ferroelectric-gate thin film transistor memory (FGT) type structure, the gate-insulator layer is extremely important for inducing the charge when accumulating or depleting. We concentrated on the application of low-temperature PZT films crystallized at 450, 500 and 550 °C, instead of at conventional high temperatures (≥600 °C). Investigation of the crystalline structure and electrical properties indicated that the PZT film, crystallized at 500 °C, was suitable for FGT fabrication because of a high (111) orientation, large remnant polarization of 38 μ C/cm 2 on SiO 2 /Si substrate and 17.8 μ C/cm 2 on glass, and low leakage current of 10 −6 A/cm 2 . In sequence, we successfully fabricated FGT with all processes below 500 °C on a glass substrate, whose operation exhibits a memory window of 4 V, ON/OFF current ratio of 10 5 , field-effect mobility of 0.092 cm 2 V −1 s −1 , and retention time of 1 h.

Fabrication and characterization of ferroelectric-gate thin-film transistors with an amorphous oxide semiconductor, amorphous In–Ga–Zn–O

We fabricated and characterized ferroelectric-gate thin-film transistors (FeTFTs) with an amorphous In–Ga–Zn–O (a-IGZO) channel and an oxide ferroelectric (Bi,La)4Ti3O12 (BLT) gate insulator, and examined the fabrication conditions beforehand for realizing ferroelectric hysteresis in their drain current versus gate voltage (ID–VG) characteristics. First, the optimal annealing conditions for BLT-thin-film formation by the sol–gel method were considered in terms of chemical phenomena and crystallization mechanism. As a result, the leakage current density of the film was decreased by more than two orders of magnitude. Second, sputtering deposition conditions and postdeposition annealing temperatures of a-IGZO thin films were investigated to prepare the a-IGZO channel with good electrical properties. A small charge-injection-type hysteresis width of 0.2 V was obsereved in ID–VG characteristics of a-IGZO/SiO2 TFTs. Finally, a-IGZO/BLT FeTFTs were fabricated using the above results, and the ferroelectric hysteresis with a width of 0.4 V was observed.

Relationship between source/drain-contact structures and switching characteristics in oxide-channel ferroelectric-gate thin-film transistors

We report on oxide-channel ferroelectric-gate thin-film transistors (FeTFTs) with the bottom-contact structure for source and drain electrodes. FeTFTs with the bottom-contact structure have faster switching characteristics than those with the top-contact structure, especially for the switching from ON to OFF. First, we confirmed that FeTFTs with the top- or bottom-contact structure exhibit similar ID–VG characteristics and retention properties to each other. Next, we measured the C–V characteristics and confirmed that the oxide semiconductor channel under the source and drain electrodes is depleted in the top-contact structure. This depleted channel impedes the switching from ON to OFF. Finally, we demonstrated that FeTFTs with the bottom-contact structure possess fast switching characteristics for the switching from both OFF to ON and ON to OFF.

Kelvin probe force microscopy study on operating In-Sn-O-channel ferroelectric-gate thin-film transistors

Surface potentials of an operating In-Sn-O channel ferroelectric-gate transistor (FGT) were mapped by Kelvin probe force microscopy. We clearly observed a gradual transition within the channel from linear potential profile to superlinear ones when drain voltage approaches and overcomes gate voltage, which is related to the physics of electronic transport under field-effect doping. The dependence of field-effect mobility on gate-bias and lateral field, as well as the effect of source/drain electrode materials on transport properties, was also elucidated. This study provides useful information for optimizing the FGT performance and for understanding its underlying physics.

Fabrication of 120-nm-channel-length ferroelectric-gate thin-film transistor by nanoimprint lithography

Nanoimprint lithography (NIL) is one of the most promising device fabrication techniques because it has a high resolution and moderate fabrication cost. Oxide-based thin-film transistors (TFTs) with various physical properties have the potential to outperform Si-based large-scale integration (LSI) devices. In this study, we focus on the miniaturization of oxide-based TFTs by NIL. A ferroelectric-gate thin-film transistor (FGT) was prepared by incorporating a chemical-solution-deposition (CSD)-processed indium tin oxide channel, a Pb(Zr,Ti)O3 (PZT) gate insulator, and sputtered Pt electrodes. The Pt source–drain electrodes and ITO channel were patterned by the NIL process. The results show that we successfully fabricated an FGT with a channel length of 120 nm by NIL. The 120 nm channel length was confirmed by scanning electron microscopy (SEM). The fabricated NIL-FGT showed typical n-channel transistor characteristics. The obtained ON/OFF current ratio, threshold voltage, subthreshold voltage, and field-effect mobility were 103, 0.5 V, 1.0 V/decade, and 0.1–0.2 cm2·V−1·s−1, respectively.

Ferroelectric-gate thin-film transistors with Bi3.15Nd0.85Ti3O12 gate insulators on LaNiO3-buffered Si substrates

Ferroelectric-gate thin-film transistors (FGTs) with a stacked oxide structure of ZnO/Bi3.15Nd0.85Ti3O12 (BNT)/LaNiO3 (LNO) on Si substrates have been prepared and characterized.

Surface-modified lead–zirconium-titanate system for solution-processed ferroelectric-gate thin-film transistors

We propose the use of a La2O3 (LO) film as the capping layer for improvement of a semiconductor/insulator interface in a solution-processed indium–tin–oxide (ITO) ferroelectric-gate thin-film transistor (FGT) device. It is demonstrated that the LO layer acts as a good barrier film not only for preventing the interdiffusion between the ITO semiconductor and lead–zirconium-titanate (PZT) insulator layers, but also for stabilizing the PZT surface structure. The fabricated FGT device exhibited high I on/I off, large M w, high μ FE and improved retention time of about 109, 3.5 V, 7.94 cm2 V−1 s−1 and 1 day, respectively, which are comparable to or better than those obtained with FGTs fabricated by means of conventional vacuum processes. We also point out that the key origin of the interface improvement is likely due to the incorporation of La into the PZT system, forming a La surface-modified PZT system which is more stable than the pure PZT in terms of Pb volatility and formation of oxygen vacancies.

Interface Charge Trap Density of Solution Processed Ferroelectric Gate Thin Film Transistor Using ITO/PZT/Pt Structure

The conductance method was applied to investigate the interface charge trap density (Dit ) of solution processed ferroelectric gate thin film transistor (FGT) using indium-tin oxide (ITO)/ Pb(Zr,Ti)O3 (PZT)/Pt structure. As a result, a large value of Dit of MFS capacitor, i.e., Pt/PZT/ITO, was estimated to be 1.2 × 1014 eV−1 cm−2. This large Dit means that an interface between the ITO layer and the PZT layer is imperfect and it is one of the main reasons for the poor memory property of this FGT. By using transmission electron microscopy (TEM), this imperfect interface was clearly observed. Thus, it is concluded that improvement of this interface is critical for better memory performance.

ナノチャネルを有する強誘電体ゲート薄膜トランジスタの作製とその電気特性評価

Controlled-polarization-type ferroelectric gate thin film transistors (CP-type FeTFT) with nano-gap channel were fabricated by using a ZnO channel and a YMnO3 ferroelectric film. The electrical properties of the epitaxially grown (0001)ZnO/(0001)YMnO3 heterostructure fabricated by a pulsed laser deposition method were investigated by an impedance spectroscopy to discuss the carrier modulation by the spontaneous polarization of YMnO3. It was found that the ZnO layer surrounding the top electrode has low resistivity. 100 nm-gap electrode was formed by an inclined deposition method on the ZnO/YMnO3 heterostructure. The TFT showed non-volatile memory operation. However, the field-effect mobility is calculated to be 0.25 cm2/Vs, which is ten times lower than that of the micro-channel TFT. The decrease of the resistivity of the ZnO layer surrounding the top electrode is a possible origin of the decrease of the field-effect mobility.

Effect of Coercive Voltage and Charge Injection on Performance of a Ferroelectric-Gate Thin-Film Transistor

We adopted a lanthanum oxide capping layer between semiconducting channel and insulator layers for fabrication of a ferroelectric-gate thin-film transistor memory (FGT) which uses solution-processed indium-tin-oxide (ITO) and lead-zirconium-titanate (PZT) film as a channel layer and a gate insulator, respectively. Good transistor characteristics such as a high “on/off” current ratio, high channel mobility, and a large memory window of 108, 15.0 cm2 V−1 s−1, and 3.5 V were obtained, respectively. Further, a correlation between effective coercive voltage, charge injection effect, and FGT’s memory window was investigated. It is found that the charge injection from the channel to the insulator layer, which occurs at a high electric field, dramatically influences the memory window. The memory window’s enhancement can be explained by a dual effect of the capping layer: (1) a reduction of the charge injection and (2) an increase of effective coercive voltage dropped on the insulator.

Electric Properties and Interface Charge Trap Density of Ferroelectric Gate Thin Film Transistor Using (Bi,La)4Ti3O12/Pb(Zr,Ti)O3 Stacked Gate Insulator

We successfully fabricated ferroelectric gate thin film transistors (FGTs) using solution-processed (Bi,La)4Ti3O12 (BLT)/Pb(Zr,Ti)O3 (PZT) stacked films and an indium–tin oxide (ITO) film as ferroelectric gate insulators and an oxide channel, respectively. The typical n-type channel transistors were obtained with the counterclockwise hysteresis loop due to the ferroelectric property of the BLT/PZT stacked gate insulators. These FGTs exhibited good device performance characteristics, such as a high ON/OFF ratio of 106, a large memory window of 1.7–3.1 V, and a large ON current of 0.5–2.5 mA. In order to investigate interface charge trapping for these devices, we applied the conductance method to MFS capacitors, i.e., Pt/ITO/BLT/PZT/Pt capacitors. As a result, the interface charge trap density (Dit) between the ITO and BLT/PZT stacked films was estimated to be in the range of 10-11–10-12 eV-1 cm-2. The small Dit value suggested that good interfaces were achieved.

Correlated motion dynamics of electron channels and domain walls in a ferroelectric-gate thin-film transistor consisting of a ZnO/Pb(Zr,Ti)O3 stacked structure

We studied the switching dynamics of a ferroelectric-gate thin-film transistor (FeTFT) consisting entirely of oxide-based thin films: SrRuO3 (SRO: bottom-gate electrode), Pb(Zr,Ti)O3 (PZT: ferroelectric), and ZnO (semiconductor). We switched the FeTFT channel conductance by applying short pulses to the gate electrode. We found that the switching of a FeTFT was caused by the domain wall motion in a ferroelectric film. The polarization reversal starts from the region located under the source and drain electrodes and travels along the channel length direction. In addition, the domain wall velocity increases as the domain wall gets closer to the source and drain electrodes in a ferroelectric film. Therefore, a FeTFT has the scaling merit of fast operation speed.

Effect of Ferroelectric Polarization Domain Structure on Electronic Transport Property of Ferroelectric/ZnO Heterostructure

To discuss the effect of the ferroelectric domain structure on the electronic transport property in the channel of a ferroelectric gate thin film transistor, the electrical property of the ferroelectric gate stack structure of an organic ferroelectric copolymer of vinylidenefluoride and tetrafluoroethylene [P(VDF–TeFE)] and ZnO was investigated. Unlike the gate stack structure using a paraelectric layer, ferroelectrics possibly affect the electron transport in the channel through its domain structure. In this study, the Hall-effect measurements were carried out at various polarized states of P(VDF–TeFE). The Hall mobility at poling voltages from 100 to -100 V showed a gradual decrease with decreasing poling voltage, whereas the carrier concentration shows a slight change in the accumulation state. The change in the carrier concentration indicates the formation of the multidomain structure in P(VDF–TeFE). The multidomain structure might be attributed to the electron scattering in the ZnO channel layer.

Ferroelectric-Gate Thin-Film Transistor Fabricated by Total Solution Deposition Process

We have fabricated inorganic ferroelectric-gate thin-film transistors (FGTs) using only a chemical solution deposition (CSD) process. All layers, including the LaNiO3 (LNO) gate electrode, Pb(Zr,Ti)O3 (PZT) ferroelectric-gate insulator, indium–tin-oxide (ITO) source/drain electrodes, and ITO channel, were formed on a SrTiO3 (STO) substrate by the CSD process. We obtained a local epitaxially grown PZT/LNO perovskite heterostructure with good crystalline quality and no interfacial layer. The fabricated FGT exhibited typical n-channel transistor operation, with a counterclockwise hysteresis loop due to the ferroelectric nature of the PZT-gate insulator, and also exhibited good drain current saturation in output characteristics. These properties are equivalent to or better than those obtained with FGTs fabricated by means of conventional vacuum processes. The obtained on/off current ratio, memory window, and subthreshold voltage swing were about 106, 2.5 V, and 357 mV/decade, respectively.

Ferroelectric-Gate Thin-Film Transistor Fabricated by Total Solution Deposition Process

We have fabricated inorganic ferroelectric-gate thin-film transistors (FGTs) using only a chemical solution deposition (CSD) process. All layers, including the LaNiO3 (LNO) gate electrode, Pb(Zr,Ti)O3 (PZT) ferroelectric-gate insulator, indium–tin-oxide (ITO) source/drain electrodes, and ITO channel, were formed on a SrTiO3 (STO) substrate by the CSD process. We obtained a local epitaxially grown PZT/LNO perovskite heterostructure with good crystalline quality and no interfacial layer. The fabricated FGT exhibited typical n-channel transistor operation, with a counterclockwise hysteresis loop due to the ferroelectric nature of the PZT-gate insulator, and also exhibited good drain current saturation in output characteristics. These properties are equivalent to or better than those obtained with FGTs fabricated by means of conventional vacuum processes. The obtained on/off current ratio, memory window, and subthreshold voltage swing were about 106, 2.5 V, and 357 mV/decade, respectively.

Impedance Analysis of Controlled-Polarization-Type Ferroelectric-Gate Thin Film Transistor Using Resistor–Capacitor Lumped Constant Circuit

We propose a novel ferroelectric-gate field-effect transistor using a polar oxide semiconductor channel, which is called a controlled-polarization (CP)-type ferroelectric-gate thin film transistor (TFT). Although the CP-type ferroelectric-gate TFTs with a ZnO/YMnO3 structure shows nonvolatile memory operation, the relationship between the electrical characteristics of the TFTs and the direction of spontaneous polarization of the ferroelectric layer (PSFe) below the channel has not been revealed. In this study, the direction of PSFe is analyzed by the impedance spectra of the channel conductance because it can be expected that the channel conductance depends on the direction of the PSFe. The five conditions of the channel conductance are assumed and the impedances between the source electrode and the gate electrode of each condition are calculated by SPICE. The direction of PSFe at various gate voltages is determined by the comparison of the calculated results and experimental results. It was found that the channel conductance of the ferroelectric-gate TFT has steep change by the change of the direction of PSFe.