Effect of Coercive Voltage and Charge Injection on Performance of a Ferroelectric-Gate Thin-Film Transistor

P T Tue,T Miyasako,T Shimoda,E Tokumitsu

doi:10.1155/2013/692469

Abstract

We adopted a lanthanum oxide capping layer between semiconducting channel and insulator layers for fabrication of a ferroelectric-gate thin-film transistor memory (FGT) which uses solution-processed indium-tin-oxide (ITO) and lead-zirconium-titanate (PZT) film as a channel layer and a gate insulator, respectively. Good transistor characteristics such as a high “on/off” current ratio, high channel mobility, and a large memory window of 108, 15.0 cm2 V−1 s−1, and 3.5 V were obtained, respectively. Further, a correlation between effective coercive voltage, charge injection effect, and FGT’s memory window was investigated. It is found that the charge injection from the channel to the insulator layer, which occurs at a high electric field, dramatically influences the memory window. The memory window’s enhancement can be explained by a dual effect of the capping layer: (1) a reduction of the charge injection and (2) an increase of effective coercive voltage dropped on the insulator.

Highlights

Ferroelectric-gate thin-film transistors (FGTs) have attracted much attention due to their nonvolatility, high write speed, low power consumption, and high endurance
In order to solve the interface problem, we have proposed the use of a lanthanum oxide (LO) as a capping layer between ITO and processed indium-tin-oxide (ITO) and lead-zirconium-titanate (PZT) to prevent the reaction and interdiffusion between these layers, as well as to improve the retention properties [23]
When a gate bias is applied to the ferroelectric gate structure, the unsaturated electric field applied to the ferroelectric film and the charge injection from the semiconductor to the interlayer can dominantly reduce the memory window because a high electric field is applied to the interlayer

Summary

Introduction

Ferroelectric-gate thin-film transistors (FGTs) have attracted much attention due to their nonvolatility, high write speed, low power consumption, and high endurance. Various types of FGTs composed of different stacked structures have been investigated [1,2,3,4,5,6,7,8,9,10,11] These devices exhibited very short retention time up to now, except for the case of epitaxial growth of the stacked ZnO/PZT/SrRuO3 structure by pulsed laser processing [6, 12]. When a gate bias is applied to the ferroelectric gate structure, the unsaturated electric field applied to the ferroelectric film and the charge injection from the semiconductor to the interlayer can dominantly reduce the memory window because a high electric field is applied to the interlayer It has usually suggested inserting a buffer insulator between the ferroelectric and the semiconducting channel, resulting in decreasing the electric field applied to the interlayer [25, 26]. The memory window’s enhancement can be explained by a dual effect of the capping layer: (1) a reduction of the charge injection and (2) an increase of effective coercive voltage dropped on the insulator

Experimental Details

Results and Discussion

Conclusion