Device Feature Size Research Articles

Present and future thermal interface materials for electronic devices

ABSTRACTPackaging electronic devices is a growing challenge as device performance and power levels escalate. As device feature sizes decrease, ensuring reliable operation becomes a challenge. Ensuring effective heat transfer from an integrated circuit and its heat spreader to a heat sink is a vital step in meeting this challenge. The projected power density and junction-to-ambient thermal resistance for high-performance chips at the 14 nm generation are >100 Wcm−2 and <0.2 °CW−1, respectively. The main bottleneck in reducing the net thermal resistance are the thermal resistances of the thermal interface material (TIM). This review evaluates the current state of the art of TIMs. Here, the theory of thermal surface interaction will be addressed and the practicalities of the measurement techniques and the reliability of TIMs will be discussed. Furthermore, the next generation of TIMs will be discussed in terms of potential thermal solutions in the realisation of Internet of Things.

Guest Editorial Special Issue on Power Semiconductor Devices and Smart Power IC Technologies

Power semiconductor devices have been a mainstay of electron device technology since the introduction of the thyristor in the late 1950s. In the last six decades, electron devices and VLSI technology have gone through unprecedented changes. The state-of-the-art performance has progressed closely according to the famous Moore's Law, since it was introduced in 1965. The current techno-trend is the “More Than Moore” roadmap with emphasis on System in Package and 3-D integration. Over this period, we have witnessed device feature sizes shrinking from several microns in the 1970s to the 10-nm production-ready processes in 2017. At the same time, power semiconductor devices have also benefited significantly from these advancements.

Creation of unidirectional spin-wave emitters by utilizing interfacial Dzyaloshinskii-Moriya interaction

We present an analytic and numerical study of the creation of an uni-directional spin-wave emission in ultra-thin ferromagnetic films sandwiched in an asymmetric layer stack. For this we extend the analytical description of spin waves in spin-wave waveguides by the incorporation of the influence of the interfacial Dzyaloshinskii-Moriya interaction on the spin-wave propagation. By exploring the model system Ni$_{81}$Fe$_{19}$/Pt we show that it is possible to achieve an uni-directional spin-wave emission by combining wave-vector selective excitation sources with the frequency splitting which arises from interfacial Dzyaloshinskii-Moriya interaction. Hereby we focus on device feature sizes and spin-wave wavelengths compatible with state-of-the art excitation and detection schemes. We demonstrate that the optimum operation conditions for the non-reciprocal emission can be predicted using the presented analytical formalism

Dye gain gold NW array of surface plasmon polariton waveguide

Plasmon lasers can support ultrasmall mode confinement and ultrafast dynamics with device feature sizes below the diffraction limit. At present in the single visible light frequency, the optical gain method of constraint SPP on metal nanowires structure reported less. We design the gold nanowire array structure, consisting of PMMA and R6G dye molecules as gain, by 488nm pump in the middle of the nanowires position for wide range of light, use symmetry broken overcome that momentum does not match the photonic and SPP energy conversion. Theoretical analysis shows that dyes provide coherent optical feedback, resulting in nanowires face will observe laser properties of surface plasmons. Feature analysis: the incident light and pump joint strength is greater than the sum of strength which is the incident light, pump respectively. Under the effect of dye molecules gain effective, length of SPP transmission can increase 1µm. The results achieved in a single optical frequency of stimulated radiation, application of dye optical gain can achieve continuous gain effect. This is for the future development of plasma amplifier and the wavelength laser.

Novel method for measurement of transistor gate length using energy-filtered transmission electron microscopy

As the feature size of devices continues to decrease, transmission electron microscopy (TEM) is becoming indispensable for measuring the critical dimension (CD) of structures. Semiconductors consist primarily of silicon-based materials such as silicon, silicon dioxide, and silicon nitride, and the electrons transmitted through a plan-view TEM sample provide diverse information about various overlapped silicon-based materials. This information is exceedingly complex, which makes it difficult to clarify the boundary to be measured. Therefore, we propose a simple measurement method using energy-filtered TEM (EF-TEM). A precise and effective measurement condition was obtained by determining the maximum value of the integrated area ratio of the electron energy loss spectrum at the boundary to be measured. This method employs an adjustable slit allowing only electrons with a certain energy range to pass. EF-TEM imaging showed a sharp transition at the boundary when the energy-filter’s passband centre was set at 90 eV, with a slit width of 40 eV. This was the optimum condition for the CD measurement of silicon-based materials involving silicon nitride. Electron energy loss spectroscopy (EELS) and EF-TEM images were used to verify this method, which makes it possible to measure the transistor gate length in a dynamic random access memory manufactured using 35 nm process technology. This method can be adapted to measure the CD of other non-silicon-based materials using the EELS area ratio of the boundary materials.

An Ultra-Short Channel Monolayer MoS2 FET Defined By the Curvature of a Thin Nanowire

In this letter, we demonstrate the first top-gated 10-nm scale field-effect transistor with chemical-vapor-deposition synthesized monolayer MoS2 as the channel material. Ultra-thin metallic Co2Si nanowires are employed to gate the MoS2 channel and thereby define the device feature size—gate/channel length, as well as to serve as a self-aligned mask for source/drain metallization. This process not only avoids using the high-cost and low-yield electron beam lithography to define the gate/channel length, but also enables a top-gate structure with ultrathin gate dielectric. The latter is required to suppress short channel effects, but difficult to achieve with conventional deposition techniques on 2D layered semiconductors. Moreover, low OFF-current of 10 pA/ $\mu \text{m}$ and high ON/OFF current ratio over six orders are achieved, which makes this device quite promising for next-generation CMOS technology.

Electrically Scaled Hafnium Oxide Based Ge Devices

As device feature sizes have continued to scale, new device engineering and dielectric materials with engineered properties are becoming essential in overcoming the issues in scaled CMOS devices such as short channel effects. Some of the recent innovations in reducing short channel effects and improved performance are through the introduction of FinFETs, nanowires, and high mobility channel materials. High mobility channel materials, such as Ge and III-V (InGaAs, GaAs), are attracting increasing interest due to the possibility of realizing increased performance even without scaling the gate length of the device (1-3). Ge is particularly attractive for use as a channel material for P-type MOSFETs due to its high hole mobility and Si VLSI high volume manufacturing compatibility. In this paper we report progress in high-k phase engineering through HfO2:ZrO2 doping combined with intermittent annealing and post deposition microwave plasma oxidation in order to achieve sub nm EOT with reasonable leakage. In this regard, 300mm epi Ge/Al2O3/ZrO2/TiN MOSCAP devices were fabricated using epitaxially grown Ge. We have utilized a TEL CertasTM Chemical Oxide Removal (COR) process (4), which uses anhydrous HF and ammonia, rather than traditional wet cleaning, to remove Ge native oxides without damaging or roughening the fragile Ge surface. The high-k stack Al2O3/HfxZr1-xO2 were deposited by atomic layer deposition on a TEL Triase +TM tool. The ALD HfxZr1-xO2 films were deposited using a cyclical deposition and annealing scheme (termed DADA) (5-6). Prior to the ALD HfxZr1-xO2 a thin ALD Al2O3 was deposited. An additional post microwave plasma oxidation was also carried out in situ. A post plasma Al2O3/ZrO2control sample with no DADA process was also fabricated. Figure 1 shows electrical leakage Jg vs equivalent oxide thickness (EOT). The electrical analysis show a scaled EOT of ~0.6nm with the combination of DADA and post plasma oxidation compared to the control sample with only post plasma oxidation processed, see Fig.1. In addition, DADA processed samples without additional post plasma oxidation (6) resulted in very high leakage. The impact of post plasma oxidation and DADA on the electrical and physical characteristics of the Hf based dielectrics will be discussed in detail.

(Invited) Silicene: Silicon at the Two Dimensional Limit and Its Applications to Nanoelectronics

The evolution of semiconductor nanoelectronics demands for a progressive miniaturization of the device feature size. Downscaling the silicon channel down to the ultra-thin film regime is a current trend in the semiconductor technology roadmap for digital devices such as ultra-thin body silicon-on-insulator field (UTB-SOI) or Fin field effect transistors. Future technology nodes are to require a turning point in the choice of alternative semiconductors replacing silicon. One approach is to make use of mobility boosters such as germanium or III-V’s in order to overcome the physical limits of silicon in the CMOS technology. However, new emerging materials are yet to come which imply a reduced dimensionality of the silicon channels (see the Figure below for a silicon roadmap).[1] This route inspired the concept of silicene as a silicon at the extreme two-dimensional (2D) limit. Silicene can be thought of as a structural analogue of graphene as well as a graphene follower in the periodic table. Silicene has recently attracted a tremendous attraction for its potential to bring the current silicon technology down to an ultimate thickness limit. Apart from the technology drivers, the existence of a silicene monolayer paves the way to the exploration of new exotic physical effecs such as the quantum spin Hall effect in an elementary crystal and to a new class of 2D materials, the so-called Xenes (X denoting other group IV semiconductors such as Ge and Sn). Despite the natural tendency of silicon to hybridize sp3 instead of sp2as carbon in graphene, the concept of silicene was previously proposed in its theoretical terms as a pseudo planar free-standing lattice. However, unlike graphene, silicene is not free-standing in nature. Silicene can be artificially forced to grow upon epitaxy on substrates with a commensurate surface lattice. The details of the silicene epitaxy are reported from the monolayer to the multilayer regime taking the growth onto Ag(111) substrates as paradigmatic example.[2] According to the ideal case of free-standing silicene, the epitaxial silicene is buckled in nature and can be grown in number of differently buckled phase depending on the growth temperature and the deposition rate. A full exploitation of silicene for device applications is hurdled by stability issues at its top and bottom interfaces. At its top interface, silicene is highly reactive under environmental condition thereby suffering from fast structural degradation and oxidation. Encapsulation with an Al2O3 ultra-thin capping films is shown to prevent silicene from degradation thus allowing for ex situ characterization and further processing steps. At the bottom interface of silicene is the hosting substrate. Previously studied hosting substrates are metallic in character, serve as stabilizers for the silicene lattice and strongly interact with it thereby suppressing the formation of Dirac cones in the silicene band structure and ultimately causing a metallization of the silicene itself. The latter fact is a detrimental obstacle for silicene handling. Two approaches are outlined to bypass this drawback. A) On one hand, a methodology for the silicene encapsulation, delamination, and isolation is presented as enabling technology for device integration. The key-point is this procedure relies on the use of epi-Ag(111) film on mica as cleavable substrates for the silicene epitaxy. A silicene-based transistor can be then fabricated by patterning the native Ag as source/drain contacts of a pure silicene channel.[3] Room temperature operation of field effect transistor incorporating silicene monolayer and multilayer as active channel materials is demonstrated. The observation of an ambipolar behavior in the transistor transfer curves turns out to be the electrical hallmark of silicene. B) On the other hand, template engineering is also explored as alternative approach to create a metal-free platform for the technological implementation of silicene. As a representative case, the epitaxy of silicene on MoS2 templates is reported and the electronic band alignment between the two terms described. [4] Silicene-on-MoS2 is then integrated into a heterosheet junction transistor making evidence of an effective electrical transport at the Si/MoS2interface. Possible advances in the functionalization of silicene are discussed which pave the way to a multifunctional applications based on the same silicene platform. Finally, an outlook of silicene contemporaries, germanene, stanene, etc., is proposed aiming at the exploitation of their non-trivial topological properties in nanoelectronics. [1] “2D Materials for Nanoelectronics”, Eds. M. Houssa, A. Dimoulas, A. Molle, CRC Press, Taylor&Francis Group, 2016 Boca Raton, FL [2] C. Grazianetti, E. Cinquanta, and A. Molle, 2D Materials 3, 012001 (2016) (Topical Review). [3] L. Tao, et al., Nature Nanotech. 10, 227 (2015). [4] A. Molle, et al., Adv. Mater. Interf. (2016), DOI: 10.1002/admi.201500619. Figure 1

A new analytical electro-thermal model in 3D resistive switching memory arrays

Resistive switching memory (RRAM) with three-dimensional (3D) integration is one of the most effective methods to satisfy the requirement of ultra-high density and ultra-large data storage. With the increase of the integration density of 3D RRAM, Joule heating effect and thermal crosstalk of the RRAM device will seriously affect the stability, reliability and life of RRAM device. Therefore, the biggest challenge for 3D RRAM is how to solve the problem of the thermal effect. Otherwise, the thermal effect will be particularly prominent as the feature size of RRAM device is ceaselessly decreased. Especially with the improving of the storage cell densities and hence the decreasing of the distance between adjacent cells, the thermal crosstalk from the adjacent cells will seriously restrict the development and application of 3D integrated RRAM. In this work, we present a new electro-thermal compact model for 3D RRAM arrays. The proposed model is based on the electro-thermal analogy which can couple thermal network to its electrical schematic. The comparison between the compact model simulation results and numerical simulation shows a good accuracy. This proposed model can be used to predict temperature distribution and analyze thermal crosstalk in 3D RRAM arrays. Our work will provide a reliable technical support for the late circuit design and practical application, and lay the foundation for the realization of the high-density 3D integration RRAM.

Piezo-Phototronic Effect in a Quantum Well Structure.

With enhancements in the performance of optoelectronic devices, the field of piezo-phototronics has attracted much attention, and several theoretical works have been reported based on semiclassical models. At present, the feature size of optoelectronic devices are rapidly shrinking toward several tens of nanometers, which results in the quantum confinement effect. Starting from the basic piezoelectricity equation, Schrödinger equation, Poisson equation, and Fermi's golden rule, a self-consistent theoretical model is proposed to study the piezo-phototronic effect in the framework of perturbation theory in quantum mechanics. The validity and universality of this model are well-proven with photoluminescence measurements in a single GaN/InGaN quantum well and multiple GaN/InGaN quantum wells. This study provides important insight into the working principle of nanoscale piezo-phototronic devices as well as guidance for the future device design.

Electrostatic risk to reticles in the nanolithography era

Reticles can be damaged by electric field as well as by the conductive transfer of charge. As device feature sizes have moved from the micro- into the nano-regime, reticle sensitivity to electric field has been increasing owing to the physics of field induction. Hence, the predominant risk to production reticles today is from exposure to electric field. Measurements of electric field that illustrate the extreme risk faced by today’s production reticles are presented. It is shown that some of the standard methods used for prevention of electrostatic discharge in semiconductor manufacturing, being based on controlling static charge and voltage, do not offer reticles adequate protection against electric field. In some cases, they actually increase the risk of reticle damage. Methodology developed specifically to protect reticles against electric field is required, which is described in SEMI Standard E163. Measurements are also presented showing that static dissipative plastic is not an ideal material to use for the construction of reticle pods as it both generates and transmits transient electric field. An appropriate combination of insulating material and metallic shielding is shown to provide the best electrostatic protection for reticles, with fail-safe protection only being possible if the reticle is fully shielded within a metal Faraday cage.

Nanoscale on-chip all-optical logic parity checker in integrated plasmonic circuits in optical communication range.

The nanoscale chip-integrated all-optical logic parity checker is an essential core component for optical computing systems and ultrahigh-speed ultrawide-band information processing chips. Unfortunately, little experimental progress has been made in development of these devices to date because of material bottleneck limitations and a lack of effective realization mechanisms. Here, we report a simple and efficient strategy for direct realization of nanoscale chip-integrated all-optical logic parity checkers in integrated plasmonic circuits in the optical communication range. The proposed parity checker consists of two-level cascaded exclusive-OR (XOR) logic gates that are realized based on the linear interference of surface plasmon polaritons propagating in the plasmonic waveguides. The parity of the number of logic 1s in the incident four-bit logic signals is determined, and the output signal is given the logic state 0 for even parity (and 1 for odd parity). Compared with previous reports, the overall device feature size is reduced by more than two orders of magnitude, while ultralow energy consumption is maintained. This work raises the possibility of realization of large-scale integrated information processing chips based on integrated plasmonic circuits, and also provides a way to overcome the intrinsic limitations of serious surface plasmon polariton losses for on-chip integration applications.

Single event upsets sensitivity of low energy proton in nanometer static random access memory

Low-energy protons are able to generate enough energy through direct ionization to cause a high single event upset cross section as the feature size of semiconductor devices shrinks. It poses a large challenge on the present proton single event modeling test technique and the space upset rate prediction method. Experimental study of proton single event effect in three different feature sizes of static random access memory (SRAM) (i.e. 65 nm, 90 nm, and 250 nm) is carried out based on domestic low-energy proton accelerators and also the foreign middle-high proton accelerators. Complete cross section curves of proton single event upset from low energy to high energy are acquired. Test results show that single event upset cross section below 1 MeV proton is up to three orders of magnitude higher than the saturation cross section of high-energy proton in nanometer SRAM. However, single event upset is not observed for protons below 3 MeV in 250 nm SRAM, and no single event multiple-cell upsets occur for protons below 1 MeV in 90 nm and 65 nm SRAM. The accurate geometrical structure model of composite sensitive volume is constructed through the combination of test data with device information, and calibrated further by single event test data of low-LET heavy ion and high-energy proton. Simulation results based on the model and Monte-Carlo calculation can reveal the root cause of low-proton single event upset cross section peak. Proton single event upsets are only caused through direct ionization of protons below 1 MeV. When low-energy protons pass through the multiple metallization and passivation layers of the device, the energy spectrum is broadened near the Bragg peak of the proton direct ionization, and the energy is deposited concentratedly into the sensitive volume through direct ionization. When the proton energy is too high or too low, the energy can not be deposited effectively into the sensitive volume through direct ionization. The energy spectrum straggling of low-energy protons due to the use of degrader has a large influence on the height and width of the single event upset cross section peak. Moreover, the contribution of low protons to the space proton single event upset rate is predicted for GEO orbit environment in the worst day environment. It shows that the direct ionization from low energy dominates the proton single event upset rate in the space in 65 nm SRAM. With the development of device technology, the critical charge of single event upset will be further reduced; and to the single event upset from low proton direct ionization more attention must be paid in the study and evaluation of single event effect.

Experimental study of multilayer SiCN barrier film in 45/40 nm technological node and beyond

With feature size of device scaled down 45nm technological node and beyond, the backend of the line (BEOL) faces too many problems such as resistance–capacitance (RC) delay, crosstalk noise, and power consumption. In order to improve RC delay, the SiCN dielectric constant had to further decrease through introducing C2H4 gas to increase its carbon content. The SiCNkI (k~5.3) and SiCNkII (k~3.8) were characterized by spectroscopic ellipsometer, fourier transform infrared spectroscopy (FTIR), Rutherford backscattering spectrometry–hydrogen forward scattering (RBS–HFS), X-ray reflectivity (XRR), Hg probe, four point bending (4-PB) test, scanning electron microscope (SEM), and transmission electron microscope (TEM). Results indicated that the hardness and modulus and density of the SiCNkII were lower than that of the SiCNkI. RBS–HFS and FTIR examination indicated that SiCNkII barrier film had high carbon content and terminating CH3 group to cause low cross-linking and density of dielectric films resulting in large volume. 4-PB test combined with transmission electron microscope (TEM) examination demonstrated that the crack occurred in the interface between SiCNkII film/SiCNkI bilayer barrier film and low k film. After adding SiCNkI barrier film, no crack was found using SiCNkI/SiCNkII film/SiCNkI tri-layer barrier film. In addition, the capacitance and RC reduction ratios were improved to about 7–8% using the SiCNkII/SiCNkI bilayer barrier film.

Photonic Frequency Double-Mixing Conversion Over the 120-GHz Band Using InP- and Graphene-Based Transistors

InP-based high electron mobility transistors (InP-HEMTs) and graphene-channel FETs (G-FETs) are experimentally examined as photonic frequency converters for future broadband optical and wireless communication systems. Optoelectronic properties and three-terminal functionalities of the InP-HEMTs and G-FETs are exploited to perform single-chip photonic double-mixing operation over the 120 GHz wireless communication band. A 10 Gbit/s-class data signal on a 112.5 GHz carrier is mixed down to a 25 GHz IF band with an 87.5 GHz LO signal that is simultaneously self-generated from an optically injected photomixed beat note. The results suggest that the intrinsic channel of the G-FET can achieve a speed performance that is superior to that of an InP-HEMT having an equivalent device feature size. The reduction of the extrinsic parasitic resistances and the implementation of an efficient photo-absorption structure in the G-FET may allow a millimeter-wave and sub-THz photonic frequency conversion with a sufficiently high conversion gain for practical purposes.

Top-down delayering to expose large inspection area on die side-edge with Platinum (Pt) deposition technique

The shrinking in feature sizes of semiconductor devices from integrated circuit (IC)11Integrated circuit (IC). and function complexity has led to greater PFA22Physical Failure Analysis (PFA). delayering challenges. The challenges stem from incorporation of top thick hard Silicon Dioxide (SiO2) material that is formed from Tetra Ethyl Ortho Silicate (TEOS)33Tetra Ethyl Ortho Silicate (TEOS). as Inter-Metal Dielectric (IMD)44Inter-Metal Dielectric (IMD). and very thin ultra low-k dielectric material.For a device in copper (Cu) metal line technology, it is almost impossible to expose the entire layer at the same surface flatness by using a conventional top down polishing method, especially at the interface on TEOS and ultra low-k layer where die's side-edge is always thinner than die center (edging effect). Hence, for cases that required PFA delayering on the die side-edge especially for those packaged device or skeleton die, it is extremely challenging for PFA skillset.This paper outlines a proposed technique; perform Platinum (Pt) deposition on the selective area to slow down the side-edging effect. This proposed technique is easy and less skillset dependent to deprocess sample for defect identification analysis.

Thermal Decomposition of Tungsten Nitrido Precursors for Low Temperature MOCVD of WNxCy

As the feature size of electronic devices continues to shrink, the integrated circuit device density increases. This not only modifies the RC time delay to severely limit the device performance, but also places increased demand on Cu metallization effectiveness (1). The extremely high diffusivity of Cu in Si and its ‘killer’ effect on devices has led to the requirement of a barrier layer to prevent Cu transport into the underlying Si. Among various candidates, W-based nitrides have shown promise as replacements of current barrier layers due to their good thermal stability, low resistivity, and the possibility of one-step CMP with Cu slurry (2, 3). In addition, a single barrier layer process is simpler than the Ta-based barrier layer, which needs a double layer of TaN and Ta. The performance of W-based nitrides increases when they are alloyed with carbide to make WNxCy due to its higher crystallization temperature and possibility to adjust film resistivity to lower values. The tungsten nitrido complex WN(NMe2)3 was demonstrated to serve as a single-source precursor for metal organic chemical vapor deposition (MOCVD) of WNxCy films at temperatures as low as 125 ˚C (4). The goal of this study is to understand decomposition mechanisms and their kinetics for the WN(NMe2)3 precursor, and furthermore, to optimize conditions for deposition of the WNxCy film. To elucidate the mechanism and kinetics of thermal decomposition of WN(NMe2)3, in-situ Raman spectroscopy was used to quantitatively measure the disappearance of precursor and appearance of products. An up-flow, cold-wall MOCVD reactor was designed to perform Raman scattering experiments along the centerline of the reactor (5). The system design allows the CVD reactor to translate along three-dimensionally, to permit the laser to focus on any spot in the reactor. In-situ Raman experiments were performed using a heater set point temperature of 650 ˚C. Axial centerline temperature profiles in the reactor are measured by analysis of the rotational bands of the diatomic N2 carrier gas. Due to the low volatility of the precursor, it was dissolved in liquid pyridine and delivered to the reactor as an aerosol with N2 carrier gas (6). The 532 nm line of a Nd:YVO4 solid-state laser at 1.5 W was used as the light source to excite the molecules in the sample. Raman spectra were measured at various distances below the heated susceptor surface and thus various temperatures from 159 ˚C to 474 ˚C. Density Functional Theory (DFT) calculations (using the B3LYP functional and LanL2DZ basis sets) were performed to assess possible pathways of thermal decomposition of WN(NMe2)3 and to assign observed Raman peaks to the decomposition products. The results of this study are consistent with proposed mechanistic steps for the thermal decomposition of the precursor, including dimerization of the precursor and loss of the amine. In addition to gas phase data, liquid phase Raman experiments were performed to better define additional species that are Raman active but not detected in the lower density gas phase experiments and to find vibrational frequencies before the molecule is decomposed.

Dual-Fluid Spray Process for Particle and Fluorocarbon-Polymer Removal in BEOL Applications

Introduction Recently the feature size of devices has decreased to <20nm, so the manufacturing process has become more complicated since the number of steps for the pattern technology and its complexity have increased. One of the most critical challenges for BEOL is a post-etch-residue cleaning in the trenches and vias. Not only the chemical step but also rinse step is required to completely remove fluorocarbon-based polymer residue (CF-polymer residue) in the structure. Conventional dual-fluid spray is widely used to improve the cleaning efficiency; however, it has not been used on advanced fragile structures because the physical force can easily induce pattern damage. According to a previous paper, smaller droplets at higher velocity are required to reduce pattern damage and to increase particle removal efficiency [1]. In addition, the spray should be able to dissolve the residue. In this paper, we have demonstrated a dual-fluid spray with chemical additive that dissolves the residue and has less pattern damage as an alternative rinse process. Experimental procedures In order to study the characteristics between de-ionized water (DIW) and its chemical additive (Chem. A), a Dynamic Direct Injection system that can mix them at point-of-use and Nanospray as a dual-fluid spray were used. Particle removal efficiency (PRE), CF-polymer removal efficiency (RRE) and distribution of droplets (size and velocity) were investigated. All tests were carried out with DIW, Chem. A and DIW-Chem. A mixtures in a conventional spin processor. (1) SiN PRE vs. pattern damage The number of removed particles was evaluated by an intentional contamination with 45- nm SiN particles on hydrophilic silicon wafer and measured by KLA SP-2. Pattern wafers with aspect ratio 6~7 were prepared as damage test samples. The pattern damage after Nanospray was counted by SEM observation. (2) Residue removal efficiency (RRE) CF-polymer (2x2 cm spots at 37-40 nm thick) was intentionally deposited on low-k material as a test vehicle. The polymer removal efficiency was evaluated by ATR-FTIR spectroscopy. (3) Distribution of droplets (size and velocity) The size (diameter) and velocity of droplets were measured by a droplet measurement system consisting of a laser, high speed camera and image processor. Results and Discussion (1) SiN PRE vs. Pattern damage Fig. 1 shows result of SiN PRE and pattern damage as a function of several Nanospray conditions. The PRE of 100% Chem. A decreased from 50% to 20% compared to DIW; however, its additive mixtures (20% and 40%) showed almost the same PRE as DIW Nanospray. On the other hand, pattern damage was significantly reduced with increasing Chem. A concentration. (2) CF polymer-RRE As shown in Fig. 2, CF-polymer indicates absorbance of functional groups such as C-C, C=O and C-F at the range of 1500 ~ 1900 cm-1. The absorbance of additive mixtures (20% and 40%) or Chem. A Nanospray indicates lower intensity than DIW Nanospray which enables the removal of the CF-polymer by adding Chem. A. (3) Droplets distributions Fig. 3 shows distribution of droplet size as a function of Chem. A concentration. Droplets of DIW Nanospray were widely distributed in size range from 2 to 38µm. In contrast, droplets of Chem.A or its additive mixture Nanospray were much narrower distributed with increasing Chem. A concentration, more than 40% Chem. A Nanospray was achieved in size range from 2 to 17µm.By the addition of the Chem.A to the water, droplet size is decreased than DIW by the role of the surfactant of Chem.A. Therefore, the distribution of large droplets with high kinetic energy decreased and resulted in reduced pattern damage. Conclusions Dual-fluid spray process for post-etch-residue cleaning was developed. An optimized process could enable simultaneous higher PRE and CF-polymer RRE. The additive made smaller droplet size and higher velocity in addition to excellent CF-polymer dissolved characteristics compared to conventional DIW Nanospray.

Focused Ion Beam Milling Technique for Plan-View TEM Sampling of DRAM Capacitor

As the semiconductor device feature size becomes smaller, the aspect ratio of DRAM capacitor gets higher. The higher the height of capacitor, the more storage node bent. Therefore, we adopt the Mechanically Enhanced Storage node for virtually unlimited Height (MESH) [1] process to prevent storage node’s bending nowadays. Nevertheless, the bending failure still exists, and thus we need to make a sample for physical failure analysis (PFA). Normally PFA needs a site specific transmission electron microscopy (TEM) sample which is vertically cross-sectioned by using focused ion beam (FIB) , but sometimes a plan-view TEM sample is also required to clarify the exact cause of failure. Figure 1-(a) shows the vertical TEM result of two bits failure caused by DRAM storage node’s bending. In the conventional plan-view TEM sampling process, the target height for plan-view TEM sampling is marked with ‘l’ shape marker [2] after realizing the height of node bridge as shown in figure 1-(b). It is important to know the end point during FIB milling [3]. And then, the top (red area) and bottom (yellow area) parts are removed to get the plan-view TEM sample. Figure 1-(c) is a TEM image after this plan-view TEM sampling process. The nodes do not stand in a line as you see in figure 1-(c). The nodes seem to move during the 3rd step milling (mill a bottom part) because of the void between nodes. The node may fall off a TEM thin foil sample in the worst case. In order to overcome this problem, we add a carbon deposition step right after the 2nd step of the top part milling as shown in figure 2-(a). As a result, we are able to get a plan-view TEM image where the nodes stand in a line as shown in figure 2-(b). Four major steps are, Step 1 : ‘1’ shape marking at the target height Step 2 : milling a top part of capacitor Step 3 : carbon deposition to fill the space between nodes Step 4 : milling a bottom part of capacitor We adopted this modified milling method to the TEM sampling of a real failure case and obtained a PFA result of a 2 bit failure using plan-view TEM image as shown in figure 2-(c). The new modified milling method turned out to be very effective and can be adopted in a mass production.

ChemInform Abstract: Magnetic and Charge Ordering in Nanosized Manganites

AbstractReview: 107 refs.