Memory Faults Research Articles

A March Test for Functional Faults in Semiconductor Random Access Memories

A test procedure requiring 14 N operations to detect functional faults in semiconductor random access memories (RAM's) is given. It is shown that the proposed test procedure detects modeled types of functional faults if only one type of fault is present in the RAM under test. The test procedure given belongs to a class of tests called march tests. It is proved that any march test requires at least 14 N operations to detect the modeled faults. Next, groups of different types of functional faults that can be simultaneously present in the RAM under test and yet be detected by the proposed test procedure or a given enhanced test procedure (requiring 16 N operations) are studied.

A Graph Model for Pattern-Sensitive Faults in Random Access Memories

This correspondence generalizes Hayes' recent ideas for generating an optimal transition write sequence which forms the backbone of his algorithm for testing semiconductor RAM's for pattern-sensitive faults. The generalization, presented in graph theoretic terms, involves two sequential steps. The frmst step results in assigning of a to each memory cell. In the second step, each color is defined as a distinct sequence of bits representing the sequence of states assumed by the correspondingly colored cell. The constraints imposed at each step lead to interesting and general problems in graph theory: the standard graph coloring problem in the first step, and a path projection problem from a binary m-cube to a subcube in the second step. Applications to arbitrary k-cell neighborhoods, and particularly to three-cell neighborhoods are shown.

Check sum computer memory fault detection: C. A. Pell. Proc. CNET Conference on Reliability and Maintainability, Tregastel, France p. 38 (8–12 September 1980)

Check sum computer memory fault detection: C. A. Pell. Proc. CNET Conference on Reliability and Maintainability, Tregastel, France p. 38 (8–12 September 1980)

Test Procedures for a Class of Pattern-Sensitive Faults in Semiconductor Random-Access Memories

A class of pattern-sensitive faults in semiconductor random-access memories are studied. Efficient test procedures to detect and locate modeled faults are presented.

Comments on "An Optimal Algorithm for Testing Stuck-at Faults in Random Access Memories"

An efficient, optimal test sequence for detecting multiple stuck-at faults in random access memories (RAM's) for any decoder implementation is presented. Another algorithm which does not assume any particular wired logic behavior of simultaneously accessed storage locations, is also presented.

Quality test of semiconductor memories by jitter measurement

This letter states the results form the application of a jitter measuring method suited to the quality testing of electronic semiconductor memories. A description is given of a jitter measuring apparatus which enables detection of latent defects in semiconductor memories.

Erasure and Error Decoding for Semiconductor Memories

In this paper we introduce and evaluate error correction methods which takes into account the special properties of failure modes in semiconductor memories. We assume that the memory faults are of the type stuck-to 1 or 0. Thus the fault, once it has occurred, is located to a specific position in a memory word. The position may be found and this fact makes it convenient to use erasure correction, rather than random error correction.

Efficient Algorithms for Testing Semiconductor Random-Access Memories

A fault model which views faults in semiconductor random-access memories at a functional level instead of at a basic gate level is presented. An efficient 0(n) algorithm to detect all faults in the fault model is described. The fault model is then extended to incorporate more complex faults. An 0(n · log2 n) algorithm is presented for one such extended fault model.

A Fault Tolerant Memory For Duplex Systems

A fault-tolerant memory design uses modular bit swapping to achieve high system availability with minimum redundancy despite high memory-device failure rates. The design permits automatic repair of multiple faults without loss of error detection, thereby allowing deferral of manual repair. Although the design was directed toward use in a duplex system, the technique potentially applies to simplex systems. Double-bit swapping and 4096-word modules were chosen for this system. With a 64k memory, 18 memory device faults would occur in its 40-year life. The number of instances of manual repair will average 3; the number of faults in the system when manual repair is required will average 6. Similarly, with a 1024k memory, 288 memory faults would occur in its 40-year life. The number of instances of manual repair will average 20 and the number of faults in the system when manual repair is required will average 14.

An Optimal Algorithm for Testing Stuck-at Faults in Random Access Memories

This correspondence presents an optimal algorithm to detect any single "stuck-at-i," "stuck-at-O" fault and any combination of "stuck-at-I," "stuck-at-O" multiple faults in a random access memory using only the n-bit memory address register input and m-bit memory buffer register input and output lines. It is shown that this algorithm requires 4 X 2n memory accesses.

An Algorithm for Testing Random Access Memories

This correspondence presents an optimal algorithm to detect any single stuck-at-1 (s-a-1), stuck-at-0 (s-a-0) fault in a random access memory using only the n-bit memory address register input and m-bit memory buffer register input and output lines. It is shown that this algorithm requires 4 X 2nmemory accesses.

Detection oF Pattern-Sensitive Faults in Random-Access Memories

Some formal models for pattern-sensitive faults (PSF's) in random-access memories are presented. The problem of detecting unrestricted PSF's is that of constructing a checking sequence for the memory. An efficient procedure for constructing such a checking sequence is presented. A local PSF is defined as a PSF where the faulty behavior of a memory cell C i depends on a fixed group of cells called the neighborhood of C i . Neighborhoods are divided into two classes, open and closed. Test generation methods are described for local PSF's defined on both open and closed neighborhoods. The detection of PSF's when only one memory cell is faulty (single PSF's) is also discussed.

On Optimization of Storage Hierarchies

A simple model of the storage hierarchies is formulated with the assumptions that the effect of the storage management strategy is characterized by the hit ratio fqnction. The hit ratio function and the device technology-cost function are assumed to be representable by power functions (or piece-wise power functions). The optimization of this model is a geometric programming problem. An explicit formula for the minimum hierarchy access time is derived; the capacity and technology of each storage level are determined. The opfimal number of storage levels in a hierarchy is shown to be directly proportional to the logarithm of the systems capacity with the constant of proportionality dependent upon the technolagy and hit ratio characteristics. The optimal cost ratio of adjacent storage levels is constant, as are the ratios of the device access times and storage capacities of the adjacent levels. An illustration of the effect of overhead cost and level-dependent cost, such as the cost per box and cos for managing memory faults is given and several generalizations are presented.

Fault Tolerant Sequential Machines

A machine representation of permanent memory faults is introduced where, if M is a sequential machine representing some fault free system, a memory fault is represented by a function μ on the states of M, and the result of the fault by an appropriately determined machine M <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">μ</sup> . Given this representation, the investigation is primarily concerned with faults that are tolerated (masked) in the sense that resulting behavior relates in some specified way to original behavior. Several types of fault masking are thus considered and conditions for their existence investigated. The restriction to a special class of stable faults is also studied, this class being of interest since it includes all faults which correspond to "stuck-at" failures in the memory cells of a sequential switching network.