Fault-tolerant Routing Algorithm Research Articles

A Novel Low-Latency Regional Fault-Aware Fault-Tolerant Routing Algorithm for Wireless NoC

WiNoC has become a promising on-chip interconnect architecture. Due to the integration and manufacturing limits of wireless interconnects in nanotechnology, WiNoC systems are more susceptible to high failure rates. In this paper, we propose a novel fault-tolerant routing algorithm based on regional fault-aware techniques for link failures in WiNoC. We trade off performance and overhead by adopting 2-hop awareness for wireless nodes and 1-hop awareness for wired nodes. And the node status is not defined merely based on its own faulty condition but with a “double sensing” mechanism. Besides, since congestion is prone to occur around faulty nodes, we consider congestion mitigation in fault-tolerant algorithm design. Simulation results demonstrate that compared with several counterparts, the performance benefits clearly overweigh the overhead with acceptable area increase. The newly proposed routing algorithm significantly enhances the robustness of the system.

Towards fault adaptive routing in metasurface controller networks

Abstract HyperSurfaces (HSFs) comprise structurally reconfigurable metasurfaces whose electromagnetic properties can be changed via a software interface, using an embedded miniaturized network of controllers, enabling novel capabilities in wireless communications, including 5G applications. Resource constraints associated with a hardware testbed of this breakthrough technology, currently under development, necessitate an interconnect architecture of a Network of Controllers (CN) that is distinct from, yet reminiscent to, those of conventional Network-on-Chip (NoC) architectures. To meet the purposes of our HSF testbed, we rationalize the construction of an irregular topology where its controllers are interconnected in a Manhattan-like geometry, with the flow of control directives conducted in a handshaking mode, and routing operated by an XY-YX algorithm that is agnostic of the CN connectivity, determined following the results of model specification and model checking techniques. With such controllers prone to the appearance of permanent faults, threatening the operation of such HSFs, we propose, develop and evaluate two fault adaptive routing algorithms aiming to enhance the successful delivery of packetized control directives to their recipients: (1) Loop Free Algorithm (LFA), and (2) Reliable Delivery Algorithm (RDA) of deterministic and probabilistic variants. LFA and RDA are developed based on utilizing said topology-agnostic XY-YX routing algorithm as a base, along with an appropriate adoption of routing turn rules, to address said HSF CN challenges that deviate from traditional fault tolerant routing algorithms seen in NoCs. Experimental evaluation results obtained using a custom developed simulator, show that probabilistic RDA exhibits top performance in terms of successful packet delivery ratio and topology coverage, albeit at the expense of a higher path hop count. Pointers in addressing tradeoffs between HSF CN performance and resource utilization are also provided.

Fault tolerant and congestion aware routing algorithm for network on chip1

Fault tolerant and congestion aware routing algorithm for network on chip1

A New Fault Tolerant Routing Algorithm for Networks on Chip

To provide correct data transmission and to handle the communication requirements, the routing algorithm should find a new path to steer packets from the source to the destination in a faulty network. Many solutions have been proposed to overcome faults in network-on-chips (NoCs). This article introduces a new fault-tolerant routing algorithm, to tolerate permanent and transient faults in NoCs. This solution called DINRA can satisfy simultaneously congestion avoidance and fault tolerance. In this work, a novel approach inspired by Catnap is proposed for NoCs using local and global congestion detection mechanisms with a hierarchical sub-network architecture. The evaluation (on reliability, latency and throughput) shows the effectiveness of this approach to improve the NoC performances compared to state of art. In addition, with the test module and fault register integrated in the basic architecture, the routers are able to detect faults dynamically and re-route packets to fault-free and congestion-free zones.

A self-adaptive and fault-tolerant routing algorithm for wireless sensor networks in microgrids

Abstract With the expanding development of power grids, a microgrid is proposed, which is located on the edge of the entire grid. The edges of wireless sensor networks (WSNs) in a MG are in edge computing environments. For initialization, we propose an edge-adaptive and fault-tolerant routing algorithm. The routing is constructed using particle swarm optimization and consists of the inter-cluster structure and the intra-cluster structure. To improve stability, we take the distance, energy and traffic into account. The cluster head nodes are adaptive and adjust their communication ranges according to the network conditions and the current load. In addition, we also consider the failure of sensors. The sensors can address accidental malfunctions autonomously and quickly. Finally, we evaluate the performance of the algorithm through the simulation. The algorithm proposed in this paper shows better performance than other existing algorithms.

HSDC: A Highly Scalable Data Center Network Architecture for Greater Incremental Scalability

As the volume of data keeps growing rapidly, more and more storage devices, servers and network devices are continuously added into data centers to store, manage and analyze the data. The industry experience indicates that, instead of a huge number of servers added at a time, the data center network also expands gradually by adding a small number of servers from time to time. As a result, how to achieve an incremental scalability is becoming a very important challenge in designing modern data center network architectures in order to maintain the topological properties unchanged when the size of data centers grows. In this paper, we propose a new type of data center network architecture named HSDC (High Scalability Data Center Network Architecture) based on the hypercube network. The HSDC is constructed by using $m$m-port switches and 2-port servers. The fault-tolerant routing algorithm designed in this paper for HSDC can be executed on any vertex and is able to construct a path between any pair of vertices. In order to achieve an incremental scalability, we further propose three types of incomplete HSDC structures that allow gradually adding servers into the structures, while maintaining all the topological properties. The simulation experiments and performance results demonstrate that the throughput of HSDC is comparable to that of Fat-Tree, BCube and DCell. Furthermore, the analysis results indicate that HSDC strikes a good balance among diameter, bisection width, incremental scalability, cost and energy consumption in contrast to the state-of-the-art data center network architectures.

Latency, Throughput and Power Aware Adaptive NoC Routing on Orthogonal Convex Faulty Region

Reliability of a Network-on-Chip (NoC) relies vastly upon the efficiency of handling faults. Faults those lead to trouble during on-chip communication process are basically of two types namely soft and hard. Here, hard faults are considered. Hard faults may be caused due to failure of links, routers, or other processing units. These are mainly dealt with fault-tolerant routing algorithms or by employing redundant hardware. Multiple faulty nodes are being avoided by acquiring region-based approaches. Most of the fault-tolerant routing techniques are designed on homogeneous faulty regions where some active nodes also act as deactivated nodes to build the region homogeneous. On the other hand, adaptive routing on nonhomogeneous faulty regions increases load on its boundary and most of them does not assure deadlock freeness. This paper proposes a deadlock-free adaptive fault-tolerant NoC routing named F-Route-NoC-Mesh (FRNM) ignoring any virtual channel on orthogonal convex faulty regions. Contributions of this work focus on balancing network traffic by assuming a virtual faulty block boundary and routing packets through this virtual boundary. Destination does not exist within that virtual faulty block regions to reduce load on the boundary of orthogonal faulty regions. Thus, this work is aimed at acquiring proper incorporation of procedures being able to reach fault-tolerant degree, routing efficiency and performance enhancement. Using the proposed algorithm (FRNM), a fault block model-based approach is developed. Significant improvements of average latency (43.37% to 60.44%), average throughput (4.18% to 90.81%) and power consumption (5.93% to 33.28%) are achieved over the state-of-the-art by using a cycle accurate simulator.

Fault-Tolerant Adaptive Routing in Dragonfly Networks

Dragonfly networks have been widely used in the current high-performance computers or high-end servers. Fault-tolerant routing in dragonfly networks is essential. The rich interconnects provide good fault-tolerance ability for the network. A new deadlock-free adaptive fault-tolerant routing algorithm based on a new two-layer safety information model, is proposed by mapping routers in a group, and groups of the dragonfly network into two separate hypercubes. The new fault-tolerant routing algorithm tolerates static and dynamic faults. Our method can determine whether a packet can reach the destination at the source by using the new safety information model, which avoids dead-ends and aimless misrouting. Sufficient simulation results show that the proposed fault-tolerant routing algorithm even outperforms the previous minimal routing algorithm in fault-free networks in many cases.

FL-RuNS: A High-Performance and Runtime Reconfigurable Fault-Tolerant Routing Scheme for Partially Connected Three-Dimensional Networks on Chip

Three-dimensional networks on chip (3D-NoCs) have been proposed as an enormously scalable solution to address communication problems in modern systems on chip. Through-silicon via (TSV) is usually adopted as a viable technology enabling vertical connection among NoC layers. However, TSV-based architectures typically exhibit high vulnerability to transient and permanent faults caused by aging effects, thermal violations, manufacturing issues, or even transient fault sources. Therefore, TSV-based architectures call for robust routing schemes capable of sustaining operation under unpredictable failure patterns. In this paper, we introduce FL-RuNS, a fault-tolerant routing scheme for achieving 100% packet delivery under an unconstrained set of runtime and permanent vertical link failures. The proposed scheme uses the concept of vertical link announcement to inform nodes in the network of the health condition of vertical links. This mechanism is able to dynamically and progressively reconfigure the entire network without any packet loss. FL-RuNS requires a very low number of asymmetric virtual channels to achieve both deadlock freedom and reachability. Also, FL-RuNS introduces one-flit-dedicated virtual channels, which are used as an escape buffer in case of TSVs failures. The experimental results have confirmed that FL-RuNS shows better reliability when compared to the recently proposed fault-tolerant routing algorithm. Furthermore, the hardware synthesis performed using a commercial 28-nm technology library shows a reasonable area and power overhead with respect to the non-fault-tolerant baseline.

Fault-Tolerant Unicast-Based Multicast for Reliable Network-on-Chip Testing

We present a unified test technique that targets faults in links, routers, and cores of a network-on-chip design based on test sessions. We call an entire procedure, that delivers test packets to the subset of routers/cores, a test session. Test delivery for router/core testing is formulated as two fault-tolerant multicast algorithms. Test packet delivery for routers is implemented as a fault-tolerant unicast-based multicast scheme via the fault-free links and routers that were identified in the previous test sessions to avoid packet corruption. A new fault-tolerant routing algorithm is also proposed for the unicast-based multicast core test delivery in the whole network. Identical cores share the same test set, and they are tested within the same test session. Simulation results highlight the effectiveness of the proposed method in reducing test time.

BCDC: A High-Performance, Server-Centric Data Center Network

The capability of the data center network largely decides the performance of cloud computing. However, the number of servers in the data center network becomes increasingly huge, because of the continuous growth of the application requirements. The performance improvement of cloud computing faces great challenges of how to connect a large number of servers in building a data center network with promising performance. Traditional tree-based data center networks have issues of bandwidth bottleneck, failure of single switch, etc. Recently proposed data center networks such as DCell, FiConn, and BCube, have larger bandwidth and better fault-tolerance with respect to traditional tree-based data center networks. Nonetheless, for DCell and FiConn, the fault-tolerant length of path between servers increases in case of failure of switches; BCube requires higher performance in switches when its scale is enlarged. Based on the above considerations, we propose a new server-centric data center network, called BCDC, based on crossed cube with excellent performance. Then, we study the connectivity of BCDC networks. Furthermore, we propose communication algorithms and fault-tolerant routing algorithm of BCDC networks. Moreover, we analyze the performance and time complexities of the proposed algorithms in BCDC networks. Our research will provide the basis for design and implementation of a new family of data center networks.

A Swarm Intelligence Algorithm for Routing Recovery Strategy in Wireless Sensor Networks With Mobile Sink

Considering the fault tolerance mechanism in the route optimization of the mobile wireless sensor network (MWSN), we analyze the routing fault tolerance between nodes and establish an intelligent fault-tolerant routing model for MWSN. We also propose a novel fault-tolerant routing algorithm for an MWSN based on an artificial bee colony (ABC) optimized particle swarm optimization algorithm (ABC-PSO), and this optimizes the ABC-PSO algorithm is applied to study the optimal construction strategy of an alternate route. The proposed using of the path coding, the ABC algorithm optimization, the collaborative updation, and the evolution of the principal and subordinate swarms, as well as particle selection, provide faster overall convergence performance and more accurate solutions for the network optimization. Analytical proofs and simulation experiments show that the route fault-tolerant strategy proposed in this paper can create a reliable transmission environment and an efficient route recovery mechanism for the MWSN. Moreover, it can lower the energy consumption of the network and increase the network’s lifetime and improve the robustness and the reliability of MWSN.

Efficient Design-for-Test Approach for Networks-on-Chip

To achieve high reliability in on-chip networks, it is necessary to test the network continuously with Built-in Self-Tests (BIST) so that the faults can be detected quickly and the number of affected packets can be minimized. However, BIST causes significant performance loss due to data dependencies. We propose EsyTest, a comprehensive test strategy with minimized influence on system performance. EsyTest tests the data path and the control path separately. The data path test starts periodically, but the actual test performs in the free time slots to avoid deactivating the router for testing. A reconfigurable router architecture and an adaptive fault-tolerant routing algorithm are proposed to guarantee the access to the processing core when the associated router is under test. During the whole test procedure of the network, all processing cores are accessible, and thus the system performance is maintained during the test. At the same time, EsyTest provides a full test coverage for the NoC and a better hardware compatibility comparing with the existing test strategies. Under the PARSEC benchmark and different test frequencies, the execution time increases less than 5 percent at the cost of 9.9 percent more area and 4.6 percent more power in comparison with the execution where no test procedure is applied.

A Path-Counter Method for Fault-Tolerant Minimal Routing Algorithms in 2D Mesh

Fault-tolerant Manhattan routing algorithms aim at finding a Manhattan path between the source and destination nodes and route around all faulty nodes. However, besides faulty nodes, some nonfaulty nodes that are helpless to make up a fault-tolerant Manhattan path should also be routed around. How to label such nonfaulty nodes efficiently is a major challenge. We propose a path-counter method. It can label such nodes with low time-complexity by counting every node’s fault-tolerant Manhattan paths to the source or destination node. During the path-counting procedure, no available nodes will be sacrificed under arbitrary fault distribution. Compared with fault-block model based work, our proposed method is independent of fault distribution, so its computational complexity is very low.

A Fault-Tolerant Routing Algorithm Using Tunnels in Fault Blocks for Network-on-Chip

In 2D mesh Network on Chips (NoCs), fault-tolerant algorithms usually deactivate healthy nodes to form rectangular or convex fault blocks. However, the deactivated nodes can possibly form an available tunnel in a faulty block. We propose a method to discover these tunnels, and propose a fault-tolerant routing algorithm to route messages through such paths such that the overall communication performance is improved. In addition, the algorithm is deadlock-free by prohibiting some turns. Simulation results demonstrate that the reuse of the sacrificed nodes in fault blocks can significantly reduce the average message latency.

Review of Network on Chip Architectures

Background: Network on Chip (NoC) is a communication mechanism to provide scalable, modular, robust and high-performance communication for the on-chip network. Keywords: Network on Chip (NoC), link sharing, quality of service (QoS), fault-tolerant routing algorithms, switching techniques, buffer management.

Minimizing the system impact of router faults by means of reconfiguration and adaptive routing

To tolerate faults in Networks-on-Chip (NoC), routers are often disconnected from the NoC, which affects the system integrity. This is because cores connected to the disabled routers cannot be accessed from the network, resulting in loss of function and performance. We propose E-Rescuer, a technique offering a reconfigurable router architecture and a fault-tolerant routing algorithm. By taking advantage of bypassing channels, the reconfigurable router architecture maintains the connection between the cores and the network regardless of the router status. The routing algorithm allows the core to access the network when the local router is disabled.Our analysis and experiments show that the proposed technique provides 100% packet delivery in 100%, 92.56%, and 83.25% of patterns when 1, 2 and 3 routers are faulty, respectively. Moreover, the throughput increases up to 80%, 46% and 33% in comparison with FTLR, HiPFaR, and CoreRescuer, respectively.

Bio-inspired fault tolerant network on chip

The integration of heterogeneous processing elements (PEs) or nodes in the System on Chip (SoC) has made the communication structure very complex. The bus based system between these components is not able to handle the communication requirements and, this has led to the idea of Network on Chip (NoC). The NoC addresses the communication requirement of different nodes on SoC. The physical sizes of devices in NoC are scaled down, including routers, processing elements and interconnects, giving rise to faults, system delay, and latency issues. Fault tolerant routing algorithms are used to recover from temporary faults while redundant resources (wires, routers) are required to overcome the permanent faults. These routing algorithms, however, still suffer from congestion problems, low bandwidth, and throughput utilization as well as lacking adaptivity and robustness. In this work, novel biologically inspired techniques were proposed for NoC using combined best effort (BE) and guaranteed throughput (GT) services. Moreover, the bio-inspired algorithms are compared and analyzed with each other using BE, GT and combined BE-GT services. The bio-inspired mechanisms of “synaptogenesis” and “sprouting” have been adopted in the proposed NoC algorithms and architecture. These techniques were implemented using the BE and GT services. With the help of these two bio-inspired techniques, the NoC becomes robust, fault tolerant and is able to efficiently utilize the throughput and bandwidth. The bio-inspired algorithms improved the accepted traffic (flit/cycle/node) by 38.99% compared to different techniques in the literature. The bio-inspired algorithm also improved the bandwidth and throughput utilization by 71.04% and 72.42% respectively compared to the XY and Odd-Even fault tolerant routing algorithms. Moreover, the bio-inspired algorithm had less end-to-end latency and interflit arrival time by 196.44% and 88.10% respectively compared to the literature techniques of XY and Odd-Even.

Bio-inspired self-aware fault-tolerant routing protocol for network-on-chip architectures using Particle Swarm Optimization

This research paper proposes a bio-inspired self-aware fault-tolerant routing protocol for network-on-chip architecture using particle swarm optimization (PSO), which considers synchronous, asynchronous, and self-organizing communication mechanisms to intelligently load-balance the traffic on the entire network in the presence of faulty components. By way of experimentation and simulation, this study demonstrates that the proposed scheme can converge to a global optimum, minimal routing path in real time, in the presence of network congestion and faulty routers and links. The basic PSO algorithm was improved to implement the proposed routing scheme, named bio-inspired self-aware fault-tolerant routing protocol (BISFTRP). This scheme uses the synchronous, asynchronous, and self-organizing features of PSO to create a global routing table and intelligent adaptation, which gives rise to scalable, real-time, and dynamic routing decisions with high throughput, low latency, and minimum power consumption. A cycle-accurate simulation system to demonstrate the flexibility and efficiency of the proposed scheme is used. Comparison results with state-of-the-art fault-tolerant routing algorithms show that the BISFTRP routing protocol achieves high routing performance without routing oscillations and throughput degradation. Furthermore, the hardware implementation results show that the BISFTRP router achieves an efficient area and power utilization, compared with state-of-the-art routers.

Path-Diversity-Aware Fault-Tolerant Routing Algorithm for Network-on-Chip Systems

Network-on-Chip (NoC) is the regular and scalable design architecture for chip multiprocessor (CMP) systems. With the increasing number of cores and the scaling of network in deep submicron (DSM) technology, the NoC systems become subject to manufacturing defects and have low production yield. Due to the fault issues, the reduction in the number of available routing paths for packet delivery may cause severe traffic congestion and even to a system crash. Therefore, the fault-tolerant routing algorithm is desired to maintain the correctness of system functionality. To overcome fault problems, conventional fault-tolerant routing algorithms employ fault information and buffer occupancy information of the local regions. However, the information only provides a limited view of traffic in the network, which still results in heavy traffic congestion. To achieve fault-resilient packet delivery and traffic balancing, this work proposes a Path-Diversity-Aware Fault-Tolerant Routing ( PDA-FTR ) algorithm, which simultaneously considers path diversity information and buffer information. Compared with other fault-tolerant routing algorithms, the proposed work can improve average saturation throughput by 175 percent with only 8.9 percent average area overhead and 7.1 percent average power overhead.