Latency, Throughput and Power Aware Adaptive NoC Routing on Orthogonal Convex Faulty Region

Abstract

Reliability of a Network-on-Chip (NoC) relies vastly upon the efficiency of handling faults. Faults those lead to trouble during on-chip communication process are basically of two types namely soft and hard. Here, hard faults are considered. Hard faults may be caused due to failure of links, routers, or other processing units. These are mainly dealt with fault-tolerant routing algorithms or by employing redundant hardware. Multiple faulty nodes are being avoided by acquiring region-based approaches. Most of the fault-tolerant routing techniques are designed on homogeneous faulty regions where some active nodes also act as deactivated nodes to build the region homogeneous. On the other hand, adaptive routing on nonhomogeneous faulty regions increases load on its boundary and most of them does not assure deadlock freeness. This paper proposes a deadlock-free adaptive fault-tolerant NoC routing named F-Route-NoC-Mesh (FRNM) ignoring any virtual channel on orthogonal convex faulty regions. Contributions of this work focus on balancing network traffic by assuming a virtual faulty block boundary and routing packets through this virtual boundary. Destination does not exist within that virtual faulty block regions to reduce load on the boundary of orthogonal faulty regions. Thus, this work is aimed at acquiring proper incorporation of procedures being able to reach fault-tolerant degree, routing efficiency and performance enhancement. Using the proposed algorithm (FRNM), a fault block model-based approach is developed. Significant improvements of average latency (43.37% to 60.44%), average throughput (4.18% to 90.81%) and power consumption (5.93% to 33.28%) are achieved over the state-of-the-art by using a cycle accurate simulator.