Fault-tolerant Gates Research Articles

CS-count-optimal quantum circuits for arbitrary multi-qubit unitaries

In quantum computing there are quite a few universal gate sets, each having their own characteristics. In this paper we study the Clifford+CS universal fault-tolerant gate set. The CS gate is used is many applications and this gate set is an important alternative to Clifford+T. We introduce a generating set in order to represent any unitary implementable by this gate set and with this we derive a bound on the CS-count of arbitrary multi-qubit unitaries. Analysing the channel representation of the generating set elements, we infer JnCS⊂JnT\\documentclass[12pt]{minimal} \\usepackage{amsmath} \\usepackage{wasysym} \\usepackage{amsfonts} \\usepackage{amssymb} \\usepackage{amsbsy} \\usepackage{mathrsfs} \\usepackage{upgreek} \\setlength{\\oddsidemargin}{-69pt} \\begin{document}$${\\mathcal {J}}_n^{CS}\\subset {\\mathcal {J}}_n^T$$\\end{document}, where JnCS\\documentclass[12pt]{minimal} \\usepackage{amsmath} \\usepackage{wasysym} \\usepackage{amsfonts} \\usepackage{amssymb} \\usepackage{amsbsy} \\usepackage{mathrsfs} \\usepackage{upgreek} \\setlength{\\oddsidemargin}{-69pt} \\begin{document}$${\\mathcal {J}}_n^{CS}$$\\end{document} and JnT\\documentclass[12pt]{minimal} \\usepackage{amsmath} \\usepackage{wasysym} \\usepackage{amsfonts} \\usepackage{amssymb} \\usepackage{amsbsy} \\usepackage{mathrsfs} \\usepackage{upgreek} \\setlength{\\oddsidemargin}{-69pt} \\begin{document}$${\\mathcal {J}}_n^T$$\\end{document} are the set of unitaries exactly implementable by the Clifford+CS and Clifford+T gate sets, respectively. We develop CS-count optimal synthesis algorithms for both approximately and exactly implementable multi-qubit unitaries. With the help of these we derive a CS-count-optimal circuit for Toffoli, implying JnTof=JnCS\\documentclass[12pt]{minimal} \\usepackage{amsmath} \\usepackage{wasysym} \\usepackage{amsfonts} \\usepackage{amssymb} \\usepackage{amsbsy} \\usepackage{mathrsfs} \\usepackage{upgreek} \\setlength{\\oddsidemargin}{-69pt} \\begin{document}$${\\mathcal {J}}_n^{Tof}={\\mathcal {J}}_n^{CS}$$\\end{document}, where JnTof\\documentclass[12pt]{minimal} \\usepackage{amsmath} \\usepackage{wasysym} \\usepackage{amsfonts} \\usepackage{amssymb} \\usepackage{amsbsy} \\usepackage{mathrsfs} \\usepackage{upgreek} \\setlength{\\oddsidemargin}{-69pt} \\begin{document}$${\\mathcal {J}}_n^{Tof}$$\\end{document} is the set of unitaries exactly implementable by the Clifford+Toffoli gate set. Such conclusions can have an important impact on resource estimates of quantum algorithms.

Cross-Cap Defects and Fault-Tolerant Logical Gates in the Surface Code and the Honeycomb Floquet Code

We consider the Z2 toric code, surface code, and Floquet code defined on a nonorientable surface, which can be considered as families of codes extending Shor’s nine-qubit code. We investigate the fault-tolerant logical gates of the Z2 toric code in this setup, which corresponds to e↔m exchanging symmetry of the underlying Z2 gauge theory. We find that nonorientable geometry provides a new way for the emergent symmetry to act on the code space, and discover the new realization of the fault-tolerant Hadamard gate of the two-dimensional surface code with a single cross cap connecting the vertices nonlocally along a slit, dubbed a nonorientable surface code. This Hadamard gate can be realized by a constant-depth local unitary circuit modulo nonlocality caused by a cross cap. Via folding, the nonorientable surface code can be turned into a bilayer local quantum code, where the folded cross cap is equivalent to a bilayer twist terminated on a gapped boundary and the logical Hadamard only contains local gates with intralayer couplings when being away from the cross cap, as opposed to the interlayer couplings on each site needed in the case of the folded surface code. We further obtain the complete logical Clifford gate set for a stack of nonorientable surface codes and similarly for codes defined on Klein-bottle geometries. We then construct the honeycomb Floquet code in the presence of a single cross cap, and find that the period of the sequential Pauli measurements acts as a HZ logical gate on the single logical qubit, where the cross cap enriches the dynamics compared with the orientable case. We find that the dynamics of the honeycomb Floquet code is precisely described by a condensation operator of the Z2 gauge theory, and illustrate the exotic dynamics of our code in terms of a condensation operator supported at a nonorientable surface. Published by the American Physical Society 2024

QCA-based fault-tolerant XOR Gate for reliable computing with high thermal stability

The XOR gate is an essential element in the design of digital circuits due to its versatility and usefulness. The design of XOR gate in this paper is based on Quantum-dot Cellular Automata (QCA) 2D planner technology with no line-to-line intersections. The output amplitude is improved by redundant cell-based design, which also helped reliability and fault tolerance outperform. The proposed XOR gate achieves fault tolerance to single-cell addition and missing-cell defects from 68.48% to 95.33%. In addition, the proposed XOR gate is also fault-tolerant against multiple-cell missing defects, as verified from the simulations. Furthermore, high thermal stability makes the circuit reliable for QCA-based digital design applications. The digital design applications such as 4-bit B2G code converter and a 4-bit parity checker are designed from this XOR gate, utilizing 438 and 414 cells, respectively. This demonstrates its effectiveness in designing fault resilient and reliable circuit designs for various applications.

Design and Analysis of a New Fault-Tolerant QCA-based Nano-Scale Circuit for Morphological Operations in Image Processing

Quantum-dot cellular automata (QCA) is based on traditional cellular automata models in which each cell has one of the finite distinct states at any given time. Cellular automata refer to the use of Coulombic contact rather than wires to connect cells. The discrete character of cellular automata and quantum mechanics have been exploited to develop nano-scale devices that can conduct computations with high switching frequency and low power dissipation. QCA has been utilized in many categories for fault-tolerant and reversible logic computing. On the other hand, the morphology algorithm is an area of image processing that provides a unified methodology and strong tools for image/video processing applications. This work proposes a unique fault-tolerant approach based on QCA to execute the morphological operations in image processing. Two fault-tolerant 5-input majority gates are employed in the implemented QCA architecture, and a control line is used to accomplish dilation and erosion. To assess the capabilities of the proposed fault-tolerant circuit for morphological procedures, its performance is analyzed and confirmed. The proposed design is compared to earlier results, which significantly improve fault-tolerant ability.

Analyzing Prospects for Quantum Advantage in Topological Data Analysis

Lloyd [Nat. Commun. , 10138 (2016)] were first to demonstrate the promise of quantum algorithms for computing Betti numbers, a way to characterize topological features of data sets. Here, we propose, analyze, and optimize an improved quantum algorithm for topological data analysis (TDA) with reduced scaling, including a method for preparing Dicke states based on inequality testing, a more efficient amplitude estimation algorithm using Kaiser windows, and an optimal implementation of eigenvalue projectors based on Chebyshev polynomials. We compile our approach to a fault-tolerant gate set and estimate constant factors in the Toffoli complexity. Our analysis reveals that superquadratic quantum speedups are only possible for this problem when targeting a multiplicative error approximation and the Betti number grows asymptotically. Further, we propose a dequantization of the quantum TDA algorithm that shows that having exponentially large dimension and Betti number are necessary, but insufficient conditions, for superpolynomial advantage. We then introduce and analyze specific problem examples which have parameters in the regime where superpolynomial advantages may be achieved, and argue that quantum circuits with tens of billions of Toffoli gates can solve seemingly classically intractable instances. Published by the American Physical Society 2024

Shorter quantum circuits via single-qubit gate approximation

We give a novel procedure for approximating general single-qubit unitaries from a finite universal gate set by reducing the problem to a novel magnitude approximation problem, achieving an immediate improvement in sequence length by a factor of 7/9. Extending the works \cite{Hastings2017} and \cite{Campbell2017}, we show that taking probabilistic mixtures of channels to solve fallback \cite{BRS2015} and magnitude approximation problems saves factor of two in approximation costs. In particular, over the Clifford+Tgate set we achieve an average non-Clifford gate count of0.23log2⁡(1/ε)+2.13and T-count0.56log2⁡(1/ε)+5.3with mixed fallback approximations for diamond norm accuracyε.This paper provides a holistic overview of gate approximation, in addition to these new insights. We give an end-to-end procedure for gate approximation for general gate sets related to some quaternion algebras, providing pedagogical examples using common fault-tolerant gate sets (V, Clifford+T and Clifford+T). We also provide detailed numerical results for Clifford+T and Clifford+Tgate sets. In an effort to keep the paper self-contained, we include an overview of the relevant algorithms for integer point enumeration and relative norm equation solving. We provide a number of further applications of the magnitude approximation problems, as well as improved algorithms for exact synthesis, in the Appendices.

Partitioning qubits in hypergraph product codes to implement logical gates

The promise of high-rate low-density parity check (LDPC) codes to substantially reduce the overhead of fault-tolerant quantum computation depends on constructing efficient, fault-tolerant implementations of logical gates on such codes. Transversal gates are the simplest type of fault-tolerant gate, but the potential of transversal gates on LDPC codes has hitherto been largely neglected. We investigate the transversal gates that can be implemented in hypergraph product codes, a class of LDPC codes. Our analysis is aided by the construction of a symplectic canonical basis for the logical operators of hypergraph product codes, a result that may be of independent interest. We show that in these codes transversal gates can implement Hadamard (up to logical SWAP gates) and control-Z on all logical qubits. Moreover, we show that sequences of transversal operations, interleaved with error correction, allow implementation of entangling gates between arbitrary pairs of logical qubits in the same code block. We thereby demonstrate that transversal gates can be used as the basis for universal quantum computing on LDPC codes, when supplemented with state injection.

Quantum error correction with fractal topological codes

Recently, a class of fractal surface codes (FSCs), has been constructed on fractal lattices with Hausdorff dimension 2+ϵ, which admits a fault-tolerant non-Clifford CCZ gate \cite{zhu2021topological}. We investigate the performance of such FSCs as fault-tolerant quantum memories. We prove that there exist decoding strategies with non-zero thresholds for bit-flip and phase-flip errors in the FSCs with Hausdorff dimension 2+ϵ. For the bit-flip errors, we adapt the sweep decoder, developed for string-like syndromes in the regular 3D surface code, to the FSCs by designing suitable modifications on the boundaries of the holes in the fractal lattice. Our adaptation of the sweep decoder for the FSCs maintains its self-correcting and single-shot nature. For the phase-flip errors, we employ the minimum-weight-perfect-matching (MWPM) decoder for the point-like syndromes. We report a sustainable fault-tolerant threshold (∼1.7%) under phenomenological noise for the sweep decoder and the code capacity threshold (lower bounded by 2.95%) for the MWPM decoder for a particular FSC with Hausdorff dimension DH≈2.966. The latter can be mapped to a lower bound of the critical point of a confinement-Higgs transition on the fractal lattice, which is tunable via the Hausdorff dimension.

Towards nanoscale fault-tolerant logical circuits using proposed robust majority voter in quantum-dot cellular automata technology

The occupied area, power consumption, and delay are the most crucial and critical factors in constructing integrated circuits. Due to the reduced occupied area, highly low power consumption, and extremely high speed of quantum-dot cellular automata (QCA) technology, it is one of the finest alternatives to complementary metal–oxide–semiconductor (CMOS) technology for nanoscale construction of circuits. On the other hand, fault tolerance becomes crucial in QCA due to the inherent sensitivity of quantum dots to various sources of errors and faults. These errors can arise from environmental disturbances, manufacturing imperfections, thermal fluctuations, and other factors. The presence of defects or faults can significantly impact the functionality and accuracy of QCA systems, leading to incorrect computation or signal corruption. To address these challenges, fault-tolerant structures are designed in QCA systems. These structures are specifically engineered to detect, tolerate, and mitigate the effects of faults, thereby enhancing the reliability and robustness of QCA-based computation. Fault-tolerant designs aim to ensure that the system can continue to operate correctly even in the presence of defects or faults. In QCA, proposed a fault-tolerant majority gate is necessary to ensure reliable computation in the presence of defects or faults. The fault-tolerant majority gate is a fundamental component in digital logic circuits, and it plays a crucial role in performing computations. It takes multiple input signals and produces an output based on the majority of those inputs. In classical computing, the majority gates are typically implemented using transistors. Therefore, this paper introduces a new and efficient fault-tolerant 3-input majority voter (FT MV3) using 11 simple and rotated cells in the QCA technology, which is 100% and 90.47% tolerant against single-cell and double-cell omission defects. The recommended FT MV3 gate verification is confirmed using some physical proofs. Afterward, to illustrate the performance of the introduced gate, three fault-tolerant computational circuits, including multiplexer, adder and ALU, are presented using the introduced FT MV3 gate. The comparison of the proposed fault tolerant ALU to the best coplanar design shows a 28.80% and 34.01% reduction of cell count and occupied area, respectively. All circuits are simulated using QCADesigner 2.0.3 software.

An ultra-efficient design of fault-tolerant 3-input majority gate (FTMG) with an error probability model based on quantum-dots

Quantum-dot cellular automata (QCA) has recently attracted significant notice thanks to their inherent ability to decrease energy dissipation and decreasing area, which is the primary need of digital circuits. However, the lack of resistance of QCA circuits under defects in previous works is a vital challenge affecting the stability of the circuit and output production. In addition, with the high defect rate in QCA, suggesting resistance and stable structures is critical. Furthermore, the 3-input majority gate is a fundamental component of QCA circuits; therefore, improving this essential gate would enable the development of fault-tolerant circuits. This paper recommends a 3-input majority gate which is 100% fault-tolerant against single-cell omission defects. Moreover, the fundamental gates are introduced based on the proposed gate. In addition, an adder and a 1:2 decoder are also designed. Using QCADesigner 2.0.3 and QCAPro software, simulations of structures and analysis of power consumption are performed.

Fault-tolerant reversible logic gate-based RO-PUF design

Physically Unclonable Function (PUF) is an emerging modern approach to the security concerns of the physical systems which require the protection of sensitive data. PUF generates unique, reliable, and secure responses which can be utilized for cryptographic applications. In this paper, a fault-tolerant reversible logic gate-based RO PUF is proposed. We utilized a fault-tolerant reversible logic Double Feynman Gate in place of conventional inverters to design the ring oscillators (RO). The proposed RO PUF designs implemented and evaluated on the Basys-3 Artix-7 FPGA board. The PUF parameters such as uniqueness, reliability, and uniformity were analyzed based on the experimental results. The empirical results show that the proposed RO PUF has uniqueness and reliability of 0.49 and 85.95%, respectively. The inter-chip and intra-chip uniqueness for the proposed design is 23% and 25.5%, respectively higher than the conventional RO PUF design. This fault-tolerant reversible logic gate-based RO PUF design shows better uniqueness, reliability, and uniformity than other considered PUF designs.

Designing a one-bit coplanar QCA ALU using a novel robust area-efficient three-input majority gate design

Quantum-dot cellular automata (QCA) which is a suitable alternative to conventional CMOS technology is susceptible to some defects in chemical synthesis and deposition phases of circuit fabrication. Besides, the majority gate is one of the most important primary gates for designing digital circuits in this emerging technology. Designing a fault-tolerant majority gate is one of the hot topics in QCA technology. Most previous works tried to improve the majority gate reliability by increasing the number of QCA cells which resulted in occupying more area. In this paper we propose a novel area-efficient three-input majority gate which can tolerate the single-cell omission and extra-cell deposition defects by 86% and 75%, respectively. The proposed majority gate consists of 11 simple QCA cells with $$0.006\,$$ µ $$\hbox {m}^{2}$$ and 1.62 e-002 MeV area and energy consumption, respectively. A complete fault tolerance analysis for our proposed majority gate against cell omission, extra-cell deposition, and cell displacement and misalignment defects is also provided. We design a fault-tolerant coplanar fulladder/fullsubtractor and a two-to-one multiplexer using the proposed majority gate and compare it with the same previous works. Simulation results from QCADesigner 2.0.3 and QCADesigner-E show that in all cases our proposed robust circuits can reduce the area consumption. Finally, we implement a fault-tolerant coplanar one-bit ALU using the proposed circuits that can perform four logical and mathematical operations.

Strategies for a practical advantage of fault-tolerant circuit design in noisy trapped-ion quantum computers

Fault-tolerant quantum error correction provides a strategy to protect information processed by a quantum computer against noise which would otherwise corrupt the data. A fault-tolerant universal quantum computer must implement a universal gate set on the logical level in order to perform arbitrary calculations to in principle unlimited precision. In this paper we characterize the recent demonstration of a fault-tolerant universal gate set in a trapped-ion quantum computer [Postler et al., Nature (London) 605, 7911 (2022)] and identify aspects to improve the design of experimental setups to reach an advantage of logical over physical qubit operation. We show that various criteria to assess the break-even point for fault-tolerant quantum operations are within reach for the ion trap quantum computing architecture under consideration. Furthermore, we analyze the influence of crosstalk in entangling gates for logical state preparation circuits. These circuits can be designed to respect fault tolerance for specific microscopic noise models. We find that an experimentally informed depolarizing noise model captures the essential noise dynamics of the fault-tolerant experiment that we consider, and crosstalk is negligible in the currently accessible regime of physical error rates. For deterministic Pauli state preparation, we provide a fault-tolerant unitary logical qubit initialization circuit, which can be realized without in-sequence measurement and feed-forward of classical information. Additionally, we show that nondeterministic state preparation schemes, i.e., repeat until success, for logical Pauli and magic states perform with higher logical fidelity over their deterministic counterparts for the current and anticipated future regime of physical error rates. Our results offer guidance on improvements of physical qubit operations and validate the experimentally informed noise model as a tool to predict logical failure rates in quantum computing architectures based on trapped ions.

Acceptor-based qubit in silicon with tunable strain

Long coherence time and compatibility with semiconductor fabrication make spin qubits in silicon an attractive platform for quantum computing. In recent years, hole spin qubits are being developed as they have the advantages of weak coupling to nuclear spin noise and strong spin-orbit coupling (SOC), in constructing high-fidelity quantum gates. However, there are relatively few studies on the hole spin qubits in a single acceptor, which requires only low density of the metallic gates. In particular, the investigation of flexible tunability using controllable strain for fault-tolerant quantum gates of acceptor-based qubits is still lacking. Here, we study the tunability of electric dipole spin resonance (EDSR) of acceptor-based hole spin qubits with controllable strain. The flexible tunability of LH-HH splitting and spin-hole coupling (SHC) with the two kinds of strain can avoid high electric field at the "sweet spot", and the operation performance of the acceptor qubits could be optimized. Longer relaxation time or stronger EDSR coupling at low electric field can be obtained. Moreover, with asymmetric strain, two "sweet spots" are induced and may merge together, and form a second-order "sweet spot". As a result, the quality factor $Q$ can reach $10^{4}$ for single-qubit operation, with high tolerance for the electric field variation. Furthermore, the two-qubit operation of acceptor qubits based on dipole-dipole interaction is discussed for high-fidelity two-qubit gates. The tunability of spin qubit properties in acceptor via strain could provide promising routes for spin-based quantum computing.

A novel design for managing the faults of the 2 × 2 nano-scale crossbar using quantum-dots

Due to new challenges in transistor technology, non-traditional design approaches and processes have risen to the fore. Quantum-dot Cellular Automata (QCA) nano-technology is a fascinating design method that uses columbic repulsion to transmit and manipulate data. On the other hand, crossbar circuits are critical areas in digital circuits and a signal across several users. A new design is suggested in this paper for a crossbar circuit to manage the faults and decrease the complexity. This paper creates the fault-tolerant crossbar circuit by combining a fault-tolerant majority gate. The clock zone technique is used to implement the suggested architecture. As a result, the suggested design is less susceptible to manufacturing flaws. In addition, the proposed design can manage energy dissipation efficiently. QCADesigner-E is used for simulation and energy dissipation studies. The suggested fault-tolerant crossbar circuit in QCA nano-technology has only 156 cells and 0.18 µm2 area.

Topological Order, Quantum Codes, and Quantum Computation on Fractal Geometries

We investigate topological order on fractal geometries embedded in $n$ dimensions. In particular, we diagnose the existence of the topological order through the lens of quantum information and geometry, i.e., via its equivalence to a quantum error-correcting code with a macroscopic code distance or the presence of macroscopic systoles in systolic geometry. We first prove a no-go theorem that $\mathbb{Z}_N$ topological order cannot survive on any fractal embedded in 2D. For fractal lattice models embedded in 3D or higher spatial dimensions, $\mathbb{Z}_N$ topological order survives if the boundaries of the interior holes condense only loop or membrane excitations. Moreover, for a class of models containing only loop or membrane excitations, and are hence self-correcting on an $n$-dimensional manifold, we prove that topological order survives on a large class of fractal geometries independent of the type of hole boundaries. We further construct fault-tolerant logical gates using their connection to global and higher-form topological symmetries. In particular, we have discovered a logical CCZ gate corresponding to a global symmetry in a class of fractal codes embedded in 3D with Hausdorff dimension asymptotically approaching $D_H=2+\epsilon$ for arbitrarily small $\epsilon$, which hence only requires a space-overhead $\Omega(d^{2+\epsilon})$ with $d$ being the code distance. This in turn leads to the surprising discovery of certain exotic gapped boundaries that only condense the combination of loop excitations and gapped domain walls. We further obtain logical $\text{C}^{p}\text{Z}$ gates with $p\le n-1$ on fractal codes embedded in $n$D. In particular, for the logical $\text{C}^{n-1}\text{Z}$ in the $n^\text{th}$ level of Clifford hierarchy, we can reduce the space overhead to $\Omega(d^{n-1+\epsilon})$. Mathematically, our findings correspond to macroscopic relative systoles in fractals.

A new fault-tolerant single-bit comparator in QCA technology using a novel X-NOR gate

Quantum-dot Cellular Automata (QCA) is one of the potential remedies to the limitations of transistor-based technologies. The QCA is brand-new, significant nanotechnology that has caught the attention of many scholars. It has a lot of tempting qualities, such as quick speed, low energy usage, and small size. This work uses QCA's cell contact rules to provide a new fault-tolerant XNOR gate. Additionally, a unique comparator circuit is suggested that makes use of the fault-tolerant XNOR gates. The proposed comparator offers a noteworthy improvement in both area and gate count. The proposed circuits' functionality, implementation, and testing are validated using the QCADesigner simulator. Only 106 cells make up this fault-tolerant comparator, which has a desirable size of 0.10 µm2. Additionally, the outcomes showed that the design offers improved fault-tolerant features in comparison to its alternatives. Investigations also looked into single-cell omission, displacement, misalignment, and other deposition defects. Based on the experiment's outcomes, the suggested comparator can tolerate more than 80 % of faults.

Morphing Quantum Codes

We introduce a morphing procedure that can be used to generate new quantum codes from existing quantum codes. In particular, we morph the 15-qubit Reed-Muller code to obtain a $[\![10,1,2]\!]$ code that is the smallest known stabilizer code with a fault-tolerant logical $T$ gate. In addition, we construct a family of hybrid color-toric codes by morphing the color code. Our code family inherits the fault-tolerant gates of the original color code, implemented via constant-depth local unitaries. As a special case of this construction, we obtain toric codes with fault-tolerant multi-qubit control-$Z$ gates. We also provide an efficient decoding algorithm for hybrid color-toric codes in two dimensions, and numerically benchmark its performance for phase-flip noise. We expect that morphing may also be a useful technique for modifying other code families such as triorthogonal codes.

Optical demonstration of quantum fault-tolerant threshold

A major challenge in practical quantum computation is the ineludible errors caused by the interaction of quantum systems with their environment. Fault-tolerant schemes, in which logical qubits are encoded by several physical qubits, enable to the output of a higher probability of correct logical qubits under the presence of errors. However, strict requirements to encode qubits and operators render the implementation of a full fault-tolerant computation challenging even for the achievable noisy intermediate-scale quantum technology. Especially the threshold for fault-tolerant computation still lacks experimental verification. Here, based on an all-optical setup, we experimentally demonstrate the existence of the threshold for the fault-tolerant protocol. Four physical qubits are represented as the spatial modes of two entangled photons, which are used to encode two logical qubits. The experimental results clearly show that when the error rate is below the threshold, the probability of correct output in the circuit, formed with fault-tolerant gates, is higher than that in the corresponding non-encoded circuit. In contrast, when the error rate is above the threshold, no advantage is observed in the fault-tolerant implementation. The developed high-accuracy optical system may provide a reliable platform to investigate error propagation in more complex circuits with fault-tolerant gates.

Demonstration of fault-tolerant universal quantum gate operations.

Quantum computers can be protected from noise by encoding the logical quantum information redundantly into multiple qubits using error-correcting codes1,2. When manipulating the logical quantum states, it is imperative that errors caused by imperfect operations do not spread uncontrollably through the quantum register. This requires that all operations on the quantum register obey a fault-tolerant circuit design3-5, which, in general, increases the complexity of the implementation. Here we demonstrate a fault-tolerant universal set of gates on two logical qubits in a trapped-ion quantum computer. In particular, we make use of the recently introduced paradigm of flag fault tolerance, where the absence or presence of dangerous errors is heralded by the use of auxiliary flag qubits6-10. We perform a logical two-qubit controlled-NOT gate between two instances of the seven-qubit colour code11,12, and fault-tolerantly prepare a logical magic state8,13. We then realize a fault-tolerant logical T gate by injecting the magic state by teleportation from one logical qubit onto the other14. We observe the hallmark feature of fault tolerance-a superior performance compared with a non-fault-tolerant implementation. In combination with recently demonstrated repeated quantum error-correction cycles15,16, these results provide a route towards error-corrected universal quantum computation.