Fault-tolerant Computer Systems Research Articles

Designing of fault-tolerant computer system structures using residue number systems

Abstract This article discusses computing systems that operate in residue number systems (RNSs). The main direction of improving computer systems (CSs) is increasing the speed of implementation of arithmetic operations and the reliability of their functioning. Encoding data in RNS solves the problem of optimal redundancy, i.e., the creation of such computing systems provides maximum reliability with restrictions on weight and size characteristics. This article proposes new structures of fault-tolerant CSs operating in RNS in the case of the application with an active fault-tolerant method. The use of the active fault-tolerant method (dynamic redundancy) in the RNSs provides higher reliability. In addition, with an increase in the digits of CSs, the efficiency of using the proposed structures increases.

A System Model of Fault Tolerance Technique in the Distributed and Scalable System: A Review

Fault tolerance is one of the most crucial concerns in distributed systems. Flout tolerance system is very difficult to implement due to its dynamic nature and complex services. Several research efforts consare istently being made to implement that tolerance in a distributed system. Some recent surveys try to incorporate the several fault tolerance architectures and methodologies proposed for a distributed system. This paper gives a systematic and comprehensive interpretation of different fault types, their causes, and various fault-tolerance approaches used in a distributed system. The paper presents a broad survey of various fault tolerance frameworks in the context of their basic approaches, fault applicability, and other key features. we investigate the different techniques of fault tolerance which is used in a distributed and scalable system. Scalability is an important factor in distributed Systems. It describes the ability of the system to dynamically adjust its own computing performance by changing available computing resources and scheduling methods. The focus of this paper is on types of faults occurring in the system and fault detection techniques. A fault can occur in the system due to the link failure or for any other reason. An appropriate fault detection technique can avoid a loss and save from system failure. The main objective of the fault-tolerant computer system is to continue operating uninterrupted despite the failure of one or more of its components. In the early day’s computer systems were not distributed and they also did not share resources. Now, most of the computers are distributed. They work independently on a common task. So, if one system gets any fault then the other systems will take over the computation of the fault system. The user will not get any issues with his tasks.

A Low-Overhead Reconfigurable RISC-V Quad-Core Processor Architecture for Fault-Tolerant Applications

Radiation can affect the correct behavior of an electronic device. Hence, the microprocessors used for space missions need to be protected against fault. TMR (Triple modular redundancy) is used for mitigating various kinds of faults in an electronic circuit. Although TMR provides an excellent level of reliability, it takes a large area and suffers from high power consumption. To reduce the area and power overheads DMR (double modular redundancy) is used. The DMR approach significantly reduces the resource overhead but it also reduces the performance by imposing timing penalty. Various methods have been proposed since the incarnation of TMR and DMR, but the resource overhead is still a challenging issue. Hence, in this work, a new DMR based reconfigurable quad-core RV32IM processor architecture is proposed for fault-tolerant applications. Depending upon the environment of operation and application sensitivity, the designed processor can be reconfigured to work either in normal mode or fault-tolerant mode. The novelty of the proposed architecture is that the reconfigurable feature reduces the resource overhead and makes the processor energy-efficient by optimally using all four processor cores to provide fault-tolerant results. The proposed computing architecture is designed using Verilog HDL(Hardware Description Language) and synthesized on 32nm CMOS (Complementary Metal-Oxide Semiconductor) process technology node using Synopsys Design Compiler EDA (Electronic Design Automation) tool. Compared to unprotected design, the synthesis tool reports -21.75% reduction in power with a time penalty of +9.96% and area overhead of +17.89% for the proposed fault-tolerant approach. Compared to the state-of-the-art fault-tolerant computing system, the proposed design achieves -2.26% low area overhead with its reliability intact as DMR. Further, the proposed processor is prototyped and tested on FPGA (field-programmable gate array) with fault-injection using SEM (soft error mitigation) IP core.

Research consistency and perfomance of nosql replicated databases

This paper evaluates performance of distributed fault-tolerant computer systems and replicated NoSQL databases and studies the impact of data consistency on performance and throughput on the example of a three-replicated Cassandra cluster. The paper presents results of heavy-load testing (benchmarking) of Cassandra cluster’s read and write performance which replicas were deployed on Amazon EC2 cloud. The presented quantitative results show how different consistency settings affect the performance of a Cassandra cluster under different workloads considering two deployment scenarios: when all cluster replicas are located in the sane data center, and when they are geographically distributed across different data centers (i.e. Amazon availability zones). We propose a new method of minimizing Cassandra response time while ensuring strong data consistency which is based on optimization of consistency settings depending on the current workload and the proportion between read and write operations.

Using pipelined control code generator as a reference system in FPGA’s selection as a hardware platform for fault-tolerance computing system

One of the main features of hash functions is a significant change in the hash with any (even small) changes in the input data. Using their pipelined versions (which outputs the next hash on each clock cycle) allows to create a system that is guaranteed to respond to any failures in the process. Reference systems based on control code generators can be quickly developed and thanks to a wide range of functions, for calculating control codes, can be close to the characteristics of the developed system in terms of area and logical complexity. In this article, we propose using pipelined control code generators as reference systems in the development of fault tolerant computing systems. In this case, before or simultaneously with the development of a computing system, we need to perform a series of experiments with pipelined generators and control codes. Several versions of such reference system have been developed, each of which implements various fault tolerance techniques. The obtained protected reference systems are synthesized into the basis of available FPGAs by various software packages. Next, the results are compared and the most successful (with good results) sets are selected from FPGAs, software, and fault tolerance techniques.

METHOD FOR ASSESSING OF RELIABILITY CHARACTERISTICS IN DESIGNING OF FAILURERESISTANT REAL-TIME OPERATING SYSTEMS

For many years, real-time OS-based applications have been used in embedded special-purpose systems. Recently they have been used everywhere, from on-board control systems for aircraft, to household appliances. The development of multiprocessor computing systems usually aims to increase either the level of reliability or the level of system performance to values that are inaccessible or difficult to implement in traditional computer systems. In the first case, the question of the availability of special means of ensuring the fault tolerance of computer systems arises, the main feature (and advantage) of which is the absence of any single resource, failure of which leads to a fatal failure of the entire system. The use of a real-time operating system is always associated with equipment, with an object and with events occurring at an object. A real-time system, as a hardware-software complex, includes sensors that record events at an object, input / output modules that convert sensor readings into a digital form suitable for processing these readings on a computer, and finally, a computer with a program that responds to events occurring at the facility. The RTOS is focused on processing external events. It is this that leads to fundamental differences (compared with general-purpose OS) in the structure of the system as well as in the functions of the kernel and in the construction of the input-output system. The RTOS can be similar in its user interface to general-purpose operating systems, but it is completely different in its structure. In addition, the use of RTOS is always specific. If users (not developers) usually perceive a general-purpose OS as a ready-made set of applications, then the RTOS serves only as a tool for creating a specific hardware-software complex in real time. Therefore, the widest class of users of RTOS is the developers of real-time complexes, people designing control and data collection systems. When designing and developing a specific real-time system, the programmer always knows exactly what events can occur at the facility, and he knows the critical terms for servicing each of these events. We call a real-time system (SRV) a hardware-software complex that responds in predictable times to an unpredictable stream of external events. The system must have time to respond to the event that occurred at the facility, during the time critical for this event. The critical time for each event is determined by the object and by the event itself, and, of course, it can be different, but the response time of the system must be predicted (calculated) when creating the system. Lack of response at the predicted time is considered an error for real-time systems. The system must have time to respond to simultaneously occurring events. Even if two or more external events occur simultaneously, the system must have time to respond to each of them during time intervals critical for these events. In this study, as part of a network fault-tolerant technology, the RTOS becomes a special type of control software that is used to organize the operation of embedded applications, which are characterized by limited memory resources, low productivity and the requirements of a guaranteed response time (T<4 μs), high level availability and availability of auto-monitoring facilities.

A Method of Error Correction in Arithmetic Logic Devices of Information-Measuring Systems Processors

An error-correction method is proposed for computer arithmetic logic units, in which memory duplication is executed and an algebraic linear code with minimal information redundancy is used for control. Rules for the use of coded information have been formulated for error detection during execution of arithmetic and logical operations. A procedure is proposed for the formulation of the duplication channel of arithmetic logic units due to the use of equipment intended for coding of information and the functional redundancy of the arithmetic logic units of the processor. Mechanisms are revealed that make it possible to use the functional arithmetic logic units of the processor and the monitoring equipment for the execution of primary and duplicating functions. Hardware costs are calculated for the formation of the duplication channel, and a comparative estimation is conducted of the gain in probability of failure-free operation of the fail-safe computer when using the proposed method of error correction in comparison with the majority reservation method. It is shown that the developed method of error correction, by comparison with the majority method, makes it possible to improve the probability of failure-free operation of the computer, reduce by a third the overall hardware costs, and reduce by a factor of 2.5 the expenditures for creation of the arithmetic logic unit of the processor.

Research on Fault-Tolerant Flight Control Computer for High Altitude Long Endurance Unmanned Air Vehicle

With the development of high altitude long endurance UAV, Flight Control System in high altitude long endurance UAV must have so strong failure tolerance ability that it can improve the whole system reliability. Using redundancy technique can extremely improve failure tolerance and reliability of flight control system. Compared among civil and military aircraft and UAV, the architectures and redundancy management of fault-tolerant flight control computer (FCC)systems are introduced. Then, give a new architectures and redundancy management of fault-tolerant FCC systems for high altitude long endurance UAV. The experimental results show that the system meets the UAV's demand of high reliability, low cost and good expansibility, maximize the utilization of system resources and effectively improve the fault tolerant capability of airborne computer and the reliability of sensor subsystem. With fault injection test method, the results show that the fault tolerant methods improve fault detection rate and fault isolation rate.

Bi-directional system analysis under copula-coverage approach

ABSTRACTReliability assessment is a major step, toward the development of fault-tolerant computing system. In different fields of engineering and physical/ailed sciences, researchers or engineers have several reliability approaches for the better performance of the system. By assuming different types of time trends, failure modes and repair effects, the legion stochastic model has been developed for repairable system. This study shows a novel concept for three state fault tolerant repairable systems with two types of repair. This research predicts the effect of the coverage factor using Gumbel-Hougaard family of copula approach on reliability characteristics of the designed system.

The reliability model of the fault-tolerant computing system with triple-modular redundancy based on the independent nodes

This paper deals with a reliability model of the restorable non-stop computing system with triple-modular redundancy based on independent computing nodes, taking into consideration the finite time for node activation and different node failure rates in the active and passive states. The obtained by authors generalized reliability model and calculation formulas for reliability indices for the system based on identical and independent computing nodes with the given threshold for quantity of active nodes, at which system is considered as operable, are also discussed. Finally, the application of the generalized model to the particular case of the non-stop restorable computing system with triple-modular redundancy based on independent nodes and calculation examples for reliability indices are also provided.

Injecting Intermittent Faults for the Dependability Assessment of a Fault-Tolerant Microcomputer System

As scaling is more and more aggressive, intermittent faults are increasing their importance in current deep submicron complementary metal-oxide-semiconductor (CMOS) technologies. This work shows the dependability assessment of a fault-tolerant computer system against intermittent faults. The applied methodology lies in VHDL-based fault injection, which allows the assessment in early design phases, together with a high level of observability and controllability. The evaluated system is a duplex microcontroller system with cold stand-by sparing. A wide set of intermittent fault models have been injected, and from the simulation traces, coverages and latencies have been measured. Markov models for this system have been generated and some dependability functions, such as reliability and safety, have been calculated. From these results, some enhancements of detection and recovery mechanisms have been suggested. The methodology presented is general to any fault-tolerant computer system.

Searching for majority with k-tuple queries

Diagnosing the quality of components in fault-tolerant computer systems often requires numerous tests with limited resources. It is usually the case that repeated tests on a selected, limited number of components are performed and the results are taken into account so as to infer a diagnostic property of the computer system as a whole. In this paper we abstract fault-tolerant testing as the following problem concerning the color of the majority in a set of colored balls. Given a set of balls each colored with one of two colors, the majority problem is to determine whether or not there is a majority in one of the two colors. In case there is such a majority, the aim is to output a ball of the majority color, otherwise to declare that there is no majority. We propose algorithms for solving the majority problem by repeatedly testing only k-tuple queries. Namely, successive answers of an oracle (which accepts as input only k-tuples) to a sequence of k-tuple queries are assembled so as to determine whether or not the majority problem has a solution. An issue is to design an algorithm which minimizes the number of k-tuple queries needed in order to solve the majority problem on any possible input of n balls. In this paper we consider three querying models: Output, Counting, and General, reflecting the amount and type of information provided by the oracle on each test for a k-tuple.

Performance Evaluation of a Multi-state System Covering Imperfect Fault Coverage

Fault-tolerant networks are being used to provide more reliable network connections. Development of the fault-tolerant computing system requires accurate reliability modeling. Numerical formulations and complex models are commonly used for obtaining reliability measures. These measures are functions of component failure rates and fault-coverage. Coverage provides information about the fault and error detection, isolation, and system recovery capabilities. This research studied a system consisting three units in parallel with three types of failures namely, catastrophic, human, and unit failures incorporating the coverage factor and evaluated the various reliability measures of the considered multi-state system subject to imperfect fault coverage.

Design and Research of Computer System High Confidence Fault Tolerant

For high security and reliability of system critical areas, this paper designed a high-confidence fault-tolerant computer system, which combined high credibility technology with high organic reliability integration. High trusted computing technology used TCM structure to build a trusted password support system and achieve the platform integrity, identity authentication and data security. Redundant fault-tolerant technology to ensure the system, which activated in case of an error, is still able to provide uninterrupted service. Simulation results show the effectiveness and implementation of the technical solution approaches.

Dependability analysis for fault-tolerant computer systems using dynamic fault graphs

Dependability analysis is an important step in designing and analyzing safety computer systems and protection systems. Introducing multi-processor and virtual machine increases the system faults' complexity, diversity and dynamic, in particular for software-induced failures, with an impact on the overall dependability. Moreover, it is very different for safety system to operate successfully at any active phase, since there is a huge difference in failure rate between hardware-induced and softwareinduced failures. To handle these difficulties and achieve accurate dependability evaluation, consistently reflecting the construct it measures, a new formalism derived from dynamic fault graphs (DFG) is developed in this paper. DFG exploits the concept of system event as fault state sequences to represent dynamic behaviors, which allows us to execute probabilistic measures at each timestamp when change occurs. The approach automatically combines the reliability analysis with the system dynamics. In this paper, we describe how to use the proposed methodology drives to the overall system dependability analysis through the phases of modeling, structural discovery and probability analysis, which is also discussed using an example of a virtual computing system.

Tänka högt med papper och penna

A pad of squared paper, a pencil, an eraser, peace and quiet. These are the tools with which I have done most of my research in theoretical population genetics. But what do I do when I solve my equations describing evolutionary processes? Inspired by among others the French mathematician Cédric Villani, I discuss what happens when I chose to consider my research craft as a special kind of work process. Communication turns out to be surprisingly important in the process – particularly between different parts of my own thinking. The primary aim of my work process seems to be to produce the comforting feeling of certainty. To reach this goal, my slow pencil-driven handwriting is often better than efficient and apparently fail-safe computer programs.

Statement and solutions of problem of planning of fault-tolerant computer systems’ reconfiguration

The problems of creating and using of fault-tolerant computer systems is considered. The article presents different solutions of problem of structure dynamic control for the fault-tolerant computer systems functioning in high availability and load balancing modes.

Designing fault-tolerant real-time computer systems with diversified bus architecture for nuclear power plants

Fault-tolerant real-time computer (FT-RTC) systems are widely used to perform safe operation of nuclear power plants (NPP) and safe shutdown in the event of any untoward situation. Design requirements for such systems need high reliability, availability, computational ability for measurement via sensors, control action via actuators, data communication and human interface via keyboard or display. All these attributes of FT-RTC systems are required to be implemented using best known methods such as redundant system design using diversified bus architecture to avoid common cause failure, fail-safe design to avoid unsafe failure and diagnostic features to validate system operation. In this context, the system designer must select efficient as well as highly reliable diversified bus architecture in order to realize fault-tolerant system design. This paper presents a comparative study between CompactPCI bus and Versa Module Eurocard (VME) bus architecture for designing FT-RTC systems with switch over logic system (SOLS) for NPP.

Fault tolerant distributed real time computer systems for I&C of prototype fast breeder reactor

Prototype fast breeder reactor (PFBR) is in the advanced stage of construction at Kalpakkam, India. Three-tier architecture is adopted for instrumentation & control (I&C) of PFBR wherein bottom tier consists of real time computer (RTC) systems, middle tier consists of process computers and top tier constitutes of display stations. These RTC systems are geographically distributed and networked together with process computers and display stations. Hot standby architecture comprising of dual redundant RTC systems with switch over logic system is deployed in order to achieve fault tolerance. Fault tolerant dual redundant network connectivity is provided in each RTC system and TCP/IP protocol is selected for network communication. In order to assess the performance of distributed RTC systems, scaled down model was developed with 9 representative systems and nearly 15% of I&C signals of PFBR were connected and monitored. Functional and performance testing were carried out for each RTC system and the fault tolerant characteristics were studied by creating various faults into the system and observed the performance. Various quality of service parameters like connection establishment delay, priority parameter, transit delay, throughput, residual error ratio, etc., are critically studied for the network.

Отказоустойчивая компьютерная система хранения данных

Отказоустойчивая компьютерная система хранения данных