A Method of Error Correction in Arithmetic Logic Devices of Information-Measuring Systems Processors

Abstract

An error-correction method is proposed for computer arithmetic logic units, in which memory duplication is executed and an algebraic linear code with minimal information redundancy is used for control. Rules for the use of coded information have been formulated for error detection during execution of arithmetic and logical operations. A procedure is proposed for the formulation of the duplication channel of arithmetic logic units due to the use of equipment intended for coding of information and the functional redundancy of the arithmetic logic units of the processor. Mechanisms are revealed that make it possible to use the functional arithmetic logic units of the processor and the monitoring equipment for the execution of primary and duplicating functions. Hardware costs are calculated for the formation of the duplication channel, and a comparative estimation is conducted of the gain in probability of failure-free operation of the fail-safe computer when using the proposed method of error correction in comparison with the majority reservation method. It is shown that the developed method of error correction, by comparison with the majority method, makes it possible to improve the probability of failure-free operation of the computer, reduce by a third the overall hardware costs, and reduce by a factor of 2.5 the expenditures for creation of the arithmetic logic unit of the processor.