Packet-based on-chip interconnection networks, or Network-on-Chips (NoCs) are progressively replacing global on-chip interconnections in Multi-processor System-on-Chips (MP-SoCs) thanks to better performances and lower power consumption. However, modern generations of MP-SoCs have an increasing sensitivity to faults due to the progressive shrinking technology. Consequently, in order to evaluate the fault sensitivity in NoC architectures, there is the need of accurate test solution which allows to evaluate the fault tolerance capability of NoCs. This paper presents an innovative test architecture based on a dual-processor system which is able to extensively test mesh based NoCs. The proposed solution improves previously developed methods since it is based on a NoC physical implementation which allows to investigate the effects induced by several kind of faults thanks to the execution of on-line fault injection within all the network interface and router resources during NoC run-time operations. The solution has been physically implemented on an FPGA platform using a NoC emulation model adopting standard communication protocols. The obtained results demonstrated the effectiveness of the developed solution in term of testability and diagnostic capabilities and make our solutions suitable for testing large scale NoC design. I. Introduction Today, the incessant reduction of the feature size of digital Very Large Scale Integration (VLSI) circuits allows integrating several hundreds of processing elements such as computational cores on a single chip. These resources are increasing demanding high performance communication; therefore traditional solution provided by on-chip buses can no longer sustain this demand. In order to improve the performances and structural weaknesses of traditional buses, Networks on Chip (NoCs) are being adopted. Nevertheless, NoCs are characterized by high performances and low power consumption; one of the open problems that afflict research activities on NoCs is the evaluation of their fault tolerance capabilities. Indeed, as specified in , faults are increasing happening and a very large set of effects must be considered in new generation of NoCs. The larger occurrence of fault is mostly due to the technology scaling of the new chip generations that result more susceptible to fault appearance induced by different phenomena such as single-event upsets, cross-talk, age- related degradation or process variability. Generally, test method of NoC infrastructures address two issues: testing the switch blocks and testing the interconnection segments layout including the logic routers logic resources. Different testing techniques have been proposed in order to evaluate fault effects on NoC. Several NoC test methods have been focused on testing of the functional IP cores using Test Access Mechanism (TAM). Other authors assumed specific fault model for NoC fabric and subsequently adopting it to test the data transportation and the functional blocks. Vice versa, dedicated TAM based on specific on-chip network is adopted by functional test solutions on SoCs multi-cores. The solution of our work improves previously proposed method by developing a flexible and accurate fault injection environment, which can be adopted in order to evaluate the fault tolerance capability of different NoC architectures. The main advantage of the proposed solution rely on the possibility to apply different fault models that can emulate the effective faults affecting NoC architectures, besides the proposed solutions has a full controllability an observability of the NoC under test, since interconnections values and routers functional behaviour can be directly observed during the test operations, feature which is extremely reduced for test solutions applied directly to the manufactured chip, since NoC interconnections are deeply embedded and spread across the chip, therefore adding of probe interconnections results inapplicable. The implementation of our solution relies on the main idea illustrated in Figure 1. The fault injection method we developed is innovative since it is based on single reconfigurable chip, such a Static RAM-based Field Programmable Gate Array (SRAM-based FPGAs) where thanks to a suitable architecture, faults can be injected and evaluated. As illustrated in Figure 1, the architecture consists of two processors: the processor 1 is devoted to the application of the test pattern to the NoC under test while the processor 2 performs the injection of the faults. The execution of the fault injection does not require the insertion of intrusive module into the NoC architecture, since modifying the configuration memory bit of the FPGA device thus physically inserting the desired fault performs the injection. This operation is performed thanks to the availability of the Configuration Access Port which is located internally to the device and can be controlled by a logic core; in our case by the processor 2. Thanks to our solution the fault injection into the NoC architecture can be performed without intrusive modules affecting the real behaviour and with optimal performances, since the working frequency of the NoC is not drastically degraded by the fault insertion. Figure
Read full abstract
Sep 27, 2022
Mohammadreza Amel Solouki + 2
Open Access
